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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003 
0004 
0005 */
0006 
0007 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0008 
0009 #define DRV_NAME    "uli526x"
0010 
0011 #include <linux/module.h>
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/string.h>
0015 #include <linux/timer.h>
0016 #include <linux/errno.h>
0017 #include <linux/ioport.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/pci.h>
0020 #include <linux/init.h>
0021 #include <linux/netdevice.h>
0022 #include <linux/etherdevice.h>
0023 #include <linux/ethtool.h>
0024 #include <linux/skbuff.h>
0025 #include <linux/delay.h>
0026 #include <linux/spinlock.h>
0027 #include <linux/dma-mapping.h>
0028 #include <linux/bitops.h>
0029 
0030 #include <asm/processor.h>
0031 #include <asm/io.h>
0032 #include <asm/dma.h>
0033 #include <linux/uaccess.h>
0034 
0035 #define uw32(reg, val)  iowrite32(val, ioaddr + (reg))
0036 #define ur32(reg)   ioread32(ioaddr + (reg))
0037 
0038 /* Board/System/Debug information/definition ---------------- */
0039 #define PCI_ULI5261_ID  0x526110B9  /* ULi M5261 ID*/
0040 #define PCI_ULI5263_ID  0x526310B9  /* ULi M5263 ID*/
0041 
0042 #define ULI526X_IO_SIZE 0x100
0043 #define TX_DESC_CNT     0x20            /* Allocated Tx descriptors */
0044 #define RX_DESC_CNT     0x30            /* Allocated Rx descriptors */
0045 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2)  /* Max TX packet count */
0046 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3)  /* TX wakeup count */
0047 #define DESC_ALL_CNT    (TX_DESC_CNT + RX_DESC_CNT)
0048 #define TX_BUF_ALLOC    0x600
0049 #define RX_ALLOC_SIZE   0x620
0050 #define ULI526X_RESET    1
0051 #define CR0_DEFAULT     0
0052 #define CR6_DEFAULT     0x22200000
0053 #define CR7_DEFAULT     0x180c1
0054 #define CR15_DEFAULT    0x06            /* TxJabber RxWatchdog */
0055 #define TDES0_ERR_MASK  0x4302          /* TXJT, LC, EC, FUE */
0056 #define MAX_PACKET_SIZE 1514
0057 #define ULI5261_MAX_MULTICAST 14
0058 #define RX_COPY_SIZE    100
0059 #define MAX_CHECK_PACKET 0x8000
0060 
0061 #define ULI526X_10MHF      0
0062 #define ULI526X_100MHF     1
0063 #define ULI526X_10MFD      4
0064 #define ULI526X_100MFD     5
0065 #define ULI526X_AUTO       8
0066 
0067 #define ULI526X_TXTH_72 0x400000    /* TX TH 72 byte */
0068 #define ULI526X_TXTH_96 0x404000    /* TX TH 96 byte */
0069 #define ULI526X_TXTH_128    0x0000      /* TX TH 128 byte */
0070 #define ULI526X_TXTH_256    0x4000      /* TX TH 256 byte */
0071 #define ULI526X_TXTH_512    0x8000      /* TX TH 512 byte */
0072 #define ULI526X_TXTH_1K 0xC000      /* TX TH 1K  byte */
0073 
0074 #define ULI526X_TIMER_WUT  (jiffies + HZ * 1)/* timer wakeup time : 1 second */
0075 #define ULI526X_TX_TIMEOUT ((16*HZ)/2)  /* tx packet time-out time 8 s" */
0076 #define ULI526X_TX_KICK     (4*HZ/2)    /* tx packet Kick-out time 2 s" */
0077 
0078 #define ULI526X_DBUG(dbug_now, msg, value)          \
0079 do {                                \
0080     if (uli526x_debug || (dbug_now))            \
0081         pr_err("%s %lx\n", (msg), (long) (value));  \
0082 } while (0)
0083 
0084 #define SHOW_MEDIA_TYPE(mode)                   \
0085     pr_err("Change Speed to %sMhz %s duplex\n",     \
0086            mode & 1 ? "100" : "10",             \
0087            mode & 4 ? "full" : "half");
0088 
0089 
0090 /* CR9 definition: SROM/MII */
0091 #define CR9_SROM_READ   0x4800
0092 #define CR9_SRCS        0x1
0093 #define CR9_SRCLK       0x2
0094 #define CR9_CRDOUT      0x8
0095 #define SROM_DATA_0     0x0
0096 #define SROM_DATA_1     0x4
0097 #define PHY_DATA_1      0x20000
0098 #define PHY_DATA_0      0x00000
0099 #define MDCLKH          0x10000
0100 
0101 #define PHY_POWER_DOWN  0x800
0102 
0103 #define SROM_V41_CODE   0x14
0104 
0105 /* Structure/enum declaration ------------------------------- */
0106 struct tx_desc {
0107         __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
0108         char *tx_buf_ptr;               /* Data for us */
0109         struct tx_desc *next_tx_desc;
0110 } __attribute__(( aligned(32) ));
0111 
0112 struct rx_desc {
0113     __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
0114     struct sk_buff *rx_skb_ptr; /* Data for us */
0115     struct rx_desc *next_rx_desc;
0116 } __attribute__(( aligned(32) ));
0117 
0118 struct uli526x_board_info {
0119     struct uli_phy_ops {
0120         void (*write)(struct uli526x_board_info *, u8, u8, u16);
0121         u16 (*read)(struct uli526x_board_info *, u8, u8);
0122     } phy;
0123     struct net_device *next_dev;    /* next device */
0124     struct pci_dev *pdev;       /* PCI device */
0125     spinlock_t lock;
0126 
0127     void __iomem *ioaddr;       /* I/O base address */
0128     u32 cr0_data;
0129     u32 cr5_data;
0130     u32 cr6_data;
0131     u32 cr7_data;
0132     u32 cr15_data;
0133 
0134     /* pointer for memory physical address */
0135     dma_addr_t buf_pool_dma_ptr;    /* Tx buffer pool memory */
0136     dma_addr_t buf_pool_dma_start;  /* Tx buffer pool align dword */
0137     dma_addr_t desc_pool_dma_ptr;   /* descriptor pool memory */
0138     dma_addr_t first_tx_desc_dma;
0139     dma_addr_t first_rx_desc_dma;
0140 
0141     /* descriptor pointer */
0142     unsigned char *buf_pool_ptr;    /* Tx buffer pool memory */
0143     unsigned char *buf_pool_start;  /* Tx buffer pool align dword */
0144     unsigned char *desc_pool_ptr;   /* descriptor pool memory */
0145     struct tx_desc *first_tx_desc;
0146     struct tx_desc *tx_insert_ptr;
0147     struct tx_desc *tx_remove_ptr;
0148     struct rx_desc *first_rx_desc;
0149     struct rx_desc *rx_insert_ptr;
0150     struct rx_desc *rx_ready_ptr;   /* packet come pointer */
0151     unsigned long tx_packet_cnt;    /* transmitted packet count */
0152     unsigned long rx_avail_cnt; /* available rx descriptor count */
0153     unsigned long interval_rx_cnt;  /* rx packet count a callback time */
0154 
0155     u16 dbug_cnt;
0156     u16 NIC_capability;     /* NIC media capability */
0157     u16 PHY_reg4;           /* Saved Phyxcer register 4 value */
0158 
0159     u8 media_mode;          /* user specify media mode */
0160     u8 op_mode;         /* real work media mode */
0161     u8 phy_addr;
0162     u8 link_failed;         /* Ever link failed */
0163     u8 wait_reset;          /* Hardware failed, need to reset */
0164     struct timer_list timer;
0165 
0166     /* Driver defined statistic counter */
0167     unsigned long tx_fifo_underrun;
0168     unsigned long tx_loss_carrier;
0169     unsigned long tx_no_carrier;
0170     unsigned long tx_late_collision;
0171     unsigned long tx_excessive_collision;
0172     unsigned long tx_jabber_timeout;
0173     unsigned long reset_count;
0174     unsigned long reset_cr8;
0175     unsigned long reset_fatal;
0176     unsigned long reset_TXtimeout;
0177 
0178     /* NIC SROM data */
0179     unsigned char srom[128];
0180     u8 init;
0181 };
0182 
0183 enum uli526x_offsets {
0184     DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
0185     DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
0186     DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
0187     DCR15 = 0x78
0188 };
0189 
0190 enum uli526x_CR6_bits {
0191     CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
0192     CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
0193     CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
0194 };
0195 
0196 /* Global variable declaration ----------------------------- */
0197 static int uli526x_debug;
0198 static unsigned char uli526x_media_mode = ULI526X_AUTO;
0199 static u32 uli526x_cr6_user_set;
0200 
0201 /* For module input parameter */
0202 static int debug;
0203 static u32 cr6set;
0204 static int mode = 8;
0205 
0206 /* function declaration ------------------------------------- */
0207 static int uli526x_open(struct net_device *);
0208 static netdev_tx_t uli526x_start_xmit(struct sk_buff *,
0209                         struct net_device *);
0210 static int uli526x_stop(struct net_device *);
0211 static void uli526x_set_filter_mode(struct net_device *);
0212 static const struct ethtool_ops netdev_ethtool_ops;
0213 static u16 read_srom_word(struct uli526x_board_info *, int);
0214 static irqreturn_t uli526x_interrupt(int, void *);
0215 #ifdef CONFIG_NET_POLL_CONTROLLER
0216 static void uli526x_poll(struct net_device *dev);
0217 #endif
0218 static void uli526x_descriptor_init(struct net_device *, void __iomem *);
0219 static void allocate_rx_buffer(struct net_device *);
0220 static void update_cr6(u32, void __iomem *);
0221 static void send_filter_frame(struct net_device *, int);
0222 static u16 phy_readby_cr9(struct uli526x_board_info *, u8, u8);
0223 static u16 phy_readby_cr10(struct uli526x_board_info *, u8, u8);
0224 static void phy_writeby_cr9(struct uli526x_board_info *, u8, u8, u16);
0225 static void phy_writeby_cr10(struct uli526x_board_info *, u8, u8, u16);
0226 static void phy_write_1bit(struct uli526x_board_info *db, u32);
0227 static u16 phy_read_1bit(struct uli526x_board_info *db);
0228 static u8 uli526x_sense_speed(struct uli526x_board_info *);
0229 static void uli526x_process_mode(struct uli526x_board_info *);
0230 static void uli526x_timer(struct timer_list *t);
0231 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
0232 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
0233 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
0234 static void uli526x_dynamic_reset(struct net_device *);
0235 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
0236 static void uli526x_init(struct net_device *);
0237 static void uli526x_set_phyxcer(struct uli526x_board_info *);
0238 
0239 static void srom_clk_write(struct uli526x_board_info *db, u32 data)
0240 {
0241     void __iomem *ioaddr = db->ioaddr;
0242 
0243     uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
0244     udelay(5);
0245     uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
0246     udelay(5);
0247     uw32(DCR9, data | CR9_SROM_READ | CR9_SRCS);
0248     udelay(5);
0249 }
0250 
0251 /* ULI526X network board routine ---------------------------- */
0252 
0253 static const struct net_device_ops netdev_ops = {
0254     .ndo_open       = uli526x_open,
0255     .ndo_stop       = uli526x_stop,
0256     .ndo_start_xmit     = uli526x_start_xmit,
0257     .ndo_set_rx_mode    = uli526x_set_filter_mode,
0258     .ndo_set_mac_address    = eth_mac_addr,
0259     .ndo_validate_addr  = eth_validate_addr,
0260 #ifdef CONFIG_NET_POLL_CONTROLLER
0261     .ndo_poll_controller    = uli526x_poll,
0262 #endif
0263 };
0264 
0265 /*
0266  *  Search ULI526X board, allocate space and register it
0267  */
0268 
0269 static int uli526x_init_one(struct pci_dev *pdev,
0270                 const struct pci_device_id *ent)
0271 {
0272     struct uli526x_board_info *db;  /* board information structure */
0273     struct net_device *dev;
0274     void __iomem *ioaddr;
0275     u8 addr[ETH_ALEN];
0276     int i, err;
0277 
0278     ULI526X_DBUG(0, "uli526x_init_one()", 0);
0279 
0280     /* Init network device */
0281     dev = alloc_etherdev(sizeof(*db));
0282     if (dev == NULL)
0283         return -ENOMEM;
0284     SET_NETDEV_DEV(dev, &pdev->dev);
0285 
0286     if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
0287         pr_warn("32-bit PCI DMA not available\n");
0288         err = -ENODEV;
0289         goto err_out_free;
0290     }
0291 
0292     /* Enable Master/IO access, Disable memory access */
0293     err = pci_enable_device(pdev);
0294     if (err)
0295         goto err_out_free;
0296 
0297     if (!pci_resource_start(pdev, 0)) {
0298         pr_err("I/O base is zero\n");
0299         err = -ENODEV;
0300         goto err_out_disable;
0301     }
0302 
0303     if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
0304         pr_err("Allocated I/O size too small\n");
0305         err = -ENODEV;
0306         goto err_out_disable;
0307     }
0308 
0309     err = pci_request_regions(pdev, DRV_NAME);
0310     if (err < 0) {
0311         pr_err("Failed to request PCI regions\n");
0312         goto err_out_disable;
0313     }
0314 
0315     /* Init system & device */
0316     db = netdev_priv(dev);
0317 
0318     /* Allocate Tx/Rx descriptor memory */
0319     err = -ENOMEM;
0320 
0321     db->desc_pool_ptr = dma_alloc_coherent(&pdev->dev,
0322                            sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
0323                            &db->desc_pool_dma_ptr, GFP_KERNEL);
0324     if (!db->desc_pool_ptr)
0325         goto err_out_release;
0326 
0327     db->buf_pool_ptr = dma_alloc_coherent(&pdev->dev,
0328                           TX_BUF_ALLOC * TX_DESC_CNT + 4,
0329                           &db->buf_pool_dma_ptr, GFP_KERNEL);
0330     if (!db->buf_pool_ptr)
0331         goto err_out_free_tx_desc;
0332 
0333     db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
0334     db->first_tx_desc_dma = db->desc_pool_dma_ptr;
0335     db->buf_pool_start = db->buf_pool_ptr;
0336     db->buf_pool_dma_start = db->buf_pool_dma_ptr;
0337 
0338     switch (ent->driver_data) {
0339     case PCI_ULI5263_ID:
0340         db->phy.write   = phy_writeby_cr10;
0341         db->phy.read    = phy_readby_cr10;
0342         break;
0343     default:
0344         db->phy.write   = phy_writeby_cr9;
0345         db->phy.read    = phy_readby_cr9;
0346         break;
0347     }
0348 
0349     /* IO region. */
0350     ioaddr = pci_iomap(pdev, 0, 0);
0351     if (!ioaddr)
0352         goto err_out_free_tx_buf;
0353 
0354     db->ioaddr = ioaddr;
0355     db->pdev = pdev;
0356     db->init = 1;
0357 
0358     pci_set_drvdata(pdev, dev);
0359 
0360     /* Register some necessary functions */
0361     dev->netdev_ops = &netdev_ops;
0362     dev->ethtool_ops = &netdev_ethtool_ops;
0363 
0364     spin_lock_init(&db->lock);
0365 
0366 
0367     /* read 64 word srom data */
0368     for (i = 0; i < 64; i++)
0369         ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db, i));
0370 
0371     /* Set Node address */
0372     if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0)       /* SROM absent, so read MAC address from ID Table */
0373     {
0374         uw32(DCR0, 0x10000);    //Diagnosis mode
0375         uw32(DCR13, 0x1c0); //Reset dianostic pointer port
0376         uw32(DCR14, 0);     //Clear reset port
0377         uw32(DCR14, 0x10);  //Reset ID Table pointer
0378         uw32(DCR14, 0);     //Clear reset port
0379         uw32(DCR13, 0);     //Clear CR13
0380         uw32(DCR13, 0x1b0); //Select ID Table access port
0381         //Read MAC address from CR14
0382         for (i = 0; i < 6; i++)
0383             addr[i] = ur32(DCR14);
0384         //Read end
0385         uw32(DCR13, 0);     //Clear CR13
0386         uw32(DCR0, 0);      //Clear CR0
0387         udelay(10);
0388     }
0389     else        /*Exist SROM*/
0390     {
0391         for (i = 0; i < 6; i++)
0392             addr[i] = db->srom[20 + i];
0393     }
0394     eth_hw_addr_set(dev, addr);
0395 
0396     err = register_netdev (dev);
0397     if (err)
0398         goto err_out_unmap;
0399 
0400     netdev_info(dev, "ULi M%04lx at pci%s, %pM, irq %d\n",
0401             ent->driver_data >> 16, pci_name(pdev),
0402             dev->dev_addr, pdev->irq);
0403 
0404     pci_set_master(pdev);
0405 
0406     return 0;
0407 
0408 err_out_unmap:
0409     pci_iounmap(pdev, db->ioaddr);
0410 err_out_free_tx_buf:
0411     dma_free_coherent(&pdev->dev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
0412               db->buf_pool_ptr, db->buf_pool_dma_ptr);
0413 err_out_free_tx_desc:
0414     dma_free_coherent(&pdev->dev,
0415               sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
0416               db->desc_pool_ptr, db->desc_pool_dma_ptr);
0417 err_out_release:
0418     pci_release_regions(pdev);
0419 err_out_disable:
0420     pci_disable_device(pdev);
0421 err_out_free:
0422     free_netdev(dev);
0423 
0424     return err;
0425 }
0426 
0427 
0428 static void uli526x_remove_one(struct pci_dev *pdev)
0429 {
0430     struct net_device *dev = pci_get_drvdata(pdev);
0431     struct uli526x_board_info *db = netdev_priv(dev);
0432 
0433     unregister_netdev(dev);
0434     pci_iounmap(pdev, db->ioaddr);
0435     dma_free_coherent(&db->pdev->dev,
0436               sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
0437               db->desc_pool_ptr, db->desc_pool_dma_ptr);
0438     dma_free_coherent(&db->pdev->dev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
0439               db->buf_pool_ptr, db->buf_pool_dma_ptr);
0440     pci_release_regions(pdev);
0441     pci_disable_device(pdev);
0442     free_netdev(dev);
0443 }
0444 
0445 
0446 /*
0447  *  Open the interface.
0448  *  The interface is opened whenever "ifconfig" activates it.
0449  */
0450 
0451 static int uli526x_open(struct net_device *dev)
0452 {
0453     int ret;
0454     struct uli526x_board_info *db = netdev_priv(dev);
0455 
0456     ULI526X_DBUG(0, "uli526x_open", 0);
0457 
0458     /* system variable init */
0459     db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
0460     db->tx_packet_cnt = 0;
0461     db->rx_avail_cnt = 0;
0462     db->link_failed = 1;
0463     netif_carrier_off(dev);
0464     db->wait_reset = 0;
0465 
0466     db->NIC_capability = 0xf;   /* All capability*/
0467     db->PHY_reg4 = 0x1e0;
0468 
0469     /* CR6 operation mode decision */
0470     db->cr6_data |= ULI526X_TXTH_256;
0471     db->cr0_data = CR0_DEFAULT;
0472 
0473     /* Initialize ULI526X board */
0474     uli526x_init(dev);
0475 
0476     ret = request_irq(db->pdev->irq, uli526x_interrupt, IRQF_SHARED,
0477               dev->name, dev);
0478     if (ret)
0479         return ret;
0480 
0481     /* Active System Interface */
0482     netif_wake_queue(dev);
0483 
0484     /* set and active a timer process */
0485     timer_setup(&db->timer, uli526x_timer, 0);
0486     db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
0487     add_timer(&db->timer);
0488 
0489     return 0;
0490 }
0491 
0492 
0493 /*  Initialize ULI526X board
0494  *  Reset ULI526X board
0495  *  Initialize TX/Rx descriptor chain structure
0496  *  Send the set-up frame
0497  *  Enable Tx/Rx machine
0498  */
0499 
0500 static void uli526x_init(struct net_device *dev)
0501 {
0502     struct uli526x_board_info *db = netdev_priv(dev);
0503     struct uli_phy_ops *phy = &db->phy;
0504     void __iomem *ioaddr = db->ioaddr;
0505     u8  phy_tmp;
0506     u8  timeout;
0507     u16 phy_reg_reset;
0508 
0509 
0510     ULI526X_DBUG(0, "uli526x_init()", 0);
0511 
0512     /* Reset M526x MAC controller */
0513     uw32(DCR0, ULI526X_RESET);  /* RESET MAC */
0514     udelay(100);
0515     uw32(DCR0, db->cr0_data);
0516     udelay(5);
0517 
0518     /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
0519     db->phy_addr = 1;
0520     for (phy_tmp = 0; phy_tmp < 32; phy_tmp++) {
0521         u16 phy_value;
0522 
0523         phy_value = phy->read(db, phy_tmp, 3);  //peer add
0524         if (phy_value != 0xffff && phy_value != 0) {
0525             db->phy_addr = phy_tmp;
0526             break;
0527         }
0528     }
0529 
0530     if (phy_tmp == 32)
0531         pr_warn("Can not find the phy address!!!\n");
0532     /* Parser SROM and media mode */
0533     db->media_mode = uli526x_media_mode;
0534 
0535     /* phyxcer capability setting */
0536     phy_reg_reset = phy->read(db, db->phy_addr, 0);
0537     phy_reg_reset = (phy_reg_reset | 0x8000);
0538     phy->write(db, db->phy_addr, 0, phy_reg_reset);
0539 
0540     /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
0541      * functions") or phy data sheet for details on phy reset
0542      */
0543     udelay(500);
0544     timeout = 10;
0545     while (timeout-- && phy->read(db, db->phy_addr, 0) & 0x8000)
0546         udelay(100);
0547 
0548     /* Process Phyxcer Media Mode */
0549     uli526x_set_phyxcer(db);
0550 
0551     /* Media Mode Process */
0552     if ( !(db->media_mode & ULI526X_AUTO) )
0553         db->op_mode = db->media_mode;       /* Force Mode */
0554 
0555     /* Initialize Transmit/Receive descriptor and CR3/4 */
0556     uli526x_descriptor_init(dev, ioaddr);
0557 
0558     /* Init CR6 to program M526X operation */
0559     update_cr6(db->cr6_data, ioaddr);
0560 
0561     /* Send setup frame */
0562     send_filter_frame(dev, netdev_mc_count(dev));   /* M5261/M5263 */
0563 
0564     /* Init CR7, interrupt active bit */
0565     db->cr7_data = CR7_DEFAULT;
0566     uw32(DCR7, db->cr7_data);
0567 
0568     /* Init CR15, Tx jabber and Rx watchdog timer */
0569     uw32(DCR15, db->cr15_data);
0570 
0571     /* Enable ULI526X Tx/Rx function */
0572     db->cr6_data |= CR6_RXSC | CR6_TXSC;
0573     update_cr6(db->cr6_data, ioaddr);
0574 }
0575 
0576 
0577 /*
0578  *  Hardware start transmission.
0579  *  Send a packet to media from the upper layer.
0580  */
0581 
0582 static netdev_tx_t uli526x_start_xmit(struct sk_buff *skb,
0583                         struct net_device *dev)
0584 {
0585     struct uli526x_board_info *db = netdev_priv(dev);
0586     void __iomem *ioaddr = db->ioaddr;
0587     struct tx_desc *txptr;
0588     unsigned long flags;
0589 
0590     ULI526X_DBUG(0, "uli526x_start_xmit", 0);
0591 
0592     /* Resource flag check */
0593     netif_stop_queue(dev);
0594 
0595     /* Too large packet check */
0596     if (skb->len > MAX_PACKET_SIZE) {
0597         netdev_err(dev, "big packet = %d\n", (u16)skb->len);
0598         dev_kfree_skb_any(skb);
0599         return NETDEV_TX_OK;
0600     }
0601 
0602     spin_lock_irqsave(&db->lock, flags);
0603 
0604     /* No Tx resource check, it never happen nromally */
0605     if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
0606         spin_unlock_irqrestore(&db->lock, flags);
0607         netdev_err(dev, "No Tx resource %ld\n", db->tx_packet_cnt);
0608         return NETDEV_TX_BUSY;
0609     }
0610 
0611     /* Disable NIC interrupt */
0612     uw32(DCR7, 0);
0613 
0614     /* transmit this packet */
0615     txptr = db->tx_insert_ptr;
0616     skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
0617     txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
0618 
0619     /* Point to next transmit free descriptor */
0620     db->tx_insert_ptr = txptr->next_tx_desc;
0621 
0622     /* Transmit Packet Process */
0623     if (db->tx_packet_cnt < TX_DESC_CNT) {
0624         txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
0625         db->tx_packet_cnt++;            /* Ready to send */
0626         uw32(DCR1, 0x1);            /* Issue Tx polling */
0627         netif_trans_update(dev);        /* saved time stamp */
0628     }
0629 
0630     /* Tx resource check */
0631     if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
0632         netif_wake_queue(dev);
0633 
0634     /* Restore CR7 to enable interrupt */
0635     spin_unlock_irqrestore(&db->lock, flags);
0636     uw32(DCR7, db->cr7_data);
0637 
0638     /* free this SKB */
0639     dev_consume_skb_any(skb);
0640 
0641     return NETDEV_TX_OK;
0642 }
0643 
0644 
0645 /*
0646  *  Stop the interface.
0647  *  The interface is stopped when it is brought.
0648  */
0649 
0650 static int uli526x_stop(struct net_device *dev)
0651 {
0652     struct uli526x_board_info *db = netdev_priv(dev);
0653     void __iomem *ioaddr = db->ioaddr;
0654 
0655     /* disable system */
0656     netif_stop_queue(dev);
0657 
0658     /* deleted timer */
0659     del_timer_sync(&db->timer);
0660 
0661     /* Reset & stop ULI526X board */
0662     uw32(DCR0, ULI526X_RESET);
0663     udelay(5);
0664     db->phy.write(db, db->phy_addr, 0, 0x8000);
0665 
0666     /* free interrupt */
0667     free_irq(db->pdev->irq, dev);
0668 
0669     /* free allocated rx buffer */
0670     uli526x_free_rxbuffer(db);
0671 
0672     return 0;
0673 }
0674 
0675 
0676 /*
0677  *  M5261/M5263 insterrupt handler
0678  *  receive the packet to upper layer, free the transmitted packet
0679  */
0680 
0681 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
0682 {
0683     struct net_device *dev = dev_id;
0684     struct uli526x_board_info *db = netdev_priv(dev);
0685     void __iomem *ioaddr = db->ioaddr;
0686     unsigned long flags;
0687 
0688     spin_lock_irqsave(&db->lock, flags);
0689     uw32(DCR7, 0);
0690 
0691     /* Got ULI526X status */
0692     db->cr5_data = ur32(DCR5);
0693     uw32(DCR5, db->cr5_data);
0694     if ( !(db->cr5_data & 0x180c1) ) {
0695         /* Restore CR7 to enable interrupt mask */
0696         uw32(DCR7, db->cr7_data);
0697         spin_unlock_irqrestore(&db->lock, flags);
0698         return IRQ_HANDLED;
0699     }
0700 
0701     /* Check system status */
0702     if (db->cr5_data & 0x2000) {
0703         /* system bus error happen */
0704         ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
0705         db->reset_fatal++;
0706         db->wait_reset = 1; /* Need to RESET */
0707         spin_unlock_irqrestore(&db->lock, flags);
0708         return IRQ_HANDLED;
0709     }
0710 
0711      /* Received the coming packet */
0712     if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
0713         uli526x_rx_packet(dev, db);
0714 
0715     /* reallocate rx descriptor buffer */
0716     if (db->rx_avail_cnt<RX_DESC_CNT)
0717         allocate_rx_buffer(dev);
0718 
0719     /* Free the transmitted descriptor */
0720     if ( db->cr5_data & 0x01)
0721         uli526x_free_tx_pkt(dev, db);
0722 
0723     /* Restore CR7 to enable interrupt mask */
0724     uw32(DCR7, db->cr7_data);
0725 
0726     spin_unlock_irqrestore(&db->lock, flags);
0727     return IRQ_HANDLED;
0728 }
0729 
0730 #ifdef CONFIG_NET_POLL_CONTROLLER
0731 static void uli526x_poll(struct net_device *dev)
0732 {
0733     struct uli526x_board_info *db = netdev_priv(dev);
0734 
0735     /* ISR grabs the irqsave lock, so this should be safe */
0736     uli526x_interrupt(db->pdev->irq, dev);
0737 }
0738 #endif
0739 
0740 /*
0741  *  Free TX resource after TX complete
0742  */
0743 
0744 static void uli526x_free_tx_pkt(struct net_device *dev,
0745                 struct uli526x_board_info * db)
0746 {
0747     struct tx_desc *txptr;
0748     u32 tdes0;
0749 
0750     txptr = db->tx_remove_ptr;
0751     while(db->tx_packet_cnt) {
0752         tdes0 = le32_to_cpu(txptr->tdes0);
0753         if (tdes0 & 0x80000000)
0754             break;
0755 
0756         /* A packet sent completed */
0757         db->tx_packet_cnt--;
0758         dev->stats.tx_packets++;
0759 
0760         /* Transmit statistic counter */
0761         if ( tdes0 != 0x7fffffff ) {
0762             dev->stats.collisions += (tdes0 >> 3) & 0xf;
0763             dev->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
0764             if (tdes0 & TDES0_ERR_MASK) {
0765                 dev->stats.tx_errors++;
0766                 if (tdes0 & 0x0002) {   /* UnderRun */
0767                     db->tx_fifo_underrun++;
0768                     if ( !(db->cr6_data & CR6_SFT) ) {
0769                         db->cr6_data = db->cr6_data | CR6_SFT;
0770                         update_cr6(db->cr6_data, db->ioaddr);
0771                     }
0772                 }
0773                 if (tdes0 & 0x0100)
0774                     db->tx_excessive_collision++;
0775                 if (tdes0 & 0x0200)
0776                     db->tx_late_collision++;
0777                 if (tdes0 & 0x0400)
0778                     db->tx_no_carrier++;
0779                 if (tdes0 & 0x0800)
0780                     db->tx_loss_carrier++;
0781                 if (tdes0 & 0x4000)
0782                     db->tx_jabber_timeout++;
0783             }
0784         }
0785 
0786         txptr = txptr->next_tx_desc;
0787     }/* End of while */
0788 
0789     /* Update TX remove pointer to next */
0790     db->tx_remove_ptr = txptr;
0791 
0792     /* Resource available check */
0793     if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
0794         netif_wake_queue(dev);  /* Active upper layer, send again */
0795 }
0796 
0797 
0798 /*
0799  *  Receive the come packet and pass to upper layer
0800  */
0801 
0802 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
0803 {
0804     struct rx_desc *rxptr;
0805     struct sk_buff *skb;
0806     int rxlen;
0807     u32 rdes0;
0808 
0809     rxptr = db->rx_ready_ptr;
0810 
0811     while(db->rx_avail_cnt) {
0812         rdes0 = le32_to_cpu(rxptr->rdes0);
0813         if (rdes0 & 0x80000000) /* packet owner check */
0814         {
0815             break;
0816         }
0817 
0818         db->rx_avail_cnt--;
0819         db->interval_rx_cnt++;
0820 
0821         dma_unmap_single(&db->pdev->dev, le32_to_cpu(rxptr->rdes2),
0822                  RX_ALLOC_SIZE, DMA_FROM_DEVICE);
0823         if ( (rdes0 & 0x300) != 0x300) {
0824             /* A packet without First/Last flag */
0825             /* reuse this SKB */
0826             ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
0827             uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
0828         } else {
0829             /* A packet with First/Last flag */
0830             rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
0831 
0832             /* error summary bit check */
0833             if (rdes0 & 0x8000) {
0834                 /* This is a error packet */
0835                 dev->stats.rx_errors++;
0836                 if (rdes0 & 1)
0837                     dev->stats.rx_fifo_errors++;
0838                 if (rdes0 & 2)
0839                     dev->stats.rx_crc_errors++;
0840                 if (rdes0 & 0x80)
0841                     dev->stats.rx_length_errors++;
0842             }
0843 
0844             if ( !(rdes0 & 0x8000) ||
0845                 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
0846                 struct sk_buff *new_skb = NULL;
0847 
0848                 skb = rxptr->rx_skb_ptr;
0849 
0850                 /* Good packet, send to upper layer */
0851                 /* Shorst packet used new SKB */
0852                 if ((rxlen < RX_COPY_SIZE) &&
0853                     (((new_skb = netdev_alloc_skb(dev, rxlen + 2)) != NULL))) {
0854                     skb = new_skb;
0855                     /* size less than COPY_SIZE, allocate a rxlen SKB */
0856                     skb_reserve(skb, 2); /* 16byte align */
0857                     skb_put_data(skb,
0858                              skb_tail_pointer(rxptr->rx_skb_ptr),
0859                              rxlen);
0860                     uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
0861                 } else
0862                     skb_put(skb, rxlen);
0863 
0864                 skb->protocol = eth_type_trans(skb, dev);
0865                 netif_rx(skb);
0866                 dev->stats.rx_packets++;
0867                 dev->stats.rx_bytes += rxlen;
0868 
0869             } else {
0870                 /* Reuse SKB buffer when the packet is error */
0871                 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
0872                 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
0873             }
0874         }
0875 
0876         rxptr = rxptr->next_rx_desc;
0877     }
0878 
0879     db->rx_ready_ptr = rxptr;
0880 }
0881 
0882 
0883 /*
0884  * Set ULI526X multicast address
0885  */
0886 
0887 static void uli526x_set_filter_mode(struct net_device * dev)
0888 {
0889     struct uli526x_board_info *db = netdev_priv(dev);
0890     unsigned long flags;
0891 
0892     ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
0893     spin_lock_irqsave(&db->lock, flags);
0894 
0895     if (dev->flags & IFF_PROMISC) {
0896         ULI526X_DBUG(0, "Enable PROM Mode", 0);
0897         db->cr6_data |= CR6_PM | CR6_PBF;
0898         update_cr6(db->cr6_data, db->ioaddr);
0899         spin_unlock_irqrestore(&db->lock, flags);
0900         return;
0901     }
0902 
0903     if (dev->flags & IFF_ALLMULTI ||
0904         netdev_mc_count(dev) > ULI5261_MAX_MULTICAST) {
0905         ULI526X_DBUG(0, "Pass all multicast address",
0906                  netdev_mc_count(dev));
0907         db->cr6_data &= ~(CR6_PM | CR6_PBF);
0908         db->cr6_data |= CR6_PAM;
0909         spin_unlock_irqrestore(&db->lock, flags);
0910         return;
0911     }
0912 
0913     ULI526X_DBUG(0, "Set multicast address", netdev_mc_count(dev));
0914     send_filter_frame(dev, netdev_mc_count(dev));   /* M5261/M5263 */
0915     spin_unlock_irqrestore(&db->lock, flags);
0916 }
0917 
0918 static void
0919 ULi_ethtool_get_link_ksettings(struct uli526x_board_info *db,
0920                    struct ethtool_link_ksettings *cmd)
0921 {
0922     u32 supported, advertising;
0923 
0924     supported = (SUPPORTED_10baseT_Half |
0925                        SUPPORTED_10baseT_Full |
0926                        SUPPORTED_100baseT_Half |
0927                        SUPPORTED_100baseT_Full |
0928                        SUPPORTED_Autoneg |
0929                        SUPPORTED_MII);
0930 
0931     advertising = (ADVERTISED_10baseT_Half |
0932                        ADVERTISED_10baseT_Full |
0933                        ADVERTISED_100baseT_Half |
0934                        ADVERTISED_100baseT_Full |
0935                        ADVERTISED_Autoneg |
0936                        ADVERTISED_MII);
0937 
0938     ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
0939                         supported);
0940     ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
0941                         advertising);
0942 
0943     cmd->base.port = PORT_MII;
0944     cmd->base.phy_address = db->phy_addr;
0945 
0946     cmd->base.speed = SPEED_10;
0947     cmd->base.duplex = DUPLEX_HALF;
0948 
0949     if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
0950     {
0951         cmd->base.speed = SPEED_100;
0952     }
0953     if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
0954     {
0955         cmd->base.duplex = DUPLEX_FULL;
0956     }
0957     if(db->link_failed)
0958     {
0959         cmd->base.speed = SPEED_UNKNOWN;
0960         cmd->base.duplex = DUPLEX_UNKNOWN;
0961     }
0962 
0963     if (db->media_mode & ULI526X_AUTO)
0964     {
0965         cmd->base.autoneg = AUTONEG_ENABLE;
0966     }
0967 }
0968 
0969 static void netdev_get_drvinfo(struct net_device *dev,
0970                    struct ethtool_drvinfo *info)
0971 {
0972     struct uli526x_board_info *np = netdev_priv(dev);
0973 
0974     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
0975     strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
0976 }
0977 
0978 static int netdev_get_link_ksettings(struct net_device *dev,
0979                      struct ethtool_link_ksettings *cmd)
0980 {
0981     struct uli526x_board_info *np = netdev_priv(dev);
0982 
0983     ULi_ethtool_get_link_ksettings(np, cmd);
0984 
0985     return 0;
0986 }
0987 
0988 static u32 netdev_get_link(struct net_device *dev) {
0989     struct uli526x_board_info *np = netdev_priv(dev);
0990 
0991     if(np->link_failed)
0992         return 0;
0993     else
0994         return 1;
0995 }
0996 
0997 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
0998 {
0999     wol->supported = WAKE_PHY | WAKE_MAGIC;
1000     wol->wolopts = 0;
1001 }
1002 
1003 static const struct ethtool_ops netdev_ethtool_ops = {
1004     .get_drvinfo        = netdev_get_drvinfo,
1005     .get_link       = netdev_get_link,
1006     .get_wol        = uli526x_get_wol,
1007     .get_link_ksettings = netdev_get_link_ksettings,
1008 };
1009 
1010 /*
1011  *  A periodic timer routine
1012  *  Dynamic media sense, allocate Rx buffer...
1013  */
1014 
1015 static void uli526x_timer(struct timer_list *t)
1016 {
1017     struct uli526x_board_info *db = from_timer(db, t, timer);
1018     struct net_device *dev = pci_get_drvdata(db->pdev);
1019     struct uli_phy_ops *phy = &db->phy;
1020     void __iomem *ioaddr = db->ioaddr;
1021     unsigned long flags;
1022     u8 tmp_cr12 = 0;
1023     u32 tmp_cr8;
1024 
1025     //ULI526X_DBUG(0, "uli526x_timer()", 0);
1026     spin_lock_irqsave(&db->lock, flags);
1027 
1028 
1029     /* Dynamic reset ULI526X : system error or transmit time-out */
1030     tmp_cr8 = ur32(DCR8);
1031     if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1032         db->reset_cr8++;
1033         db->wait_reset = 1;
1034     }
1035     db->interval_rx_cnt = 0;
1036 
1037     /* TX polling kick monitor */
1038     if ( db->tx_packet_cnt &&
1039          time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_KICK) ) {
1040         uw32(DCR1, 0x1);   // Tx polling again
1041 
1042         // TX Timeout
1043         if ( time_after(jiffies, dev_trans_start(dev) + ULI526X_TX_TIMEOUT) ) {
1044             db->reset_TXtimeout++;
1045             db->wait_reset = 1;
1046             netdev_err(dev, " Tx timeout - resetting\n");
1047         }
1048     }
1049 
1050     if (db->wait_reset) {
1051         ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1052         db->reset_count++;
1053         uli526x_dynamic_reset(dev);
1054         db->timer.expires = ULI526X_TIMER_WUT;
1055         add_timer(&db->timer);
1056         spin_unlock_irqrestore(&db->lock, flags);
1057         return;
1058     }
1059 
1060     /* Link status check, Dynamic media type change */
1061     if ((phy->read(db, db->phy_addr, 5) & 0x01e0)!=0)
1062         tmp_cr12 = 3;
1063 
1064     if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1065         /* Link Failed */
1066         ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1067         netif_carrier_off(dev);
1068         netdev_info(dev, "NIC Link is Down\n");
1069         db->link_failed = 1;
1070 
1071         /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1072         /* AUTO don't need */
1073         if ( !(db->media_mode & 0x8) )
1074             phy->write(db, db->phy_addr, 0, 0x1000);
1075 
1076         /* AUTO mode, if INT phyxcer link failed, select EXT device */
1077         if (db->media_mode & ULI526X_AUTO) {
1078             db->cr6_data&=~0x00000200;  /* bit9=0, HD mode */
1079             update_cr6(db->cr6_data, db->ioaddr);
1080         }
1081     } else
1082         if ((tmp_cr12 & 0x3) && db->link_failed) {
1083             ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1084             db->link_failed = 0;
1085 
1086             /* Auto Sense Speed */
1087             if ( (db->media_mode & ULI526X_AUTO) &&
1088                 uli526x_sense_speed(db) )
1089                 db->link_failed = 1;
1090             uli526x_process_mode(db);
1091 
1092             if(db->link_failed==0)
1093             {
1094                 netdev_info(dev, "NIC Link is Up %d Mbps %s duplex\n",
1095                         (db->op_mode == ULI526X_100MHF ||
1096                          db->op_mode == ULI526X_100MFD)
1097                         ? 100 : 10,
1098                         (db->op_mode == ULI526X_10MFD ||
1099                          db->op_mode == ULI526X_100MFD)
1100                         ? "Full" : "Half");
1101                 netif_carrier_on(dev);
1102             }
1103             /* SHOW_MEDIA_TYPE(db->op_mode); */
1104         }
1105         else if(!(tmp_cr12 & 0x3) && db->link_failed)
1106         {
1107             if(db->init==1)
1108             {
1109                 netdev_info(dev, "NIC Link is Down\n");
1110                 netif_carrier_off(dev);
1111             }
1112         }
1113     db->init = 0;
1114 
1115     /* Timer active again */
1116     db->timer.expires = ULI526X_TIMER_WUT;
1117     add_timer(&db->timer);
1118     spin_unlock_irqrestore(&db->lock, flags);
1119 }
1120 
1121 
1122 /*
1123  *  Stop ULI526X board
1124  *  Free Tx/Rx allocated memory
1125  *  Init system variable
1126  */
1127 
1128 static void uli526x_reset_prepare(struct net_device *dev)
1129 {
1130     struct uli526x_board_info *db = netdev_priv(dev);
1131     void __iomem *ioaddr = db->ioaddr;
1132 
1133     /* Sopt MAC controller */
1134     db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1135     update_cr6(db->cr6_data, ioaddr);
1136     uw32(DCR7, 0);              /* Disable Interrupt */
1137     uw32(DCR5, ur32(DCR5));
1138 
1139     /* Disable upper layer interface */
1140     netif_stop_queue(dev);
1141 
1142     /* Free Rx Allocate buffer */
1143     uli526x_free_rxbuffer(db);
1144 
1145     /* system variable init */
1146     db->tx_packet_cnt = 0;
1147     db->rx_avail_cnt = 0;
1148     db->link_failed = 1;
1149     db->init=1;
1150     db->wait_reset = 0;
1151 }
1152 
1153 
1154 /*
1155  *  Dynamic reset the ULI526X board
1156  *  Stop ULI526X board
1157  *  Free Tx/Rx allocated memory
1158  *  Reset ULI526X board
1159  *  Re-initialize ULI526X board
1160  */
1161 
1162 static void uli526x_dynamic_reset(struct net_device *dev)
1163 {
1164     ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1165 
1166     uli526x_reset_prepare(dev);
1167 
1168     /* Re-initialize ULI526X board */
1169     uli526x_init(dev);
1170 
1171     /* Restart upper layer interface */
1172     netif_wake_queue(dev);
1173 }
1174 
1175 /*
1176  *  Suspend the interface.
1177  */
1178 
1179 static int __maybe_unused uli526x_suspend(struct device *dev_d)
1180 {
1181     struct net_device *dev = dev_get_drvdata(dev_d);
1182 
1183     ULI526X_DBUG(0, "uli526x_suspend", 0);
1184 
1185     if (!netif_running(dev))
1186         return 0;
1187 
1188     netif_device_detach(dev);
1189     uli526x_reset_prepare(dev);
1190 
1191     device_set_wakeup_enable(dev_d, 0);
1192 
1193     return 0;
1194 }
1195 
1196 /*
1197  *  Resume the interface.
1198  */
1199 
1200 static int __maybe_unused uli526x_resume(struct device *dev_d)
1201 {
1202     struct net_device *dev = dev_get_drvdata(dev_d);
1203 
1204     ULI526X_DBUG(0, "uli526x_resume", 0);
1205 
1206 
1207     if (!netif_running(dev))
1208         return 0;
1209 
1210     netif_device_attach(dev);
1211     /* Re-initialize ULI526X board */
1212     uli526x_init(dev);
1213     /* Restart upper layer interface */
1214     netif_wake_queue(dev);
1215 
1216     return 0;
1217 }
1218 
1219 /*
1220  *  free all allocated rx buffer
1221  */
1222 
1223 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1224 {
1225     ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1226 
1227     /* free allocated rx buffer */
1228     while (db->rx_avail_cnt) {
1229         dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1230         db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1231         db->rx_avail_cnt--;
1232     }
1233 }
1234 
1235 
1236 /*
1237  *  Reuse the SK buffer
1238  */
1239 
1240 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1241 {
1242     struct rx_desc *rxptr = db->rx_insert_ptr;
1243 
1244     if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1245         rxptr->rx_skb_ptr = skb;
1246         rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb_tail_pointer(skb),
1247                               RX_ALLOC_SIZE, DMA_FROM_DEVICE));
1248         wmb();
1249         rxptr->rdes0 = cpu_to_le32(0x80000000);
1250         db->rx_avail_cnt++;
1251         db->rx_insert_ptr = rxptr->next_rx_desc;
1252     } else
1253         ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1254 }
1255 
1256 
1257 /*
1258  *  Initialize transmit/Receive descriptor
1259  *  Using Chain structure, and allocate Tx/Rx buffer
1260  */
1261 
1262 static void uli526x_descriptor_init(struct net_device *dev, void __iomem *ioaddr)
1263 {
1264     struct uli526x_board_info *db = netdev_priv(dev);
1265     struct tx_desc *tmp_tx;
1266     struct rx_desc *tmp_rx;
1267     unsigned char *tmp_buf;
1268     dma_addr_t tmp_tx_dma, tmp_rx_dma;
1269     dma_addr_t tmp_buf_dma;
1270     int i;
1271 
1272     ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1273 
1274     /* tx descriptor start pointer */
1275     db->tx_insert_ptr = db->first_tx_desc;
1276     db->tx_remove_ptr = db->first_tx_desc;
1277     uw32(DCR4, db->first_tx_desc_dma);  /* TX DESC address */
1278 
1279     /* rx descriptor start pointer */
1280     db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1281     db->first_rx_desc_dma =  db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1282     db->rx_insert_ptr = db->first_rx_desc;
1283     db->rx_ready_ptr = db->first_rx_desc;
1284     uw32(DCR3, db->first_rx_desc_dma);  /* RX DESC address */
1285 
1286     /* Init Transmit chain */
1287     tmp_buf = db->buf_pool_start;
1288     tmp_buf_dma = db->buf_pool_dma_start;
1289     tmp_tx_dma = db->first_tx_desc_dma;
1290     for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1291         tmp_tx->tx_buf_ptr = tmp_buf;
1292         tmp_tx->tdes0 = cpu_to_le32(0);
1293         tmp_tx->tdes1 = cpu_to_le32(0x81000000);    /* IC, chain */
1294         tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1295         tmp_tx_dma += sizeof(struct tx_desc);
1296         tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1297         tmp_tx->next_tx_desc = tmp_tx + 1;
1298         tmp_buf = tmp_buf + TX_BUF_ALLOC;
1299         tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1300     }
1301     (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1302     tmp_tx->next_tx_desc = db->first_tx_desc;
1303 
1304      /* Init Receive descriptor chain */
1305     tmp_rx_dma=db->first_rx_desc_dma;
1306     for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1307         tmp_rx->rdes0 = cpu_to_le32(0);
1308         tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1309         tmp_rx_dma += sizeof(struct rx_desc);
1310         tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1311         tmp_rx->next_rx_desc = tmp_rx + 1;
1312     }
1313     (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1314     tmp_rx->next_rx_desc = db->first_rx_desc;
1315 
1316     /* pre-allocate Rx buffer */
1317     allocate_rx_buffer(dev);
1318 }
1319 
1320 
1321 /*
1322  *  Update CR6 value
1323  *  Firstly stop ULI526X, then written value and start
1324  */
1325 static void update_cr6(u32 cr6_data, void __iomem *ioaddr)
1326 {
1327     uw32(DCR6, cr6_data);
1328     udelay(5);
1329 }
1330 
1331 
1332 /*
1333  *  Send a setup frame for M5261/M5263
1334  *  This setup frame initialize ULI526X address filter mode
1335  */
1336 
1337 #ifdef __BIG_ENDIAN
1338 #define FLT_SHIFT 16
1339 #else
1340 #define FLT_SHIFT 0
1341 #endif
1342 
1343 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1344 {
1345     struct uli526x_board_info *db = netdev_priv(dev);
1346     void __iomem *ioaddr = db->ioaddr;
1347     struct netdev_hw_addr *ha;
1348     struct tx_desc *txptr;
1349     const u16 * addrptr;
1350     u32 * suptr;
1351     int i;
1352 
1353     ULI526X_DBUG(0, "send_filter_frame()", 0);
1354 
1355     txptr = db->tx_insert_ptr;
1356     suptr = (u32 *) txptr->tx_buf_ptr;
1357 
1358     /* Node address */
1359     addrptr = (const u16 *) dev->dev_addr;
1360     *suptr++ = addrptr[0] << FLT_SHIFT;
1361     *suptr++ = addrptr[1] << FLT_SHIFT;
1362     *suptr++ = addrptr[2] << FLT_SHIFT;
1363 
1364     /* broadcast address */
1365     *suptr++ = 0xffff << FLT_SHIFT;
1366     *suptr++ = 0xffff << FLT_SHIFT;
1367     *suptr++ = 0xffff << FLT_SHIFT;
1368 
1369     /* fit the multicast address */
1370     netdev_for_each_mc_addr(ha, dev) {
1371         addrptr = (u16 *) ha->addr;
1372         *suptr++ = addrptr[0] << FLT_SHIFT;
1373         *suptr++ = addrptr[1] << FLT_SHIFT;
1374         *suptr++ = addrptr[2] << FLT_SHIFT;
1375     }
1376 
1377     for (i = netdev_mc_count(dev); i < 14; i++) {
1378         *suptr++ = 0xffff << FLT_SHIFT;
1379         *suptr++ = 0xffff << FLT_SHIFT;
1380         *suptr++ = 0xffff << FLT_SHIFT;
1381     }
1382 
1383     /* prepare the setup frame */
1384     db->tx_insert_ptr = txptr->next_tx_desc;
1385     txptr->tdes1 = cpu_to_le32(0x890000c0);
1386 
1387     /* Resource Check and Send the setup packet */
1388     if (db->tx_packet_cnt < TX_DESC_CNT) {
1389         /* Resource Empty */
1390         db->tx_packet_cnt++;
1391         txptr->tdes0 = cpu_to_le32(0x80000000);
1392         update_cr6(db->cr6_data | 0x2000, ioaddr);
1393         uw32(DCR1, 0x1);    /* Issue Tx polling */
1394         update_cr6(db->cr6_data, ioaddr);
1395         netif_trans_update(dev);
1396     } else
1397         netdev_err(dev, "No Tx resource - Send_filter_frame!\n");
1398 }
1399 
1400 
1401 /*
1402  *  Allocate rx buffer,
1403  *  As possible as allocate maxiumn Rx buffer
1404  */
1405 
1406 static void allocate_rx_buffer(struct net_device *dev)
1407 {
1408     struct uli526x_board_info *db = netdev_priv(dev);
1409     struct rx_desc *rxptr;
1410     struct sk_buff *skb;
1411 
1412     rxptr = db->rx_insert_ptr;
1413 
1414     while(db->rx_avail_cnt < RX_DESC_CNT) {
1415         skb = netdev_alloc_skb(dev, RX_ALLOC_SIZE);
1416         if (skb == NULL)
1417             break;
1418         rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1419         rxptr->rdes2 = cpu_to_le32(dma_map_single(&db->pdev->dev, skb_tail_pointer(skb),
1420                               RX_ALLOC_SIZE, DMA_FROM_DEVICE));
1421         wmb();
1422         rxptr->rdes0 = cpu_to_le32(0x80000000);
1423         rxptr = rxptr->next_rx_desc;
1424         db->rx_avail_cnt++;
1425     }
1426 
1427     db->rx_insert_ptr = rxptr;
1428 }
1429 
1430 
1431 /*
1432  *  Read one word data from the serial ROM
1433  */
1434 
1435 static u16 read_srom_word(struct uli526x_board_info *db, int offset)
1436 {
1437     void __iomem *ioaddr = db->ioaddr;
1438     u16 srom_data = 0;
1439     int i;
1440 
1441     uw32(DCR9, CR9_SROM_READ);
1442     uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1443 
1444     /* Send the Read Command 110b */
1445     srom_clk_write(db, SROM_DATA_1);
1446     srom_clk_write(db, SROM_DATA_1);
1447     srom_clk_write(db, SROM_DATA_0);
1448 
1449     /* Send the offset */
1450     for (i = 5; i >= 0; i--) {
1451         srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1452         srom_clk_write(db, srom_data);
1453     }
1454 
1455     uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1456 
1457     for (i = 16; i > 0; i--) {
1458         uw32(DCR9, CR9_SROM_READ | CR9_SRCS | CR9_SRCLK);
1459         udelay(5);
1460         srom_data = (srom_data << 1) |
1461                 ((ur32(DCR9) & CR9_CRDOUT) ? 1 : 0);
1462         uw32(DCR9, CR9_SROM_READ | CR9_SRCS);
1463         udelay(5);
1464     }
1465 
1466     uw32(DCR9, CR9_SROM_READ);
1467     return srom_data;
1468 }
1469 
1470 
1471 /*
1472  *  Auto sense the media mode
1473  */
1474 
1475 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1476 {
1477     struct uli_phy_ops *phy = &db->phy;
1478     u8 ErrFlag = 0;
1479     u16 phy_mode;
1480 
1481     phy_mode = phy->read(db, db->phy_addr, 1);
1482     phy_mode = phy->read(db, db->phy_addr, 1);
1483 
1484     if ( (phy_mode & 0x24) == 0x24 ) {
1485 
1486         phy_mode = ((phy->read(db, db->phy_addr, 5) & 0x01e0)<<7);
1487         if(phy_mode&0x8000)
1488             phy_mode = 0x8000;
1489         else if(phy_mode&0x4000)
1490             phy_mode = 0x4000;
1491         else if(phy_mode&0x2000)
1492             phy_mode = 0x2000;
1493         else
1494             phy_mode = 0x1000;
1495 
1496         switch (phy_mode) {
1497         case 0x1000: db->op_mode = ULI526X_10MHF; break;
1498         case 0x2000: db->op_mode = ULI526X_10MFD; break;
1499         case 0x4000: db->op_mode = ULI526X_100MHF; break;
1500         case 0x8000: db->op_mode = ULI526X_100MFD; break;
1501         default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1502         }
1503     } else {
1504         db->op_mode = ULI526X_10MHF;
1505         ULI526X_DBUG(0, "Link Failed :", phy_mode);
1506         ErrFlag = 1;
1507     }
1508 
1509     return ErrFlag;
1510 }
1511 
1512 
1513 /*
1514  *  Set 10/100 phyxcer capability
1515  *  AUTO mode : phyxcer register4 is NIC capability
1516  *  Force mode: phyxcer register4 is the force media
1517  */
1518 
1519 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1520 {
1521     struct uli_phy_ops *phy = &db->phy;
1522     u16 phy_reg;
1523 
1524     /* Phyxcer capability setting */
1525     phy_reg = phy->read(db, db->phy_addr, 4) & ~0x01e0;
1526 
1527     if (db->media_mode & ULI526X_AUTO) {
1528         /* AUTO Mode */
1529         phy_reg |= db->PHY_reg4;
1530     } else {
1531         /* Force Mode */
1532         switch(db->media_mode) {
1533         case ULI526X_10MHF: phy_reg |= 0x20; break;
1534         case ULI526X_10MFD: phy_reg |= 0x40; break;
1535         case ULI526X_100MHF: phy_reg |= 0x80; break;
1536         case ULI526X_100MFD: phy_reg |= 0x100; break;
1537         }
1538 
1539     }
1540 
1541     /* Write new capability to Phyxcer Reg4 */
1542     if ( !(phy_reg & 0x01e0)) {
1543         phy_reg|=db->PHY_reg4;
1544         db->media_mode|=ULI526X_AUTO;
1545     }
1546     phy->write(db, db->phy_addr, 4, phy_reg);
1547 
1548     /* Restart Auto-Negotiation */
1549     phy->write(db, db->phy_addr, 0, 0x1200);
1550     udelay(50);
1551 }
1552 
1553 
1554 /*
1555  *  Process op-mode
1556     AUTO mode : PHY controller in Auto-negotiation Mode
1557  *  Force mode: PHY controller in force mode with HUB
1558  *          N-way force capability with SWITCH
1559  */
1560 
1561 static void uli526x_process_mode(struct uli526x_board_info *db)
1562 {
1563     struct uli_phy_ops *phy = &db->phy;
1564     u16 phy_reg;
1565 
1566     /* Full Duplex Mode Check */
1567     if (db->op_mode & 0x4)
1568         db->cr6_data |= CR6_FDM;    /* Set Full Duplex Bit */
1569     else
1570         db->cr6_data &= ~CR6_FDM;   /* Clear Full Duplex Bit */
1571 
1572     update_cr6(db->cr6_data, db->ioaddr);
1573 
1574     /* 10/100M phyxcer force mode need */
1575     if (!(db->media_mode & 0x8)) {
1576         /* Forece Mode */
1577         phy_reg = phy->read(db, db->phy_addr, 6);
1578         if (!(phy_reg & 0x1)) {
1579             /* parter without N-Way capability */
1580             phy_reg = 0x0;
1581             switch(db->op_mode) {
1582             case ULI526X_10MHF: phy_reg = 0x0; break;
1583             case ULI526X_10MFD: phy_reg = 0x100; break;
1584             case ULI526X_100MHF: phy_reg = 0x2000; break;
1585             case ULI526X_100MFD: phy_reg = 0x2100; break;
1586             }
1587             phy->write(db, db->phy_addr, 0, phy_reg);
1588         }
1589     }
1590 }
1591 
1592 
1593 /* M5261/M5263 Chip */
1594 static void phy_writeby_cr9(struct uli526x_board_info *db, u8 phy_addr,
1595                 u8 offset, u16 phy_data)
1596 {
1597     u16 i;
1598 
1599     /* Send 33 synchronization clock to Phy controller */
1600     for (i = 0; i < 35; i++)
1601         phy_write_1bit(db, PHY_DATA_1);
1602 
1603     /* Send start command(01) to Phy */
1604     phy_write_1bit(db, PHY_DATA_0);
1605     phy_write_1bit(db, PHY_DATA_1);
1606 
1607     /* Send write command(01) to Phy */
1608     phy_write_1bit(db, PHY_DATA_0);
1609     phy_write_1bit(db, PHY_DATA_1);
1610 
1611     /* Send Phy address */
1612     for (i = 0x10; i > 0; i = i >> 1)
1613         phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1614 
1615     /* Send register address */
1616     for (i = 0x10; i > 0; i = i >> 1)
1617         phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1618 
1619     /* written trasnition */
1620     phy_write_1bit(db, PHY_DATA_1);
1621     phy_write_1bit(db, PHY_DATA_0);
1622 
1623     /* Write a word data to PHY controller */
1624     for (i = 0x8000; i > 0; i >>= 1)
1625         phy_write_1bit(db, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1626 }
1627 
1628 static u16 phy_readby_cr9(struct uli526x_board_info *db, u8 phy_addr, u8 offset)
1629 {
1630     u16 phy_data;
1631     int i;
1632 
1633     /* Send 33 synchronization clock to Phy controller */
1634     for (i = 0; i < 35; i++)
1635         phy_write_1bit(db, PHY_DATA_1);
1636 
1637     /* Send start command(01) to Phy */
1638     phy_write_1bit(db, PHY_DATA_0);
1639     phy_write_1bit(db, PHY_DATA_1);
1640 
1641     /* Send read command(10) to Phy */
1642     phy_write_1bit(db, PHY_DATA_1);
1643     phy_write_1bit(db, PHY_DATA_0);
1644 
1645     /* Send Phy address */
1646     for (i = 0x10; i > 0; i = i >> 1)
1647         phy_write_1bit(db, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1648 
1649     /* Send register address */
1650     for (i = 0x10; i > 0; i = i >> 1)
1651         phy_write_1bit(db, offset & i ? PHY_DATA_1 : PHY_DATA_0);
1652 
1653     /* Skip transition state */
1654     phy_read_1bit(db);
1655 
1656     /* read 16bit data */
1657     for (phy_data = 0, i = 0; i < 16; i++) {
1658         phy_data <<= 1;
1659         phy_data |= phy_read_1bit(db);
1660     }
1661 
1662     return phy_data;
1663 }
1664 
1665 static u16 phy_readby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1666                u8 offset)
1667 {
1668     void __iomem *ioaddr = db->ioaddr;
1669     u32 cr10_value = phy_addr;
1670 
1671     cr10_value = (cr10_value <<  5) + offset;
1672     cr10_value = (cr10_value << 16) + 0x08000000;
1673     uw32(DCR10, cr10_value);
1674     udelay(1);
1675     while (1) {
1676         cr10_value = ur32(DCR10);
1677         if (cr10_value & 0x10000000)
1678             break;
1679     }
1680     return cr10_value & 0x0ffff;
1681 }
1682 
1683 static void phy_writeby_cr10(struct uli526x_board_info *db, u8 phy_addr,
1684                  u8 offset, u16 phy_data)
1685 {
1686     void __iomem *ioaddr = db->ioaddr;
1687     u32 cr10_value = phy_addr;
1688 
1689     cr10_value = (cr10_value <<  5) + offset;
1690     cr10_value = (cr10_value << 16) + 0x04000000 + phy_data;
1691     uw32(DCR10, cr10_value);
1692     udelay(1);
1693 }
1694 /*
1695  *  Write one bit data to Phy Controller
1696  */
1697 
1698 static void phy_write_1bit(struct uli526x_board_info *db, u32 data)
1699 {
1700     void __iomem *ioaddr = db->ioaddr;
1701 
1702     uw32(DCR9, data);       /* MII Clock Low */
1703     udelay(1);
1704     uw32(DCR9, data | MDCLKH);  /* MII Clock High */
1705     udelay(1);
1706     uw32(DCR9, data);       /* MII Clock Low */
1707     udelay(1);
1708 }
1709 
1710 
1711 /*
1712  *  Read one bit phy data from PHY controller
1713  */
1714 
1715 static u16 phy_read_1bit(struct uli526x_board_info *db)
1716 {
1717     void __iomem *ioaddr = db->ioaddr;
1718     u16 phy_data;
1719 
1720     uw32(DCR9, 0x50000);
1721     udelay(1);
1722     phy_data = (ur32(DCR9) >> 19) & 0x1;
1723     uw32(DCR9, 0x40000);
1724     udelay(1);
1725 
1726     return phy_data;
1727 }
1728 
1729 
1730 static const struct pci_device_id uli526x_pci_tbl[] = {
1731     { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1732     { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1733     { 0, }
1734 };
1735 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1736 
1737 static SIMPLE_DEV_PM_OPS(uli526x_pm_ops, uli526x_suspend, uli526x_resume);
1738 
1739 static struct pci_driver uli526x_driver = {
1740     .name       = "uli526x",
1741     .id_table   = uli526x_pci_tbl,
1742     .probe      = uli526x_init_one,
1743     .remove     = uli526x_remove_one,
1744     .driver.pm  = &uli526x_pm_ops,
1745 };
1746 
1747 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1748 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1749 MODULE_LICENSE("GPL");
1750 
1751 module_param(debug, int, 0644);
1752 module_param(mode, int, 0);
1753 module_param(cr6set, int, 0);
1754 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1755 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1756 
1757 /*  Description:
1758  *  when user used insmod to add module, system invoked init_module()
1759  *  to register the services.
1760  */
1761 
1762 static int __init uli526x_init_module(void)
1763 {
1764 
1765     ULI526X_DBUG(0, "init_module() ", debug);
1766 
1767     if (debug)
1768         uli526x_debug = debug;  /* set debug flag */
1769     if (cr6set)
1770         uli526x_cr6_user_set = cr6set;
1771 
1772     switch (mode) {
1773     case ULI526X_10MHF:
1774     case ULI526X_100MHF:
1775     case ULI526X_10MFD:
1776     case ULI526X_100MFD:
1777         uli526x_media_mode = mode;
1778         break;
1779     default:
1780         uli526x_media_mode = ULI526X_AUTO;
1781         break;
1782     }
1783 
1784     return pci_register_driver(&uli526x_driver);
1785 }
1786 
1787 
1788 /*
1789  *  Description:
1790  *  when user used rmmod to delete module, system invoked clean_module()
1791  *  to un-register all registered services.
1792  */
1793 
1794 static void __exit uli526x_cleanup_module(void)
1795 {
1796     ULI526X_DBUG(0, "uli526x_cleanup_module() ", debug);
1797     pci_unregister_driver(&uli526x_driver);
1798 }
1799 
1800 module_init(uli526x_init_module);
1801 module_exit(uli526x_cleanup_module);
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