dec/tulip/tulip.h

0001 /*
0002     drivers/net/ethernet/dec/tulip/tulip.h
0003
0004     Copyright 2000,2001  The Linux Kernel Team
0005     Written/copyright 1994-2001 by Donald Becker.
0006
0007     This software may be used and distributed according to the terms
0008     of the GNU General Public License, incorporated herein by reference.
0009
0010     Please submit bugs to http://bugzilla.kernel.org/ .
0011 */
0012
0013 #ifndef __NET_TULIP_H__
0014 #define __NET_TULIP_H__
0015
0016 #include <linux/kernel.h>
0017 #include <linux/types.h>
0018 #include <linux/spinlock.h>
0019 #include <linux/netdevice.h>
0020 #include <linux/ethtool.h>
0021 #include <linux/timer.h>
0022 #include <linux/delay.h>
0023 #include <linux/pci.h>
0024 #include <asm/io.h>
0025 #include <asm/irq.h>
0026 #include <asm/unaligned.h>
0027
0028
0029
0030 /* undefine, or define to various debugging levels (>4 == obscene levels) */
0031 #define TULIP_DEBUG 1
0032
0033 #ifdef CONFIG_TULIP_MMIO
0034 #define TULIP_BAR   1   /* CBMA */
0035 #else
0036 #define TULIP_BAR   0   /* CBIO */
0037 #endif
0038
0039
0040
0041 struct tulip_chip_table {
0042     char *chip_name;
0043     int io_size;
0044     int valid_intrs;    /* CSR7 interrupt enable settings */
0045     int flags;
0046     void (*media_timer) (struct timer_list *);
0047     work_func_t media_task;
0048 };
0049
0050
0051 enum tbl_flag {
0052     HAS_MII         = 0x00001,
0053     HAS_MEDIA_TABLE     = 0x00002,
0054     CSR12_IN_SROM       = 0x00004,
0055     ALWAYS_CHECK_MII    = 0x00008,
0056     HAS_ACPI        = 0x00010,
0057     MC_HASH_ONLY        = 0x00020, /* Hash-only multicast filter. */
0058     HAS_PNICNWAY        = 0x00080,
0059     HAS_NWAY        = 0x00040, /* Uses internal NWay xcvr. */
0060     HAS_INTR_MITIGATION = 0x00100,
0061     IS_ASIX         = 0x00200,
0062     HAS_8023X       = 0x00400,
0063     COMET_MAC_ADDR      = 0x00800,
0064     HAS_PCI_MWI     = 0x01000,
0065     HAS_PHY_IRQ     = 0x02000,
0066     HAS_SWAPPED_SEEPROM = 0x04000,
0067     NEEDS_FAKE_MEDIA_TABLE  = 0x08000,
0068     COMET_PM        = 0x10000,
0069 };
0070
0071
0072 /* chip types.  careful!  order is VERY IMPORTANT here, as these
0073  * are used throughout the driver as indices into arrays */
0074 /* Note 21142 == 21143. */
0075 enum chips {
0076     DC21040 = 0,
0077     DC21041 = 1,
0078     DC21140 = 2,
0079     DC21142 = 3, DC21143 = 3,
0080     LC82C168,
0081     MX98713,
0082     MX98715,
0083     MX98725,
0084     AX88140,
0085     PNIC2,
0086     COMET,
0087     COMPEX9881,
0088     I21145,
0089     DM910X,
0090     CONEXANT,
0091 };
0092
0093
0094 enum MediaIs {
0095     MediaIsFD = 1,
0096     MediaAlwaysFD = 2,
0097     MediaIsMII = 4,
0098     MediaIsFx = 8,
0099     MediaIs100 = 16
0100 };
0101
0102
0103 /* Offsets to the Command and Status Registers, "CSRs".  All accesses
0104    must be longword instructions and quadword aligned. */
0105 enum tulip_offsets {
0106     CSR0 = 0,
0107     CSR1 = 0x08,
0108     CSR2 = 0x10,
0109     CSR3 = 0x18,
0110     CSR4 = 0x20,
0111     CSR5 = 0x28,
0112     CSR6 = 0x30,
0113     CSR7 = 0x38,
0114     CSR8 = 0x40,
0115     CSR9 = 0x48,
0116     CSR10 = 0x50,
0117     CSR11 = 0x58,
0118     CSR12 = 0x60,
0119     CSR13 = 0x68,
0120     CSR14 = 0x70,
0121     CSR15 = 0x78,
0122     CSR18 = 0x88,
0123     CSR19 = 0x8c,
0124     CSR20 = 0x90,
0125     CSR27 = 0xAC,
0126     CSR28 = 0xB0,
0127 };
0128
0129 /* register offset and bits for CFDD PCI config reg */
0130 enum pci_cfg_driver_reg {
0131     CFDD = 0x40,
0132     CFDD_Sleep = (1 << 31),
0133     CFDD_Snooze = (1 << 30),
0134 };
0135
0136 #define RxPollInt (RxIntr|RxNoBuf|RxDied|RxJabber)
0137
0138 /* The bits in the CSR5 status registers, mostly interrupt sources. */
0139 enum status_bits {
0140     TimerInt = 0x800,
0141     SystemError = 0x2000,
0142     TPLnkFail = 0x1000,
0143     TPLnkPass = 0x10,
0144     NormalIntr = 0x10000,
0145     AbnormalIntr = 0x8000,
0146     RxJabber = 0x200,
0147     RxDied = 0x100,
0148     RxNoBuf = 0x80,
0149     RxIntr = 0x40,
0150     TxFIFOUnderflow = 0x20,
0151     RxErrIntr = 0x10,
0152     TxJabber = 0x08,
0153     TxNoBuf = 0x04,
0154     TxDied = 0x02,
0155     TxIntr = 0x01,
0156 };
0157
0158 /* bit mask for CSR5 TX/RX process state */
0159 #define CSR5_TS 0x00700000
0160 #define CSR5_RS 0x000e0000
0161
0162 enum tulip_mode_bits {
0163     TxThreshold     = (1 << 22),
0164     FullDuplex      = (1 << 9),
0165     TxOn            = 0x2000,
0166     AcceptBroadcast     = 0x0100,
0167     AcceptAllMulticast  = 0x0080,
0168     AcceptAllPhys       = 0x0040,
0169     AcceptRunt      = 0x0008,
0170     RxOn            = 0x0002,
0171     RxTx            = (TxOn | RxOn),
0172 };
0173
0174
0175 enum tulip_busconfig_bits {
0176     MWI         = (1 << 24),
0177     MRL         = (1 << 23),
0178     MRM         = (1 << 21),
0179     CALShift        = 14,
0180     BurstLenShift       = 8,
0181 };
0182
0183
0184 /* The Tulip Rx and Tx buffer descriptors. */
0185 struct tulip_rx_desc {
0186     __le32 status;
0187     __le32 length;
0188     __le32 buffer1;
0189     __le32 buffer2;
0190 };
0191
0192
0193 struct tulip_tx_desc {
0194     __le32 status;
0195     __le32 length;
0196     __le32 buffer1;
0197     __le32 buffer2;     /* We use only buffer 1.  */
0198 };
0199
0200
0201 enum desc_status_bits {
0202     DescOwned    = 0x80000000,
0203     DescWholePkt = 0x60000000,
0204     DescEndPkt   = 0x40000000,
0205     DescStartPkt = 0x20000000,
0206     DescEndRing  = 0x02000000,
0207     DescUseLink  = 0x01000000,
0208
0209     /*
0210      * Error summary flag is logical or of 'CRC Error', 'Collision Seen',
0211      * 'Frame Too Long', 'Runt' and 'Descriptor Error' flags generated
0212      * within tulip chip.
0213      */
0214     RxDescErrorSummary = 0x8000,
0215     RxDescCRCError = 0x0002,
0216     RxDescCollisionSeen = 0x0040,
0217
0218     /*
0219      * 'Frame Too Long' flag is set if packet length including CRC exceeds
0220      * 1518.  However, a full sized VLAN tagged frame is 1522 bytes
0221      * including CRC.
0222      *
0223      * The tulip chip does not block oversized frames, and if this flag is
0224      * set on a receive descriptor it does not indicate the frame has been
0225      * truncated.  The receive descriptor also includes the actual length.
0226      * Therefore we can safety ignore this flag and check the length
0227      * ourselves.
0228      */
0229     RxDescFrameTooLong = 0x0080,
0230     RxDescRunt = 0x0800,
0231     RxDescDescErr = 0x4000,
0232     RxWholePkt   = 0x00000300,
0233     /*
0234      * Top three bits of 14 bit frame length (status bits 27-29) should
0235      * never be set as that would make frame over 2047 bytes. The Receive
0236      * Watchdog flag (bit 4) may indicate the length is over 2048 and the
0237      * length field is invalid.
0238      */
0239     RxLengthOver2047 = 0x38000010
0240 };
0241
0242
0243 enum t21143_csr6_bits {
0244     csr6_sc = (1<<31),
0245     csr6_ra = (1<<30),
0246     csr6_ign_dest_msb = (1<<26),
0247     csr6_mbo = (1<<25),
0248     csr6_scr = (1<<24),  /* scramble mode flag: can't be set */
0249     csr6_pcs = (1<<23),  /* Enables PCS functions (symbol mode requires csr6_ps be set) default is set */
0250     csr6_ttm = (1<<22),  /* Transmit Threshold Mode, set for 10baseT, 0 for 100BaseTX */
0251     csr6_sf = (1<<21),   /* Store and forward. If set ignores TR bits */
0252     csr6_hbd = (1<<19),  /* Heart beat disable. Disables SQE function in 10baseT */
0253     csr6_ps = (1<<18),   /* Port Select. 0 (defualt) = 10baseT, 1 = 100baseTX: can't be set */
0254     csr6_ca = (1<<17),   /* Collision Offset Enable. If set uses special algorithm in low collision situations */
0255     csr6_trh = (1<<15),  /* Transmit Threshold high bit */
0256     csr6_trl = (1<<14),  /* Transmit Threshold low bit */
0257
0258     /***************************************************************
0259      * This table shows transmit threshold values based on media   *
0260      * and these two registers (from PNIC1 & 2 docs) Note: this is *
0261      * all meaningless if sf is set.                               *
0262      ***************************************************************/
0263
0264     /***********************************
0265      * (trh,trl) * 100BaseTX * 10BaseT *
0266      ***********************************
0267      *   (0,0)   *     128   *    72   *
0268      *   (0,1)   *     256   *    96   *
0269      *   (1,0)   *     512   *   128   *
0270      *   (1,1)   *    1024   *   160   *
0271      ***********************************/
0272
0273     csr6_fc = (1<<12),   /* Forces a collision in next transmission (for testing in loopback mode) */
0274     csr6_om_int_loop = (1<<10), /* internal (FIFO) loopback flag */
0275     csr6_om_ext_loop = (1<<11), /* external (PMD) loopback flag */
0276     /* set both and you get (PHY) loopback */
0277     csr6_fd = (1<<9),    /* Full duplex mode, disables hearbeat, no loopback */
0278     csr6_pm = (1<<7),    /* Pass All Multicast */
0279     csr6_pr = (1<<6),    /* Promiscuous mode */
0280     csr6_sb = (1<<5),    /* Start(1)/Stop(0) backoff counter */
0281     csr6_if = (1<<4),    /* Inverse Filtering, rejects only addresses in address table: can't be set */
0282     csr6_pb = (1<<3),    /* Pass Bad Frames, (1) causes even bad frames to be passed on */
0283     csr6_ho = (1<<2),    /* Hash-only filtering mode: can't be set */
0284     csr6_hp = (1<<0),    /* Hash/Perfect Receive Filtering Mode: can't be set */
0285
0286     csr6_mask_capture = (csr6_sc | csr6_ca),
0287     csr6_mask_defstate = (csr6_mask_capture | csr6_mbo),
0288     csr6_mask_hdcap = (csr6_mask_defstate | csr6_hbd | csr6_ps),
0289     csr6_mask_hdcaptt = (csr6_mask_hdcap  | csr6_trh | csr6_trl),
0290     csr6_mask_fullcap = (csr6_mask_hdcaptt | csr6_fd),
0291     csr6_mask_fullpromisc = (csr6_pr | csr6_pm),
0292     csr6_mask_filters = (csr6_hp | csr6_ho | csr6_if),
0293     csr6_mask_100bt = (csr6_scr | csr6_pcs | csr6_hbd),
0294 };
0295
0296 enum tulip_comet_csr13_bits {
0297 /* The LINKOFFE and LINKONE work in conjunction with LSCE, i.e. they
0298  * determine which link status transition wakes up if LSCE is
0299  * enabled */
0300         comet_csr13_linkoffe = (1 << 17),
0301         comet_csr13_linkone = (1 << 16),
0302         comet_csr13_wfre = (1 << 10),
0303         comet_csr13_mpre = (1 << 9),
0304         comet_csr13_lsce = (1 << 8),
0305         comet_csr13_wfr = (1 << 2),
0306         comet_csr13_mpr = (1 << 1),
0307         comet_csr13_lsc = (1 << 0),
0308 };
0309
0310 enum tulip_comet_csr18_bits {
0311         comet_csr18_pmes_sticky = (1 << 24),
0312         comet_csr18_pm_mode = (1 << 19),
0313         comet_csr18_apm_mode = (1 << 18),
0314         comet_csr18_d3a = (1 << 7)
0315 };
0316
0317 enum tulip_comet_csr20_bits {
0318         comet_csr20_pmes = (1 << 15),
0319 };
0320
0321 /* Keep the ring sizes a power of two for efficiency.
0322    Making the Tx ring too large decreases the effectiveness of channel
0323    bonding and packet priority.
0324    There are no ill effects from too-large receive rings. */
0325
0326 #define TX_RING_SIZE    32
0327 #define RX_RING_SIZE    128
0328 #define MEDIA_MASK     31
0329
0330 /* The receiver on the DC21143 rev 65 can fail to close the last
0331  * receive descriptor in certain circumstances (see errata) when
0332  * using MWI. This can only occur if the receive buffer ends on
0333  * a cache line boundary, so the "+ 4" below ensures it doesn't.
0334  */
0335 #define PKT_BUF_SZ  (1536 + 4)  /* Size of each temporary Rx buffer. */
0336
0337 #define TULIP_MIN_CACHE_LINE    8   /* in units of 32-bit words */
0338
0339 #if defined(__sparc__) || defined(__hppa__)
0340 /* The UltraSparc PCI controllers will disconnect at every 64-byte
0341  * crossing anyways so it makes no sense to tell Tulip to burst
0342  * any more than that.
0343  */
0344 #define TULIP_MAX_CACHE_LINE    16  /* in units of 32-bit words */
0345 #else
0346 #define TULIP_MAX_CACHE_LINE    32  /* in units of 32-bit words */
0347 #endif
0348
0349
0350 /* Ring-wrap flag in length field, use for last ring entry.
0351     0x01000000 means chain on buffer2 address,
0352     0x02000000 means use the ring start address in CSR2/3.
0353    Note: Some work-alike chips do not function correctly in chained mode.
0354    The ASIX chip works only in chained mode.
0355    Thus we indicates ring mode, but always write the 'next' field for
0356    chained mode as well.
0357 */
0358 #define DESC_RING_WRAP 0x02000000
0359
0360
0361 #define EEPROM_SIZE 512     /* 2 << EEPROM_ADDRLEN */
0362
0363
0364 #define RUN_AT(x) (jiffies + (x))
0365
0366 #define get_u16(ptr) get_unaligned_le16((ptr))
0367
0368 struct medialeaf {
0369     u8 type;
0370     u8 media;
0371     unsigned char *leafdata;
0372 };
0373
0374
0375 struct mediatable {
0376     u16 defaultmedia;
0377     u8 leafcount;
0378     u8 csr12dir;        /* General purpose pin directions. */
0379     unsigned has_mii:1;
0380     unsigned has_nonmii:1;
0381     unsigned has_reset:6;
0382     u32 csr15dir;
0383     u32 csr15val;       /* 21143 NWay setting. */
0384     struct medialeaf mleaf[];
0385 };
0386
0387
0388 struct mediainfo {
0389     struct mediainfo *next;
0390     int info_type;
0391     int index;
0392     unsigned char *info;
0393 };
0394
0395 struct ring_info {
0396     struct sk_buff  *skb;
0397     dma_addr_t  mapping;
0398 };
0399
0400
0401 struct tulip_private {
0402     const char *product_name;
0403     struct net_device *next_module;
0404     struct tulip_rx_desc *rx_ring;
0405     struct tulip_tx_desc *tx_ring;
0406     dma_addr_t rx_ring_dma;
0407     dma_addr_t tx_ring_dma;
0408     /* The saved address of a sent-in-place packet/buffer, for skfree(). */
0409     struct ring_info tx_buffers[TX_RING_SIZE];
0410     /* The addresses of receive-in-place skbuffs. */
0411     struct ring_info rx_buffers[RX_RING_SIZE];
0412     u16 setup_frame[96];    /* Pseudo-Tx frame to init address table. */
0413     int chip_id;
0414     int revision;
0415     int flags;
0416     struct napi_struct napi;
0417     struct timer_list timer;    /* Media selection timer. */
0418     struct timer_list oom_timer;    /* Out of memory timer. */
0419     u32 mc_filter[2];
0420     spinlock_t lock;
0421     spinlock_t mii_lock;
0422     unsigned int cur_rx, cur_tx;    /* The next free ring entry */
0423     unsigned int dirty_rx, dirty_tx;    /* The ring entries to be free()ed. */
0424
0425 #ifdef  CONFIG_TULIP_NAPI_HW_MITIGATION
0426         int mit_on;
0427 #endif
0428     unsigned int full_duplex:1; /* Full-duplex operation requested. */
0429     unsigned int full_duplex_lock:1;
0430     unsigned int fake_addr:1;   /* Multiport board faked address. */
0431     unsigned int default_port:4;    /* Last dev->if_port value. */
0432     unsigned int media2:4;  /* Secondary monitored media port. */
0433     unsigned int medialock:1;   /* Don't sense media type. */
0434     unsigned int mediasense:1;  /* Media sensing in progress. */
0435     unsigned int nway:1, nwayset:1;     /* 21143 internal NWay. */
0436     unsigned int timeout_recovery:1;
0437     unsigned int csr0;  /* CSR0 setting. */
0438     unsigned int csr6;  /* Current CSR6 control settings. */
0439     unsigned char eeprom[EEPROM_SIZE];  /* Serial EEPROM contents. */
0440     void (*link_change) (struct net_device * dev, int csr5);
0441         struct ethtool_wolinfo wolinfo;        /* WOL settings */
0442     u16 sym_advertise, mii_advertise; /* NWay capabilities advertised.  */
0443     u16 lpar;       /* 21143 Link partner ability. */
0444     u16 advertising[4];
0445     signed char phys[4], mii_cnt;   /* MII device addresses. */
0446     struct mediatable *mtable;
0447     int cur_index;      /* Current media index. */
0448     int saved_if_port;
0449     struct pci_dev *pdev;
0450     int ttimer;
0451     int susp_rx;
0452     unsigned long nir;
0453     void __iomem *base_addr;
0454     int csr12_shadow;
0455     int pad0;       /* Used for 8-byte alignment */
0456     struct work_struct media_work;
0457     struct net_device *dev;
0458 };
0459
0460
0461 struct eeprom_fixup {
0462     char *name;
0463     unsigned char addr0;
0464     unsigned char addr1;
0465     unsigned char addr2;
0466     u16 newtable[32];   /* Max length below. */
0467 };
0468
0469
0470 /* 21142.c */
0471 extern u16 t21142_csr14[];
0472 void t21142_media_task(struct work_struct *work);
0473 void t21142_start_nway(struct net_device *dev);
0474 void t21142_lnk_change(struct net_device *dev, int csr5);
0475
0476
0477 /* PNIC2.c */
0478 void pnic2_lnk_change(struct net_device *dev, int csr5);
0479 void pnic2_timer(struct timer_list *t);
0480 void pnic2_start_nway(struct net_device *dev);
0481
0482 /* eeprom.c */
0483 void tulip_parse_eeprom(struct net_device *dev);
0484 int tulip_read_eeprom(struct net_device *dev, int location, int addr_len);
0485
0486 /* interrupt.c */
0487 extern unsigned int tulip_max_interrupt_work;
0488 extern int tulip_rx_copybreak;
0489 irqreturn_t tulip_interrupt(int irq, void *dev_instance);
0490 int tulip_refill_rx(struct net_device *dev);
0491 #ifdef CONFIG_TULIP_NAPI
0492 int tulip_poll(struct napi_struct *napi, int budget);
0493 #endif
0494
0495
0496 /* media.c */
0497 int tulip_mdio_read(struct net_device *dev, int phy_id, int location);
0498 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int value);
0499 void tulip_select_media(struct net_device *dev, int startup);
0500 int tulip_check_duplex(struct net_device *dev);
0501 void tulip_find_mii (struct net_device *dev, int board_idx);
0502
0503 /* pnic.c */
0504 void pnic_do_nway(struct net_device *dev);
0505 void pnic_lnk_change(struct net_device *dev, int csr5);
0506 void pnic_timer(struct timer_list *t);
0507
0508 /* timer.c */
0509 void tulip_media_task(struct work_struct *work);
0510 void mxic_timer(struct timer_list *t);
0511 void comet_timer(struct timer_list *t);
0512
0513 /* tulip_core.c */
0514 extern int tulip_debug;
0515 extern const char * const medianame[];
0516 extern const char tulip_media_cap[];
0517 extern const struct tulip_chip_table tulip_tbl[];
0518 void oom_timer(struct timer_list *t);
0519 extern u8 t21040_csr13[];
0520
0521 static inline void tulip_start_rxtx(struct tulip_private *tp)
0522 {
0523     void __iomem *ioaddr = tp->base_addr;
0524     iowrite32(tp->csr6 | RxTx, ioaddr + CSR6);
0525     barrier();
0526     (void) ioread32(ioaddr + CSR6); /* mmio sync */
0527 }
0528
0529 static inline void tulip_stop_rxtx(struct tulip_private *tp)
0530 {
0531     void __iomem *ioaddr = tp->base_addr;
0532     u32 csr6 = ioread32(ioaddr + CSR6);
0533
0534     if (csr6 & RxTx) {
0535         unsigned i=1300/10;
0536         iowrite32(csr6 & ~RxTx, ioaddr + CSR6);
0537         barrier();
0538         /* wait until in-flight frame completes.
0539          * Max time @ 10BT: 1500*8b/10Mbps == 1200us (+ 100us margin)
0540          * Typically expect this loop to end in < 50 us on 100BT.
0541          */
0542         while (--i && (ioread32(ioaddr + CSR5) & (CSR5_TS|CSR5_RS)))
0543             udelay(10);
0544
0545         if (!i)
0546             netdev_dbg(tp->dev, "tulip_stop_rxtx() failed (CSR5 0x%x CSR6 0x%x)\n",
0547                    ioread32(ioaddr + CSR5),
0548                    ioread32(ioaddr + CSR6));
0549     }
0550 }
0551
0552 static inline void tulip_restart_rxtx(struct tulip_private *tp)
0553 {
0554     tulip_stop_rxtx(tp);
0555     udelay(5);
0556     tulip_start_rxtx(tp);
0557 }
0558
0559 static inline void tulip_tx_timeout_complete(struct tulip_private *tp, void __iomem *ioaddr)
0560 {
0561     /* Stop and restart the chip's Tx processes. */
0562     tulip_restart_rxtx(tp);
0563     /* Trigger an immediate transmit demand. */
0564     iowrite32(0, ioaddr + CSR1);
0565
0566     tp->dev->stats.tx_errors++;
0567 }
0568
0569 #endif /* __NET_TULIP_H__ */