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0001 /*
0002     drivers/net/ethernet/dec/tulip/media.c
0003 
0004     Copyright 2000,2001  The Linux Kernel Team
0005     Written/copyright 1994-2001 by Donald Becker.
0006 
0007     This software may be used and distributed according to the terms
0008     of the GNU General Public License, incorporated herein by reference.
0009 
0010     Please submit bugs to http://bugzilla.kernel.org/ .
0011 */
0012 
0013 #include <linux/kernel.h>
0014 #include <linux/mii.h>
0015 #include <linux/delay.h>
0016 #include <linux/pci.h>
0017 #include "tulip.h"
0018 
0019 
0020 /* The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
0021    met by back-to-back PCI I/O cycles, but we insert a delay to avoid
0022    "overclocking" issues or future 66Mhz PCI. */
0023 #define mdio_delay() ioread32(mdio_addr)
0024 
0025 /* Read and write the MII registers using software-generated serial
0026    MDIO protocol.  It is just different enough from the EEPROM protocol
0027    to not share code.  The maxium data clock rate is 2.5 Mhz. */
0028 #define MDIO_SHIFT_CLK      0x10000
0029 #define MDIO_DATA_WRITE0    0x00000
0030 #define MDIO_DATA_WRITE1    0x20000
0031 #define MDIO_ENB        0x00000 /* Ignore the 0x02000 databook setting. */
0032 #define MDIO_ENB_IN     0x40000
0033 #define MDIO_DATA_READ      0x80000
0034 
0035 static const unsigned char comet_miireg2offset[32] = {
0036     0xB4, 0xB8, 0xBC, 0xC0,  0xC4, 0xC8, 0xCC, 0,  0,0,0,0,  0,0,0,0,
0037     0,0xD0,0,0,  0,0,0,0,  0,0,0,0, 0, 0xD4, 0xD8, 0xDC, };
0038 
0039 
0040 /* MII transceiver control section.
0041    Read and write the MII registers using software-generated serial
0042    MDIO protocol.
0043    See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management functions")
0044    or DP83840A data sheet for more details.
0045    */
0046 
0047 int tulip_mdio_read(struct net_device *dev, int phy_id, int location)
0048 {
0049     struct tulip_private *tp = netdev_priv(dev);
0050     int i;
0051     int read_cmd = (0xf6 << 10) | ((phy_id & 0x1f) << 5) | location;
0052     int retval = 0;
0053     void __iomem *ioaddr = tp->base_addr;
0054     void __iomem *mdio_addr = ioaddr + CSR9;
0055     unsigned long flags;
0056 
0057     if (location & ~0x1f)
0058         return 0xffff;
0059 
0060     if (tp->chip_id == COMET  &&  phy_id == 30) {
0061         if (comet_miireg2offset[location])
0062             return ioread32(ioaddr + comet_miireg2offset[location]);
0063         return 0xffff;
0064     }
0065 
0066     spin_lock_irqsave(&tp->mii_lock, flags);
0067     if (tp->chip_id == LC82C168) {
0068         iowrite32(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
0069         ioread32(ioaddr + 0xA0);
0070         ioread32(ioaddr + 0xA0);
0071         for (i = 1000; i >= 0; --i) {
0072             barrier();
0073             if ( ! ((retval = ioread32(ioaddr + 0xA0)) & 0x80000000))
0074                 break;
0075         }
0076         spin_unlock_irqrestore(&tp->mii_lock, flags);
0077         return retval & 0xffff;
0078     }
0079 
0080     /* Establish sync by sending at least 32 logic ones. */
0081     for (i = 32; i >= 0; i--) {
0082         iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
0083         mdio_delay();
0084         iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
0085         mdio_delay();
0086     }
0087     /* Shift the read command bits out. */
0088     for (i = 15; i >= 0; i--) {
0089         int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
0090 
0091         iowrite32(MDIO_ENB | dataval, mdio_addr);
0092         mdio_delay();
0093         iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
0094         mdio_delay();
0095     }
0096     /* Read the two transition, 16 data, and wire-idle bits. */
0097     for (i = 19; i > 0; i--) {
0098         iowrite32(MDIO_ENB_IN, mdio_addr);
0099         mdio_delay();
0100         retval = (retval << 1) | ((ioread32(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
0101         iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
0102         mdio_delay();
0103     }
0104 
0105     spin_unlock_irqrestore(&tp->mii_lock, flags);
0106     return (retval>>1) & 0xffff;
0107 }
0108 
0109 void tulip_mdio_write(struct net_device *dev, int phy_id, int location, int val)
0110 {
0111     struct tulip_private *tp = netdev_priv(dev);
0112     int i;
0113     int cmd = (0x5002 << 16) | ((phy_id & 0x1f) << 23) | (location<<18) | (val & 0xffff);
0114     void __iomem *ioaddr = tp->base_addr;
0115     void __iomem *mdio_addr = ioaddr + CSR9;
0116     unsigned long flags;
0117 
0118     if (location & ~0x1f)
0119         return;
0120 
0121     if (tp->chip_id == COMET && phy_id == 30) {
0122         if (comet_miireg2offset[location])
0123             iowrite32(val, ioaddr + comet_miireg2offset[location]);
0124         return;
0125     }
0126 
0127     spin_lock_irqsave(&tp->mii_lock, flags);
0128     if (tp->chip_id == LC82C168) {
0129         iowrite32(cmd, ioaddr + 0xA0);
0130         for (i = 1000; i >= 0; --i) {
0131             barrier();
0132             if ( ! (ioread32(ioaddr + 0xA0) & 0x80000000))
0133                 break;
0134         }
0135         spin_unlock_irqrestore(&tp->mii_lock, flags);
0136         return;
0137     }
0138 
0139     /* Establish sync by sending 32 logic ones. */
0140     for (i = 32; i >= 0; i--) {
0141         iowrite32(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
0142         mdio_delay();
0143         iowrite32(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
0144         mdio_delay();
0145     }
0146     /* Shift the command bits out. */
0147     for (i = 31; i >= 0; i--) {
0148         int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
0149         iowrite32(MDIO_ENB | dataval, mdio_addr);
0150         mdio_delay();
0151         iowrite32(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
0152         mdio_delay();
0153     }
0154     /* Clear out extra bits. */
0155     for (i = 2; i > 0; i--) {
0156         iowrite32(MDIO_ENB_IN, mdio_addr);
0157         mdio_delay();
0158         iowrite32(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
0159         mdio_delay();
0160     }
0161 
0162     spin_unlock_irqrestore(&tp->mii_lock, flags);
0163 }
0164 
0165 
0166 /* Set up the transceiver control registers for the selected media type. */
0167 void tulip_select_media(struct net_device *dev, int startup)
0168 {
0169     struct tulip_private *tp = netdev_priv(dev);
0170     void __iomem *ioaddr = tp->base_addr;
0171     struct mediatable *mtable = tp->mtable;
0172     u32 new_csr6;
0173     int i;
0174 
0175     if (mtable) {
0176         struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
0177         unsigned char *p = mleaf->leafdata;
0178         switch (mleaf->type) {
0179         case 0:                 /* 21140 non-MII xcvr. */
0180             if (tulip_debug > 1)
0181                 netdev_dbg(dev, "Using a 21140 non-MII transceiver with control setting %02x\n",
0182                        p[1]);
0183             dev->if_port = p[0];
0184             if (startup)
0185                 iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
0186             iowrite32(p[1], ioaddr + CSR12);
0187             new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);
0188             break;
0189         case 2: case 4: {
0190             u16 setup[5];
0191             u32 csr13val, csr14val, csr15dir, csr15val;
0192             for (i = 0; i < 5; i++)
0193                 setup[i] = get_u16(&p[i*2 + 1]);
0194 
0195             dev->if_port = p[0] & MEDIA_MASK;
0196             if (tulip_media_cap[dev->if_port] & MediaAlwaysFD)
0197                 tp->full_duplex = 1;
0198 
0199             if (startup && mtable->has_reset) {
0200                 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
0201                 unsigned char *rst = rleaf->leafdata;
0202                 if (tulip_debug > 1)
0203                     netdev_dbg(dev, "Resetting the transceiver\n");
0204                 for (i = 0; i < rst[0]; i++)
0205                     iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
0206             }
0207             if (tulip_debug > 1)
0208                 netdev_dbg(dev, "21143 non-MII %s transceiver control %04x/%04x\n",
0209                        medianame[dev->if_port],
0210                        setup[0], setup[1]);
0211             if (p[0] & 0x40) {  /* SIA (CSR13-15) setup values are provided. */
0212                 csr13val = setup[0];
0213                 csr14val = setup[1];
0214                 csr15dir = (setup[3]<<16) | setup[2];
0215                 csr15val = (setup[4]<<16) | setup[2];
0216                 iowrite32(0, ioaddr + CSR13);
0217                 iowrite32(csr14val, ioaddr + CSR14);
0218                 iowrite32(csr15dir, ioaddr + CSR15);    /* Direction */
0219                 iowrite32(csr15val, ioaddr + CSR15);    /* Data */
0220                 iowrite32(csr13val, ioaddr + CSR13);
0221             } else {
0222                 csr13val = 1;
0223                 csr14val = 0;
0224                 csr15dir = (setup[0]<<16) | 0x0008;
0225                 csr15val = (setup[1]<<16) | 0x0008;
0226                 if (dev->if_port <= 4)
0227                     csr14val = t21142_csr14[dev->if_port];
0228                 if (startup) {
0229                     iowrite32(0, ioaddr + CSR13);
0230                     iowrite32(csr14val, ioaddr + CSR14);
0231                 }
0232                 iowrite32(csr15dir, ioaddr + CSR15);    /* Direction */
0233                 iowrite32(csr15val, ioaddr + CSR15);    /* Data */
0234                 if (startup) iowrite32(csr13val, ioaddr + CSR13);
0235             }
0236             if (tulip_debug > 1)
0237                 netdev_dbg(dev, "Setting CSR15 to %08x/%08x\n",
0238                        csr15dir, csr15val);
0239             if (mleaf->type == 4)
0240                 new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);
0241             else
0242                 new_csr6 = 0x82420000;
0243             break;
0244         }
0245         case 1: case 3: {
0246             int phy_num = p[0];
0247             int init_length = p[1];
0248             u16 *misc_info, tmp_info;
0249 
0250             dev->if_port = 11;
0251             new_csr6 = 0x020E0000;
0252             if (mleaf->type == 3) { /* 21142 */
0253                 u16 *init_sequence = (u16*)(p+2);
0254                 u16 *reset_sequence = &((u16*)(p+3))[init_length];
0255                 int reset_length = p[2 + init_length*2];
0256                 misc_info = reset_sequence + reset_length;
0257                 if (startup) {
0258                     int timeout = 10;   /* max 1 ms */
0259                     for (i = 0; i < reset_length; i++)
0260                         iowrite32(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);
0261 
0262                     /* flush posted writes */
0263                     ioread32(ioaddr + CSR15);
0264 
0265                     /* Sect 3.10.3 in DP83840A.pdf (p39) */
0266                     udelay(500);
0267 
0268                     /* Section 4.2 in DP83840A.pdf (p43) */
0269                     /* and IEEE 802.3 "22.2.4.1.1 Reset" */
0270                     while (timeout-- &&
0271                         (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
0272                         udelay(100);
0273                 }
0274                 for (i = 0; i < init_length; i++)
0275                     iowrite32(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);
0276 
0277                 ioread32(ioaddr + CSR15);   /* flush posted writes */
0278             } else {
0279                 u8 *init_sequence = p + 2;
0280                 u8 *reset_sequence = p + 3 + init_length;
0281                 int reset_length = p[2 + init_length];
0282                 misc_info = (u16*)(reset_sequence + reset_length);
0283                 if (startup) {
0284                     int timeout = 10;   /* max 1 ms */
0285                     iowrite32(mtable->csr12dir | 0x100, ioaddr + CSR12);
0286                     for (i = 0; i < reset_length; i++)
0287                         iowrite32(reset_sequence[i], ioaddr + CSR12);
0288 
0289                     /* flush posted writes */
0290                     ioread32(ioaddr + CSR12);
0291 
0292                     /* Sect 3.10.3 in DP83840A.pdf (p39) */
0293                     udelay(500);
0294 
0295                     /* Section 4.2 in DP83840A.pdf (p43) */
0296                     /* and IEEE 802.3 "22.2.4.1.1 Reset" */
0297                     while (timeout-- &&
0298                         (tulip_mdio_read (dev, phy_num, MII_BMCR) & BMCR_RESET))
0299                         udelay(100);
0300                 }
0301                 for (i = 0; i < init_length; i++)
0302                     iowrite32(init_sequence[i], ioaddr + CSR12);
0303 
0304                 ioread32(ioaddr + CSR12);   /* flush posted writes */
0305             }
0306 
0307             tmp_info = get_u16(&misc_info[1]);
0308             if (tmp_info)
0309                 tp->advertising[phy_num] = tmp_info | 1;
0310             if (tmp_info && startup < 2) {
0311                 if (tp->mii_advertise == 0)
0312                     tp->mii_advertise = tp->advertising[phy_num];
0313                 if (tulip_debug > 1)
0314                     netdev_dbg(dev, " Advertising %04x on MII %d\n",
0315                            tp->mii_advertise,
0316                            tp->phys[phy_num]);
0317                 tulip_mdio_write(dev, tp->phys[phy_num], 4, tp->mii_advertise);
0318             }
0319             break;
0320         }
0321         case 5: case 6: {
0322             new_csr6 = 0; /* FIXME */
0323 
0324             if (startup && mtable->has_reset) {
0325                 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
0326                 unsigned char *rst = rleaf->leafdata;
0327                 if (tulip_debug > 1)
0328                     netdev_dbg(dev, "Resetting the transceiver\n");
0329                 for (i = 0; i < rst[0]; i++)
0330                     iowrite32(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
0331             }
0332 
0333             break;
0334         }
0335         default:
0336             netdev_dbg(dev, " Invalid media table selection %d\n",
0337                    mleaf->type);
0338             new_csr6 = 0x020E0000;
0339         }
0340         if (tulip_debug > 1)
0341             netdev_dbg(dev, "Using media type %s, CSR12 is %02x\n",
0342                    medianame[dev->if_port],
0343                    ioread32(ioaddr + CSR12) & 0xff);
0344     } else if (tp->chip_id == LC82C168) {
0345         if (startup && ! tp->medialock)
0346             dev->if_port = tp->mii_cnt ? 11 : 0;
0347         if (tulip_debug > 1)
0348             netdev_dbg(dev, "PNIC PHY status is %3.3x, media %s\n",
0349                    ioread32(ioaddr + 0xB8),
0350                    medianame[dev->if_port]);
0351         if (tp->mii_cnt) {
0352             new_csr6 = 0x810C0000;
0353             iowrite32(0x0001, ioaddr + CSR15);
0354             iowrite32(0x0201B07A, ioaddr + 0xB8);
0355         } else if (startup) {
0356             /* Start with 10mbps to do autonegotiation. */
0357             iowrite32(0x32, ioaddr + CSR12);
0358             new_csr6 = 0x00420000;
0359             iowrite32(0x0001B078, ioaddr + 0xB8);
0360             iowrite32(0x0201B078, ioaddr + 0xB8);
0361         } else if (dev->if_port == 3  ||  dev->if_port == 5) {
0362             iowrite32(0x33, ioaddr + CSR12);
0363             new_csr6 = 0x01860000;
0364             /* Trigger autonegotiation. */
0365             iowrite32(0x0001F868, ioaddr + 0xB8);
0366         } else {
0367             iowrite32(0x32, ioaddr + CSR12);
0368             new_csr6 = 0x00420000;
0369             iowrite32(0x1F078, ioaddr + 0xB8);
0370         }
0371     } else {                    /* Unknown chip type with no media table. */
0372         if (tp->default_port == 0)
0373             dev->if_port = tp->mii_cnt ? 11 : 3;
0374         if (tulip_media_cap[dev->if_port] & MediaIsMII) {
0375             new_csr6 = 0x020E0000;
0376         } else if (tulip_media_cap[dev->if_port] & MediaIsFx) {
0377             new_csr6 = 0x02860000;
0378         } else
0379             new_csr6 = 0x03860000;
0380         if (tulip_debug > 1)
0381             netdev_dbg(dev, "No media description table, assuming %s transceiver, CSR12 %02x\n",
0382                    medianame[dev->if_port],
0383                    ioread32(ioaddr + CSR12));
0384     }
0385 
0386     tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
0387 
0388     mdelay(1);
0389 }
0390 
0391 /*
0392   Check the MII negotiated duplex and change the CSR6 setting if
0393   required.
0394   Return 0 if everything is OK.
0395   Return < 0 if the transceiver is missing or has no link beat.
0396   */
0397 int tulip_check_duplex(struct net_device *dev)
0398 {
0399     struct tulip_private *tp = netdev_priv(dev);
0400     unsigned int bmsr, lpa, negotiated, new_csr6;
0401 
0402     bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
0403     lpa = tulip_mdio_read(dev, tp->phys[0], MII_LPA);
0404     if (tulip_debug > 1)
0405         dev_info(&dev->dev, "MII status %04x, Link partner report %04x\n",
0406              bmsr, lpa);
0407     if (bmsr == 0xffff)
0408         return -2;
0409     if ((bmsr & BMSR_LSTATUS) == 0) {
0410         int new_bmsr = tulip_mdio_read(dev, tp->phys[0], MII_BMSR);
0411         if ((new_bmsr & BMSR_LSTATUS) == 0) {
0412             if (tulip_debug  > 1)
0413                 dev_info(&dev->dev,
0414                      "No link beat on the MII interface, status %04x\n",
0415                      new_bmsr);
0416             return -1;
0417         }
0418     }
0419     negotiated = lpa & tp->advertising[0];
0420     tp->full_duplex = mii_duplex(tp->full_duplex_lock, negotiated);
0421 
0422     new_csr6 = tp->csr6;
0423 
0424     if (negotiated & LPA_100) new_csr6 &= ~TxThreshold;
0425     else              new_csr6 |= TxThreshold;
0426     if (tp->full_duplex) new_csr6 |= FullDuplex;
0427     else             new_csr6 &= ~FullDuplex;
0428 
0429     if (new_csr6 != tp->csr6) {
0430         tp->csr6 = new_csr6;
0431         tulip_restart_rxtx(tp);
0432 
0433         if (tulip_debug > 0)
0434             dev_info(&dev->dev,
0435                  "Setting %s-duplex based on MII#%d link partner capability of %04x\n",
0436                  tp->full_duplex ? "full" : "half",
0437                  tp->phys[0], lpa);
0438         return 1;
0439     }
0440 
0441     return 0;
0442 }
0443 
0444 void tulip_find_mii(struct net_device *dev, int board_idx)
0445 {
0446     struct tulip_private *tp = netdev_priv(dev);
0447     int phyn, phy_idx = 0;
0448     int mii_reg0;
0449     int mii_advert;
0450     unsigned int to_advert, new_bmcr, ane_switch;
0451 
0452     /* Find the connected MII xcvrs.
0453        Doing this in open() would allow detecting external xcvrs later,
0454        but takes much time. */
0455     for (phyn = 1; phyn <= 32 && phy_idx < ARRAY_SIZE(tp->phys); phyn++) {
0456         int phy = phyn & 0x1f;
0457         int mii_status = tulip_mdio_read (dev, phy, MII_BMSR);
0458         if ((mii_status & 0x8301) == 0x8001 ||
0459             ((mii_status & BMSR_100BASE4) == 0 &&
0460              (mii_status & 0x7800) != 0)) {
0461             /* preserve Becker logic, gain indentation level */
0462         } else {
0463             continue;
0464         }
0465 
0466         mii_reg0 = tulip_mdio_read (dev, phy, MII_BMCR);
0467         mii_advert = tulip_mdio_read (dev, phy, MII_ADVERTISE);
0468         ane_switch = 0;
0469 
0470         /* if not advertising at all, gen an
0471          * advertising value from the capability
0472          * bits in BMSR
0473          */
0474         if ((mii_advert & ADVERTISE_ALL) == 0) {
0475             unsigned int tmpadv = tulip_mdio_read (dev, phy, MII_BMSR);
0476             mii_advert = ((tmpadv >> 6) & 0x3e0) | 1;
0477         }
0478 
0479         if (tp->mii_advertise) {
0480             tp->advertising[phy_idx] =
0481             to_advert = tp->mii_advertise;
0482         } else if (tp->advertising[phy_idx]) {
0483             to_advert = tp->advertising[phy_idx];
0484         } else {
0485             tp->advertising[phy_idx] =
0486             tp->mii_advertise =
0487             to_advert = mii_advert;
0488         }
0489 
0490         tp->phys[phy_idx++] = phy;
0491 
0492         pr_info("tulip%d:  MII transceiver #%d config %04x status %04x advertising %04x\n",
0493             board_idx, phy, mii_reg0, mii_status, mii_advert);
0494 
0495         /* Fixup for DLink with miswired PHY. */
0496         if (mii_advert != to_advert) {
0497             pr_debug("tulip%d:  Advertising %04x on PHY %d, previously advertising %04x\n",
0498                  board_idx, to_advert, phy, mii_advert);
0499             tulip_mdio_write (dev, phy, 4, to_advert);
0500         }
0501 
0502         /* Enable autonegotiation: some boards default to off. */
0503         if (tp->default_port == 0) {
0504             new_bmcr = mii_reg0 | BMCR_ANENABLE;
0505             if (new_bmcr != mii_reg0) {
0506                 new_bmcr |= BMCR_ANRESTART;
0507                 ane_switch = 1;
0508             }
0509         }
0510         /* ...or disable nway, if forcing media */
0511         else {
0512             new_bmcr = mii_reg0 & ~BMCR_ANENABLE;
0513             if (new_bmcr != mii_reg0)
0514                 ane_switch = 1;
0515         }
0516 
0517         /* clear out bits we never want at this point */
0518         new_bmcr &= ~(BMCR_CTST | BMCR_FULLDPLX | BMCR_ISOLATE |
0519                   BMCR_PDOWN | BMCR_SPEED100 | BMCR_LOOPBACK |
0520                   BMCR_RESET);
0521 
0522         if (tp->full_duplex)
0523             new_bmcr |= BMCR_FULLDPLX;
0524         if (tulip_media_cap[tp->default_port] & MediaIs100)
0525             new_bmcr |= BMCR_SPEED100;
0526 
0527         if (new_bmcr != mii_reg0) {
0528             /* some phys need the ANE switch to
0529              * happen before forced media settings
0530              * will "take."  However, we write the
0531              * same value twice in order not to
0532              * confuse the sane phys.
0533              */
0534             if (ane_switch) {
0535                 tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
0536                 udelay (10);
0537             }
0538             tulip_mdio_write (dev, phy, MII_BMCR, new_bmcr);
0539         }
0540     }
0541     tp->mii_cnt = phy_idx;
0542     if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) {
0543         pr_info("tulip%d: ***WARNING***: No MII transceiver found!\n",
0544             board_idx);
0545         tp->phys[0] = 1;
0546     }
0547 }
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