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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2022 Davicom Semiconductor,Inc.
0004  * Davicom DM9051 SPI Fast Ethernet Linux driver
0005  */
0006 
0007 #include <linux/etherdevice.h>
0008 #include <linux/ethtool.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/irq.h>
0012 #include <linux/mii.h>
0013 #include <linux/module.h>
0014 #include <linux/netdevice.h>
0015 #include <linux/phy.h>
0016 #include <linux/regmap.h>
0017 #include <linux/skbuff.h>
0018 #include <linux/spinlock.h>
0019 #include <linux/spi/spi.h>
0020 #include <linux/types.h>
0021 
0022 #include "dm9051.h"
0023 
0024 #define DRVNAME_9051    "dm9051"
0025 
0026 /**
0027  * struct rx_ctl_mach - rx activities record
0028  * @status_err_counter: rx status error counter
0029  * @large_err_counter: rx get large packet length error counter
0030  * @rx_err_counter: receive packet error counter
0031  * @tx_err_counter: transmit packet error counter
0032  * @fifo_rst_counter: reset operation counter
0033  *
0034  * To keep track for the driver operation statistics
0035  */
0036 struct rx_ctl_mach {
0037     u16             status_err_counter;
0038     u16             large_err_counter;
0039     u16             rx_err_counter;
0040     u16             tx_err_counter;
0041     u16             fifo_rst_counter;
0042 };
0043 
0044 /**
0045  * struct dm9051_rxctrl - dm9051 driver rx control
0046  * @hash_table: Multicast hash-table data
0047  * @rcr_all: KS_RXCR1 register setting
0048  *
0049  * The settings needs to control the receive filtering
0050  * such as the multicast hash-filter and the receive register settings
0051  */
0052 struct dm9051_rxctrl {
0053     u16             hash_table[4];
0054     u8              rcr_all;
0055 };
0056 
0057 /**
0058  * struct dm9051_rxhdr - rx packet data header
0059  * @headbyte: lead byte equal to 0x01 notifies a valid packet
0060  * @status: status bits for the received packet
0061  * @rxlen: packet length
0062  *
0063  * The Rx packed, entered into the FIFO memory, start with these
0064  * four bytes which is the Rx header, followed by the ethernet
0065  * packet data and ends with an appended 4-byte CRC data.
0066  * Both Rx packet and CRC data are for check purpose and finally
0067  * are dropped by this driver
0068  */
0069 struct dm9051_rxhdr {
0070     u8              headbyte;
0071     u8              status;
0072     __le16              rxlen;
0073 };
0074 
0075 /**
0076  * struct board_info - maintain the saved data
0077  * @spidev: spi device structure
0078  * @ndev: net device structure
0079  * @mdiobus: mii bus structure
0080  * @phydev: phy device structure
0081  * @txq: tx queue structure
0082  * @regmap_dm: regmap for register read/write
0083  * @regmap_dmbulk: extra regmap for bulk read/write
0084  * @rxctrl_work: Work queue for updating RX mode and multicast lists
0085  * @tx_work: Work queue for tx packets
0086  * @pause: ethtool pause parameter structure
0087  * @spi_lockm: between threads lock structure
0088  * @reg_mutex: regmap access lock structure
0089  * @bc: rx control statistics structure
0090  * @rxhdr: rx header structure
0091  * @rctl: rx control setting structure
0092  * @msg_enable: message level value
0093  * @imr_all: to store operating imr value for register DM9051_IMR
0094  * @lcr_all: to store operating rcr value for register DM9051_LMCR
0095  *
0096  * The saved data variables, keep up to date for retrieval back to use
0097  */
0098 struct board_info {
0099     u32             msg_enable;
0100     struct spi_device       *spidev;
0101     struct net_device       *ndev;
0102     struct mii_bus          *mdiobus;
0103     struct phy_device       *phydev;
0104     struct sk_buff_head     txq;
0105     struct regmap           *regmap_dm;
0106     struct regmap           *regmap_dmbulk;
0107     struct work_struct      rxctrl_work;
0108     struct work_struct      tx_work;
0109     struct ethtool_pauseparam   pause;
0110     struct mutex            spi_lockm;
0111     struct mutex            reg_mutex;
0112     struct rx_ctl_mach      bc;
0113     struct dm9051_rxhdr     rxhdr;
0114     struct dm9051_rxctrl        rctl;
0115     u8              imr_all;
0116     u8              lcr_all;
0117 };
0118 
0119 static int dm9051_set_reg(struct board_info *db, unsigned int reg, unsigned int val)
0120 {
0121     int ret;
0122 
0123     ret = regmap_write(db->regmap_dm, reg, val);
0124     if (ret < 0)
0125         netif_err(db, drv, db->ndev, "%s: error %d set reg %02x\n",
0126               __func__, ret, reg);
0127     return ret;
0128 }
0129 
0130 static int dm9051_update_bits(struct board_info *db, unsigned int reg, unsigned int mask,
0131                   unsigned int val)
0132 {
0133     int ret;
0134 
0135     ret = regmap_update_bits(db->regmap_dm, reg, mask, val);
0136     if (ret < 0)
0137         netif_err(db, drv, db->ndev, "%s: error %d update bits reg %02x\n",
0138               __func__, ret, reg);
0139     return ret;
0140 }
0141 
0142 /* skb buffer exhausted, just discard the received data
0143  */
0144 static int dm9051_dumpblk(struct board_info *db, u8 reg, size_t count)
0145 {
0146     struct net_device *ndev = db->ndev;
0147     unsigned int rb;
0148     int ret;
0149 
0150     /* no skb buffer,
0151      * both reg and &rb must be noinc,
0152      * read once one byte via regmap_read
0153      */
0154     do {
0155         ret = regmap_read(db->regmap_dm, reg, &rb);
0156         if (ret < 0) {
0157             netif_err(db, drv, ndev, "%s: error %d dumping read reg %02x\n",
0158                   __func__, ret, reg);
0159             break;
0160         }
0161     } while (--count);
0162 
0163     return ret;
0164 }
0165 
0166 static int dm9051_set_regs(struct board_info *db, unsigned int reg, const void *val,
0167                size_t val_count)
0168 {
0169     int ret;
0170 
0171     ret = regmap_bulk_write(db->regmap_dmbulk, reg, val, val_count);
0172     if (ret < 0)
0173         netif_err(db, drv, db->ndev, "%s: error %d bulk writing regs %02x\n",
0174               __func__, ret, reg);
0175     return ret;
0176 }
0177 
0178 static int dm9051_get_regs(struct board_info *db, unsigned int reg, void *val,
0179                size_t val_count)
0180 {
0181     int ret;
0182 
0183     ret = regmap_bulk_read(db->regmap_dmbulk, reg, val, val_count);
0184     if (ret < 0)
0185         netif_err(db, drv, db->ndev, "%s: error %d bulk reading regs %02x\n",
0186               __func__, ret, reg);
0187     return ret;
0188 }
0189 
0190 static int dm9051_write_mem(struct board_info *db, unsigned int reg, const void *buff,
0191                 size_t len)
0192 {
0193     int ret;
0194 
0195     ret = regmap_noinc_write(db->regmap_dm, reg, buff, len);
0196     if (ret < 0)
0197         netif_err(db, drv, db->ndev, "%s: error %d noinc writing regs %02x\n",
0198               __func__, ret, reg);
0199     return ret;
0200 }
0201 
0202 static int dm9051_read_mem(struct board_info *db, unsigned int reg, void *buff,
0203                size_t len)
0204 {
0205     int ret;
0206 
0207     ret = regmap_noinc_read(db->regmap_dm, reg, buff, len);
0208     if (ret < 0)
0209         netif_err(db, drv, db->ndev, "%s: error %d noinc reading regs %02x\n",
0210               __func__, ret, reg);
0211     return ret;
0212 }
0213 
0214 /* waiting tx-end rather than tx-req
0215  * got faster
0216  */
0217 static int dm9051_nsr_poll(struct board_info *db)
0218 {
0219     unsigned int mval;
0220     int ret;
0221 
0222     ret = regmap_read_poll_timeout(db->regmap_dm, DM9051_NSR, mval,
0223                        mval & (NSR_TX2END | NSR_TX1END), 1, 20);
0224     if (ret == -ETIMEDOUT)
0225         netdev_err(db->ndev, "timeout in checking for tx end\n");
0226     return ret;
0227 }
0228 
0229 static int dm9051_epcr_poll(struct board_info *db)
0230 {
0231     unsigned int mval;
0232     int ret;
0233 
0234     ret = regmap_read_poll_timeout(db->regmap_dm, DM9051_EPCR, mval,
0235                        !(mval & EPCR_ERRE), 100, 10000);
0236     if (ret == -ETIMEDOUT)
0237         netdev_err(db->ndev, "eeprom/phy in processing get timeout\n");
0238     return ret;
0239 }
0240 
0241 static int dm9051_irq_flag(struct board_info *db)
0242 {
0243     struct spi_device *spi = db->spidev;
0244     int irq_type = irq_get_trigger_type(spi->irq);
0245 
0246     if (irq_type)
0247         return irq_type;
0248 
0249     return IRQF_TRIGGER_LOW;
0250 }
0251 
0252 static unsigned int dm9051_intcr_value(struct board_info *db)
0253 {
0254     return (dm9051_irq_flag(db) == IRQF_TRIGGER_LOW) ?
0255         INTCR_POL_LOW : INTCR_POL_HIGH;
0256 }
0257 
0258 static int dm9051_set_fcr(struct board_info *db)
0259 {
0260     u8 fcr = 0;
0261 
0262     if (db->pause.rx_pause)
0263         fcr |= FCR_BKPM | FCR_FLCE;
0264     if (db->pause.tx_pause)
0265         fcr |= FCR_TXPEN;
0266 
0267     return dm9051_set_reg(db, DM9051_FCR, fcr);
0268 }
0269 
0270 static int dm9051_set_recv(struct board_info *db)
0271 {
0272     int ret;
0273 
0274     ret = dm9051_set_regs(db, DM9051_MAR, db->rctl.hash_table, sizeof(db->rctl.hash_table));
0275     if (ret)
0276         return ret;
0277 
0278     return dm9051_set_reg(db, DM9051_RCR, db->rctl.rcr_all); /* enable rx */
0279 }
0280 
0281 static int dm9051_core_reset(struct board_info *db)
0282 {
0283     int ret;
0284 
0285     db->bc.fifo_rst_counter++;
0286 
0287     ret = regmap_write(db->regmap_dm, DM9051_NCR, NCR_RST); /* NCR reset */
0288     if (ret)
0289         return ret;
0290     ret = regmap_write(db->regmap_dm, DM9051_MBNDRY, MBNDRY_BYTE); /* MemBound */
0291     if (ret)
0292         return ret;
0293     ret = regmap_write(db->regmap_dm, DM9051_PPCR, PPCR_PAUSE_COUNT); /* Pause Count */
0294     if (ret)
0295         return ret;
0296     ret = regmap_write(db->regmap_dm, DM9051_LMCR, db->lcr_all); /* LEDMode1 */
0297     if (ret)
0298         return ret;
0299 
0300     return dm9051_set_reg(db, DM9051_INTCR, dm9051_intcr_value(db));
0301 }
0302 
0303 static int dm9051_update_fcr(struct board_info *db)
0304 {
0305     u8 fcr = 0;
0306 
0307     if (db->pause.rx_pause)
0308         fcr |= FCR_BKPM | FCR_FLCE;
0309     if (db->pause.tx_pause)
0310         fcr |= FCR_TXPEN;
0311 
0312     return dm9051_update_bits(db, DM9051_FCR, FCR_RXTX_BITS, fcr);
0313 }
0314 
0315 static int dm9051_disable_interrupt(struct board_info *db)
0316 {
0317     return dm9051_set_reg(db, DM9051_IMR, IMR_PAR); /* disable int */
0318 }
0319 
0320 static int dm9051_enable_interrupt(struct board_info *db)
0321 {
0322     return dm9051_set_reg(db, DM9051_IMR, db->imr_all); /* enable int */
0323 }
0324 
0325 static int dm9051_stop_mrcmd(struct board_info *db)
0326 {
0327     return dm9051_set_reg(db, DM9051_ISR, ISR_STOP_MRCMD); /* to stop mrcmd */
0328 }
0329 
0330 static int dm9051_clear_interrupt(struct board_info *db)
0331 {
0332     return dm9051_update_bits(db, DM9051_ISR, ISR_CLR_INT, ISR_CLR_INT);
0333 }
0334 
0335 static int dm9051_eeprom_read(struct board_info *db, int offset, u8 *to)
0336 {
0337     int ret;
0338 
0339     ret = regmap_write(db->regmap_dm, DM9051_EPAR, offset);
0340     if (ret)
0341         return ret;
0342 
0343     ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_ERPRR);
0344     if (ret)
0345         return ret;
0346 
0347     ret = dm9051_epcr_poll(db);
0348     if (ret)
0349         return ret;
0350 
0351     ret = regmap_write(db->regmap_dm, DM9051_EPCR, 0);
0352     if (ret)
0353         return ret;
0354 
0355     return regmap_bulk_read(db->regmap_dmbulk, DM9051_EPDRL, to, 2);
0356 }
0357 
0358 static int dm9051_eeprom_write(struct board_info *db, int offset, u8 *data)
0359 {
0360     int ret;
0361 
0362     ret = regmap_write(db->regmap_dm, DM9051_EPAR, offset);
0363     if (ret)
0364         return ret;
0365 
0366     ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_EPDRL, data, 2);
0367     if (ret < 0)
0368         return ret;
0369 
0370     ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_WEP | EPCR_ERPRW);
0371     if (ret)
0372         return ret;
0373 
0374     ret = dm9051_epcr_poll(db);
0375     if (ret)
0376         return ret;
0377 
0378     return regmap_write(db->regmap_dm, DM9051_EPCR, 0);
0379 }
0380 
0381 static int dm9051_phyread(void *context, unsigned int reg, unsigned int *val)
0382 {
0383     struct board_info *db = context;
0384     int ret;
0385 
0386     ret = regmap_write(db->regmap_dm, DM9051_EPAR, DM9051_PHY | reg);
0387     if (ret)
0388         return ret;
0389 
0390     ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_ERPRR | EPCR_EPOS);
0391     if (ret)
0392         return ret;
0393 
0394     ret = dm9051_epcr_poll(db);
0395     if (ret)
0396         return ret;
0397 
0398     ret = regmap_write(db->regmap_dm, DM9051_EPCR, 0);
0399     if (ret)
0400         return ret;
0401 
0402     /* this is a 4 bytes data, clear to zero since following regmap_bulk_read
0403      * only fill lower 2 bytes
0404      */
0405     *val = 0;
0406     return regmap_bulk_read(db->regmap_dmbulk, DM9051_EPDRL, val, 2);
0407 }
0408 
0409 static int dm9051_phywrite(void *context, unsigned int reg, unsigned int val)
0410 {
0411     struct board_info *db = context;
0412     int ret;
0413 
0414     ret = regmap_write(db->regmap_dm, DM9051_EPAR, DM9051_PHY | reg);
0415     if (ret)
0416         return ret;
0417 
0418     ret = regmap_bulk_write(db->regmap_dmbulk, DM9051_EPDRL, &val, 2);
0419     if (ret < 0)
0420         return ret;
0421 
0422     ret = regmap_write(db->regmap_dm, DM9051_EPCR, EPCR_EPOS | EPCR_ERPRW);
0423     if (ret)
0424         return ret;
0425 
0426     ret = dm9051_epcr_poll(db);
0427     if (ret)
0428         return ret;
0429 
0430     return regmap_write(db->regmap_dm, DM9051_EPCR, 0);
0431 }
0432 
0433 static int dm9051_mdio_read(struct mii_bus *bus, int addr, int regnum)
0434 {
0435     struct board_info *db = bus->priv;
0436     unsigned int val = 0xffff;
0437     int ret;
0438 
0439     if (addr == DM9051_PHY_ADDR) {
0440         ret = dm9051_phyread(db, regnum, &val);
0441         if (ret)
0442             return ret;
0443     }
0444 
0445     return val;
0446 }
0447 
0448 static int dm9051_mdio_write(struct mii_bus *bus, int addr, int regnum, u16 val)
0449 {
0450     struct board_info *db = bus->priv;
0451 
0452     if (addr == DM9051_PHY_ADDR)
0453         return dm9051_phywrite(db, regnum, val);
0454 
0455     return -ENODEV;
0456 }
0457 
0458 static void dm9051_reg_lock_mutex(void *dbcontext)
0459 {
0460     struct board_info *db = dbcontext;
0461 
0462     mutex_lock(&db->reg_mutex);
0463 }
0464 
0465 static void dm9051_reg_unlock_mutex(void *dbcontext)
0466 {
0467     struct board_info *db = dbcontext;
0468 
0469     mutex_unlock(&db->reg_mutex);
0470 }
0471 
0472 static struct regmap_config regconfigdm = {
0473     .reg_bits = 8,
0474     .val_bits = 8,
0475     .max_register = 0xff,
0476     .reg_stride = 1,
0477     .cache_type = REGCACHE_NONE,
0478     .read_flag_mask = 0,
0479     .write_flag_mask = DM_SPI_WR,
0480     .val_format_endian = REGMAP_ENDIAN_LITTLE,
0481     .lock = dm9051_reg_lock_mutex,
0482     .unlock = dm9051_reg_unlock_mutex,
0483 };
0484 
0485 static struct regmap_config regconfigdmbulk = {
0486     .reg_bits = 8,
0487     .val_bits = 8,
0488     .max_register = 0xff,
0489     .reg_stride = 1,
0490     .cache_type = REGCACHE_NONE,
0491     .read_flag_mask = 0,
0492     .write_flag_mask = DM_SPI_WR,
0493     .val_format_endian = REGMAP_ENDIAN_LITTLE,
0494     .lock = dm9051_reg_lock_mutex,
0495     .unlock = dm9051_reg_unlock_mutex,
0496     .use_single_read = true,
0497     .use_single_write = true,
0498 };
0499 
0500 static int dm9051_map_init(struct spi_device *spi, struct board_info *db)
0501 {
0502     /* create two regmap instances,
0503      * split read/write and bulk_read/bulk_write to individual regmap
0504      * to resolve regmap execution confliction problem
0505      */
0506     regconfigdm.lock_arg = db;
0507     db->regmap_dm = devm_regmap_init_spi(db->spidev, &regconfigdm);
0508     if (IS_ERR(db->regmap_dm))
0509         return PTR_ERR(db->regmap_dm);
0510 
0511     regconfigdmbulk.lock_arg = db;
0512     db->regmap_dmbulk = devm_regmap_init_spi(db->spidev, &regconfigdmbulk);
0513     if (IS_ERR(db->regmap_dmbulk))
0514         return PTR_ERR(db->regmap_dmbulk);
0515 
0516     return 0;
0517 }
0518 
0519 static int dm9051_map_chipid(struct board_info *db)
0520 {
0521     struct device *dev = &db->spidev->dev;
0522     unsigned short wid;
0523     u8 buff[6];
0524     int ret;
0525 
0526     ret = dm9051_get_regs(db, DM9051_VIDL, buff, sizeof(buff));
0527     if (ret < 0)
0528         return ret;
0529 
0530     wid = get_unaligned_le16(buff + 2);
0531     if (wid != DM9051_ID) {
0532         dev_err(dev, "chipid error as %04x !\n", wid);
0533         return -ENODEV;
0534     }
0535 
0536     dev_info(dev, "chip %04x found\n", wid);
0537     return 0;
0538 }
0539 
0540 /* Read DM9051_PAR registers which is the mac address loaded from EEPROM while power-on
0541  */
0542 static int dm9051_map_etherdev_par(struct net_device *ndev, struct board_info *db)
0543 {
0544     u8 addr[ETH_ALEN];
0545     int ret;
0546 
0547     ret = dm9051_get_regs(db, DM9051_PAR, addr, sizeof(addr));
0548     if (ret < 0)
0549         return ret;
0550 
0551     if (!is_valid_ether_addr(addr)) {
0552         eth_hw_addr_random(ndev);
0553 
0554         ret = dm9051_set_regs(db, DM9051_PAR, ndev->dev_addr, sizeof(ndev->dev_addr));
0555         if (ret < 0)
0556             return ret;
0557 
0558         dev_dbg(&db->spidev->dev, "Use random MAC address\n");
0559         return 0;
0560     }
0561 
0562     eth_hw_addr_set(ndev, addr);
0563     return 0;
0564 }
0565 
0566 /* ethtool-ops
0567  */
0568 static void dm9051_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
0569 {
0570     strscpy(info->driver, DRVNAME_9051, sizeof(info->driver));
0571 }
0572 
0573 static void dm9051_set_msglevel(struct net_device *ndev, u32 value)
0574 {
0575     struct board_info *db = to_dm9051_board(ndev);
0576 
0577     db->msg_enable = value;
0578 }
0579 
0580 static u32 dm9051_get_msglevel(struct net_device *ndev)
0581 {
0582     struct board_info *db = to_dm9051_board(ndev);
0583 
0584     return db->msg_enable;
0585 }
0586 
0587 static int dm9051_get_eeprom_len(struct net_device *dev)
0588 {
0589     return 128;
0590 }
0591 
0592 static int dm9051_get_eeprom(struct net_device *ndev,
0593                  struct ethtool_eeprom *ee, u8 *data)
0594 {
0595     struct board_info *db = to_dm9051_board(ndev);
0596     int offset = ee->offset;
0597     int len = ee->len;
0598     int i, ret;
0599 
0600     if ((len | offset) & 1)
0601         return -EINVAL;
0602 
0603     ee->magic = DM_EEPROM_MAGIC;
0604 
0605     for (i = 0; i < len; i += 2) {
0606         ret = dm9051_eeprom_read(db, (offset + i) / 2, data + i);
0607         if (ret)
0608             break;
0609     }
0610     return ret;
0611 }
0612 
0613 static int dm9051_set_eeprom(struct net_device *ndev,
0614                  struct ethtool_eeprom *ee, u8 *data)
0615 {
0616     struct board_info *db = to_dm9051_board(ndev);
0617     int offset = ee->offset;
0618     int len = ee->len;
0619     int i, ret;
0620 
0621     if ((len | offset) & 1)
0622         return -EINVAL;
0623 
0624     if (ee->magic != DM_EEPROM_MAGIC)
0625         return -EINVAL;
0626 
0627     for (i = 0; i < len; i += 2) {
0628         ret = dm9051_eeprom_write(db, (offset + i) / 2, data + i);
0629         if (ret)
0630             break;
0631     }
0632     return ret;
0633 }
0634 
0635 static void dm9051_get_pauseparam(struct net_device *ndev,
0636                   struct ethtool_pauseparam *pause)
0637 {
0638     struct board_info *db = to_dm9051_board(ndev);
0639 
0640     *pause = db->pause;
0641 }
0642 
0643 static int dm9051_set_pauseparam(struct net_device *ndev,
0644                  struct ethtool_pauseparam *pause)
0645 {
0646     struct board_info *db = to_dm9051_board(ndev);
0647 
0648     db->pause = *pause;
0649 
0650     if (pause->autoneg == AUTONEG_DISABLE)
0651         return dm9051_update_fcr(db);
0652 
0653     phy_set_sym_pause(db->phydev, pause->rx_pause, pause->tx_pause,
0654               pause->autoneg);
0655     phy_start_aneg(db->phydev);
0656     return 0;
0657 }
0658 
0659 static const struct ethtool_ops dm9051_ethtool_ops = {
0660     .get_drvinfo = dm9051_get_drvinfo,
0661     .get_link_ksettings = phy_ethtool_get_link_ksettings,
0662     .set_link_ksettings = phy_ethtool_set_link_ksettings,
0663     .get_msglevel = dm9051_get_msglevel,
0664     .set_msglevel = dm9051_set_msglevel,
0665     .nway_reset = phy_ethtool_nway_reset,
0666     .get_link = ethtool_op_get_link,
0667     .get_eeprom_len = dm9051_get_eeprom_len,
0668     .get_eeprom = dm9051_get_eeprom,
0669     .set_eeprom = dm9051_set_eeprom,
0670     .get_pauseparam = dm9051_get_pauseparam,
0671     .set_pauseparam = dm9051_set_pauseparam,
0672 };
0673 
0674 static int dm9051_all_start(struct board_info *db)
0675 {
0676     int ret;
0677 
0678     /* GPR power on of the internal phy
0679      */
0680     ret = dm9051_set_reg(db, DM9051_GPR, 0);
0681     if (ret)
0682         return ret;
0683 
0684     /* dm9051 chip registers could not be accessed within 1 ms
0685      * after GPR power on, delay 1 ms is essential
0686      */
0687     msleep(1);
0688 
0689     ret = dm9051_core_reset(db);
0690     if (ret)
0691         return ret;
0692 
0693     return dm9051_enable_interrupt(db);
0694 }
0695 
0696 static int dm9051_all_stop(struct board_info *db)
0697 {
0698     int ret;
0699 
0700     /* GPR power off of the internal phy,
0701      * The internal phy still could be accessed after this GPR power off control
0702      */
0703     ret = dm9051_set_reg(db, DM9051_GPR, GPR_PHY_OFF);
0704     if (ret)
0705         return ret;
0706 
0707     return dm9051_set_reg(db, DM9051_RCR, RCR_RX_DISABLE);
0708 }
0709 
0710 /* fifo reset while rx error found
0711  */
0712 static int dm9051_all_restart(struct board_info *db)
0713 {
0714     struct net_device *ndev = db->ndev;
0715     int ret;
0716 
0717     ret = dm9051_core_reset(db);
0718     if (ret)
0719         return ret;
0720 
0721     ret = dm9051_enable_interrupt(db);
0722     if (ret)
0723         return ret;
0724 
0725     netdev_dbg(ndev, " rxstatus_Er & rxlen_Er %d, RST_c %d\n",
0726            db->bc.status_err_counter + db->bc.large_err_counter,
0727            db->bc.fifo_rst_counter);
0728 
0729     ret = dm9051_set_recv(db);
0730     if (ret)
0731         return ret;
0732 
0733     return dm9051_set_fcr(db);
0734 }
0735 
0736 /* read packets from the fifo memory
0737  * return value,
0738  *  > 0 - read packet number, caller can repeat the rx operation
0739  *    0 - no error, caller need stop further rx operation
0740  *  -EBUSY - read data error, caller escape from rx operation
0741  */
0742 static int dm9051_loop_rx(struct board_info *db)
0743 {
0744     struct net_device *ndev = db->ndev;
0745     unsigned int rxbyte;
0746     int ret, rxlen;
0747     struct sk_buff *skb;
0748     u8 *rdptr;
0749     int scanrr = 0;
0750 
0751     do {
0752         ret = dm9051_read_mem(db, DM_SPI_MRCMDX, &rxbyte, 2);
0753         if (ret)
0754             return ret;
0755 
0756         if ((rxbyte & GENMASK(7, 0)) != DM9051_PKT_RDY)
0757             break; /* exhaust-empty */
0758 
0759         ret = dm9051_read_mem(db, DM_SPI_MRCMD, &db->rxhdr, DM_RXHDR_SIZE);
0760         if (ret)
0761             return ret;
0762 
0763         ret = dm9051_stop_mrcmd(db);
0764         if (ret)
0765             return ret;
0766 
0767         rxlen = le16_to_cpu(db->rxhdr.rxlen);
0768         if (db->rxhdr.status & RSR_ERR_BITS || rxlen > DM9051_PKT_MAX) {
0769             netdev_dbg(ndev, "rxhdr-byte (%02x)\n",
0770                    db->rxhdr.headbyte);
0771 
0772             if (db->rxhdr.status & RSR_ERR_BITS) {
0773                 db->bc.status_err_counter++;
0774                 netdev_dbg(ndev, "check rxstatus-error (%02x)\n",
0775                        db->rxhdr.status);
0776             } else {
0777                 db->bc.large_err_counter++;
0778                 netdev_dbg(ndev, "check rxlen large-error (%d > %d)\n",
0779                        rxlen, DM9051_PKT_MAX);
0780             }
0781             return dm9051_all_restart(db);
0782         }
0783 
0784         skb = dev_alloc_skb(rxlen);
0785         if (!skb) {
0786             ret = dm9051_dumpblk(db, DM_SPI_MRCMD, rxlen);
0787             if (ret)
0788                 return ret;
0789             return scanrr;
0790         }
0791 
0792         rdptr = skb_put(skb, rxlen - 4);
0793         ret = dm9051_read_mem(db, DM_SPI_MRCMD, rdptr, rxlen);
0794         if (ret) {
0795             db->bc.rx_err_counter++;
0796             dev_kfree_skb(skb);
0797             return ret;
0798         }
0799 
0800         ret = dm9051_stop_mrcmd(db);
0801         if (ret)
0802             return ret;
0803 
0804         skb->protocol = eth_type_trans(skb, db->ndev);
0805         if (db->ndev->features & NETIF_F_RXCSUM)
0806             skb_checksum_none_assert(skb);
0807         netif_rx(skb);
0808         db->ndev->stats.rx_bytes += rxlen;
0809         db->ndev->stats.rx_packets++;
0810         scanrr++;
0811     } while (!ret);
0812 
0813     return scanrr;
0814 }
0815 
0816 /* transmit a packet,
0817  * return value,
0818  *   0 - succeed
0819  *  -ETIMEDOUT - timeout error
0820  */
0821 static int dm9051_single_tx(struct board_info *db, u8 *buff, unsigned int len)
0822 {
0823     int ret;
0824 
0825     ret = dm9051_nsr_poll(db);
0826     if (ret)
0827         return ret;
0828 
0829     ret = dm9051_write_mem(db, DM_SPI_MWCMD, buff, len);
0830     if (ret)
0831         return ret;
0832 
0833     ret = dm9051_set_regs(db, DM9051_TXPLL, &len, 2);
0834     if (ret < 0)
0835         return ret;
0836 
0837     return dm9051_set_reg(db, DM9051_TCR, TCR_TXREQ);
0838 }
0839 
0840 static int dm9051_loop_tx(struct board_info *db)
0841 {
0842     struct net_device *ndev = db->ndev;
0843     int ntx = 0;
0844     int ret;
0845 
0846     while (!skb_queue_empty(&db->txq)) {
0847         struct sk_buff *skb;
0848         unsigned int len;
0849 
0850         skb = skb_dequeue(&db->txq);
0851         if (skb) {
0852             ntx++;
0853             ret = dm9051_single_tx(db, skb->data, skb->len);
0854             len = skb->len;
0855             dev_kfree_skb(skb);
0856             if (ret < 0) {
0857                 db->bc.tx_err_counter++;
0858                 return 0;
0859             }
0860             ndev->stats.tx_bytes += len;
0861             ndev->stats.tx_packets++;
0862         }
0863 
0864         if (netif_queue_stopped(ndev) &&
0865             (skb_queue_len(&db->txq) < DM9051_TX_QUE_LO_WATER))
0866             netif_wake_queue(ndev);
0867     }
0868 
0869     return ntx;
0870 }
0871 
0872 static irqreturn_t dm9051_rx_threaded_irq(int irq, void *pw)
0873 {
0874     struct board_info *db = pw;
0875     int result, result_tx;
0876 
0877     mutex_lock(&db->spi_lockm);
0878 
0879     result = dm9051_disable_interrupt(db);
0880     if (result)
0881         goto out_unlock;
0882 
0883     result = dm9051_clear_interrupt(db);
0884     if (result)
0885         goto out_unlock;
0886 
0887     do {
0888         result = dm9051_loop_rx(db); /* threaded irq rx */
0889         if (result < 0)
0890             goto out_unlock;
0891         result_tx = dm9051_loop_tx(db); /* more tx better performance */
0892         if (result_tx < 0)
0893             goto out_unlock;
0894     } while (result > 0);
0895 
0896     dm9051_enable_interrupt(db);
0897 
0898     /* To exit and has mutex unlock while rx or tx error
0899      */
0900 out_unlock:
0901     mutex_unlock(&db->spi_lockm);
0902 
0903     return IRQ_HANDLED;
0904 }
0905 
0906 static void dm9051_tx_delay(struct work_struct *work)
0907 {
0908     struct board_info *db = container_of(work, struct board_info, tx_work);
0909     int result;
0910 
0911     mutex_lock(&db->spi_lockm);
0912 
0913     result = dm9051_loop_tx(db);
0914     if (result < 0)
0915         netdev_err(db->ndev, "transmit packet error\n");
0916 
0917     mutex_unlock(&db->spi_lockm);
0918 }
0919 
0920 static void dm9051_rxctl_delay(struct work_struct *work)
0921 {
0922     struct board_info *db = container_of(work, struct board_info, rxctrl_work);
0923     struct net_device *ndev = db->ndev;
0924     int result;
0925 
0926     mutex_lock(&db->spi_lockm);
0927 
0928     result = dm9051_set_regs(db, DM9051_PAR, ndev->dev_addr, sizeof(ndev->dev_addr));
0929     if (result < 0)
0930         goto out_unlock;
0931 
0932     dm9051_set_recv(db);
0933 
0934     /* To has mutex unlock and return from this function if regmap function fail
0935      */
0936 out_unlock:
0937     mutex_unlock(&db->spi_lockm);
0938 }
0939 
0940 /* Open network device
0941  * Called when the network device is marked active, such as a user executing
0942  * 'ifconfig up' on the device
0943  */
0944 static int dm9051_open(struct net_device *ndev)
0945 {
0946     struct board_info *db = to_dm9051_board(ndev);
0947     struct spi_device *spi = db->spidev;
0948     int ret;
0949 
0950     db->imr_all = IMR_PAR | IMR_PRM;
0951     db->lcr_all = LMCR_MODE1;
0952     db->rctl.rcr_all = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
0953     memset(db->rctl.hash_table, 0, sizeof(db->rctl.hash_table));
0954 
0955     ndev->irq = spi->irq; /* by dts */
0956     ret = request_threaded_irq(spi->irq, NULL, dm9051_rx_threaded_irq,
0957                    dm9051_irq_flag(db) | IRQF_ONESHOT,
0958                    ndev->name, db);
0959     if (ret < 0) {
0960         netdev_err(ndev, "failed to get irq\n");
0961         return ret;
0962     }
0963 
0964     phy_support_sym_pause(db->phydev);
0965     phy_start(db->phydev);
0966 
0967     /* flow control parameters init */
0968     db->pause.rx_pause = true;
0969     db->pause.tx_pause = true;
0970     db->pause.autoneg = AUTONEG_DISABLE;
0971 
0972     if (db->phydev->autoneg)
0973         db->pause.autoneg = AUTONEG_ENABLE;
0974 
0975     ret = dm9051_all_start(db);
0976     if (ret) {
0977         phy_stop(db->phydev);
0978         free_irq(spi->irq, db);
0979         return ret;
0980     }
0981 
0982     netif_wake_queue(ndev);
0983 
0984     return 0;
0985 }
0986 
0987 /* Close network device
0988  * Called to close down a network device which has been active. Cancel any
0989  * work, shutdown the RX and TX process and then place the chip into a low
0990  * power state while it is not being used
0991  */
0992 static int dm9051_stop(struct net_device *ndev)
0993 {
0994     struct board_info *db = to_dm9051_board(ndev);
0995     int ret;
0996 
0997     ret = dm9051_all_stop(db);
0998     if (ret)
0999         return ret;
1000 
1001     flush_work(&db->tx_work);
1002     flush_work(&db->rxctrl_work);
1003 
1004     phy_stop(db->phydev);
1005 
1006     free_irq(db->spidev->irq, db);
1007 
1008     netif_stop_queue(ndev);
1009 
1010     skb_queue_purge(&db->txq);
1011 
1012     return 0;
1013 }
1014 
1015 /* event: play a schedule starter in condition
1016  */
1017 static netdev_tx_t dm9051_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1018 {
1019     struct board_info *db = to_dm9051_board(ndev);
1020 
1021     skb_queue_tail(&db->txq, skb);
1022     if (skb_queue_len(&db->txq) > DM9051_TX_QUE_HI_WATER)
1023         netif_stop_queue(ndev); /* enforce limit queue size */
1024 
1025     schedule_work(&db->tx_work);
1026 
1027     return NETDEV_TX_OK;
1028 }
1029 
1030 /* event: play with a schedule starter
1031  */
1032 static void dm9051_set_rx_mode(struct net_device *ndev)
1033 {
1034     struct board_info *db = to_dm9051_board(ndev);
1035     struct dm9051_rxctrl rxctrl;
1036     struct netdev_hw_addr *ha;
1037     u8 rcr = RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN;
1038     u32 hash_val;
1039 
1040     memset(&rxctrl, 0, sizeof(rxctrl));
1041 
1042     /* rx control */
1043     if (ndev->flags & IFF_PROMISC) {
1044         rcr |= RCR_PRMSC;
1045         netdev_dbg(ndev, "set_multicast rcr |= RCR_PRMSC, rcr= %02x\n", rcr);
1046     }
1047 
1048     if (ndev->flags & IFF_ALLMULTI) {
1049         rcr |= RCR_ALL;
1050         netdev_dbg(ndev, "set_multicast rcr |= RCR_ALLMULTI, rcr= %02x\n", rcr);
1051     }
1052 
1053     rxctrl.rcr_all = rcr;
1054 
1055     /* broadcast address */
1056     rxctrl.hash_table[0] = 0;
1057     rxctrl.hash_table[1] = 0;
1058     rxctrl.hash_table[2] = 0;
1059     rxctrl.hash_table[3] = 0x8000;
1060 
1061     /* the multicast address in Hash Table : 64 bits */
1062     netdev_for_each_mc_addr(ha, ndev) {
1063         hash_val = ether_crc_le(ETH_ALEN, ha->addr) & GENMASK(5, 0);
1064         rxctrl.hash_table[hash_val / 16] |= BIT(0) << (hash_val % 16);
1065     }
1066 
1067     /* schedule work to do the actual set of the data if needed */
1068 
1069     if (memcmp(&db->rctl, &rxctrl, sizeof(rxctrl))) {
1070         memcpy(&db->rctl, &rxctrl, sizeof(rxctrl));
1071         schedule_work(&db->rxctrl_work);
1072     }
1073 }
1074 
1075 /* event: write into the mac registers and eeprom directly
1076  */
1077 static int dm9051_set_mac_address(struct net_device *ndev, void *p)
1078 {
1079     struct board_info *db = to_dm9051_board(ndev);
1080     int ret;
1081 
1082     ret = eth_prepare_mac_addr_change(ndev, p);
1083     if (ret < 0)
1084         return ret;
1085 
1086     eth_commit_mac_addr_change(ndev, p);
1087     return dm9051_set_regs(db, DM9051_PAR, ndev->dev_addr, sizeof(ndev->dev_addr));
1088 }
1089 
1090 static const struct net_device_ops dm9051_netdev_ops = {
1091     .ndo_open = dm9051_open,
1092     .ndo_stop = dm9051_stop,
1093     .ndo_start_xmit = dm9051_start_xmit,
1094     .ndo_set_rx_mode = dm9051_set_rx_mode,
1095     .ndo_validate_addr = eth_validate_addr,
1096     .ndo_set_mac_address = dm9051_set_mac_address,
1097 };
1098 
1099 static void dm9051_operation_clear(struct board_info *db)
1100 {
1101     db->bc.status_err_counter = 0;
1102     db->bc.large_err_counter = 0;
1103     db->bc.rx_err_counter = 0;
1104     db->bc.tx_err_counter = 0;
1105     db->bc.fifo_rst_counter = 0;
1106 }
1107 
1108 static int dm9051_mdio_register(struct board_info *db)
1109 {
1110     struct spi_device *spi = db->spidev;
1111     int ret;
1112 
1113     db->mdiobus = devm_mdiobus_alloc(&spi->dev);
1114     if (!db->mdiobus)
1115         return -ENOMEM;
1116 
1117     db->mdiobus->priv = db;
1118     db->mdiobus->read = dm9051_mdio_read;
1119     db->mdiobus->write = dm9051_mdio_write;
1120     db->mdiobus->name = "dm9051-mdiobus";
1121     db->mdiobus->phy_mask = (u32)~BIT(1);
1122     db->mdiobus->parent = &spi->dev;
1123     snprintf(db->mdiobus->id, MII_BUS_ID_SIZE,
1124          "dm9051-%s.%u", dev_name(&spi->dev), spi->chip_select);
1125 
1126     ret = devm_mdiobus_register(&spi->dev, db->mdiobus);
1127     if (ret)
1128         dev_err(&spi->dev, "Could not register MDIO bus\n");
1129 
1130     return ret;
1131 }
1132 
1133 static void dm9051_handle_link_change(struct net_device *ndev)
1134 {
1135     struct board_info *db = to_dm9051_board(ndev);
1136 
1137     phy_print_status(db->phydev);
1138 
1139     /* only write pause settings to mac. since mac and phy are integrated
1140      * together, such as link state, speed and duplex are sync already
1141      */
1142     if (db->phydev->link) {
1143         if (db->phydev->pause) {
1144             db->pause.rx_pause = true;
1145             db->pause.tx_pause = true;
1146         }
1147         dm9051_update_fcr(db);
1148     }
1149 }
1150 
1151 /* phy connect as poll mode
1152  */
1153 static int dm9051_phy_connect(struct board_info *db)
1154 {
1155     char phy_id[MII_BUS_ID_SIZE + 3];
1156 
1157     snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1158          db->mdiobus->id, DM9051_PHY_ADDR);
1159 
1160     db->phydev = phy_connect(db->ndev, phy_id, dm9051_handle_link_change,
1161                  PHY_INTERFACE_MODE_MII);
1162     if (IS_ERR(db->phydev))
1163         return PTR_ERR_OR_ZERO(db->phydev);
1164     return 0;
1165 }
1166 
1167 static int dm9051_probe(struct spi_device *spi)
1168 {
1169     struct device *dev = &spi->dev;
1170     struct net_device *ndev;
1171     struct board_info *db;
1172     int ret;
1173 
1174     ndev = devm_alloc_etherdev(dev, sizeof(struct board_info));
1175     if (!ndev)
1176         return -ENOMEM;
1177 
1178     SET_NETDEV_DEV(ndev, dev);
1179     dev_set_drvdata(dev, ndev);
1180 
1181     db = netdev_priv(ndev);
1182 
1183     db->msg_enable = 0;
1184     db->spidev = spi;
1185     db->ndev = ndev;
1186 
1187     ndev->netdev_ops = &dm9051_netdev_ops;
1188     ndev->ethtool_ops = &dm9051_ethtool_ops;
1189 
1190     mutex_init(&db->spi_lockm);
1191     mutex_init(&db->reg_mutex);
1192 
1193     INIT_WORK(&db->rxctrl_work, dm9051_rxctl_delay);
1194     INIT_WORK(&db->tx_work, dm9051_tx_delay);
1195 
1196     ret = dm9051_map_init(spi, db);
1197     if (ret)
1198         return ret;
1199 
1200     ret = dm9051_map_chipid(db);
1201     if (ret)
1202         return ret;
1203 
1204     ret = dm9051_map_etherdev_par(ndev, db);
1205     if (ret < 0)
1206         return ret;
1207 
1208     ret = dm9051_mdio_register(db);
1209     if (ret)
1210         return ret;
1211 
1212     ret = dm9051_phy_connect(db);
1213     if (ret)
1214         return ret;
1215 
1216     dm9051_operation_clear(db);
1217     skb_queue_head_init(&db->txq);
1218 
1219     ret = devm_register_netdev(dev, ndev);
1220     if (ret) {
1221         phy_disconnect(db->phydev);
1222         return dev_err_probe(dev, ret, "device register failed");
1223     }
1224 
1225     return 0;
1226 }
1227 
1228 static void dm9051_drv_remove(struct spi_device *spi)
1229 {
1230     struct device *dev = &spi->dev;
1231     struct net_device *ndev = dev_get_drvdata(dev);
1232     struct board_info *db = to_dm9051_board(ndev);
1233 
1234     phy_disconnect(db->phydev);
1235 }
1236 
1237 static const struct of_device_id dm9051_match_table[] = {
1238     { .compatible = "davicom,dm9051" },
1239     {}
1240 };
1241 
1242 static const struct spi_device_id dm9051_id_table[] = {
1243     { "dm9051", 0 },
1244     {}
1245 };
1246 
1247 static struct spi_driver dm9051_driver = {
1248     .driver = {
1249         .name = DRVNAME_9051,
1250         .of_match_table = dm9051_match_table,
1251     },
1252     .probe = dm9051_probe,
1253     .remove = dm9051_drv_remove,
1254     .id_table = dm9051_id_table,
1255 };
1256 module_spi_driver(dm9051_driver);
1257 
1258 MODULE_AUTHOR("Joseph CHANG <joseph_chang@davicom.com.tw>");
1259 MODULE_DESCRIPTION("Davicom DM9051 network SPI driver");
1260 MODULE_LICENSE("GPL");
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