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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Register definitions for Gemini GMAC Ethernet device driver
0003  *
0004  * Copyright (C) 2006 Storlink, Corp.
0005  * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
0006  * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
0007  * Copytight (C) 2017 Linus Walleij <linus.walleij@linaro.org>
0008  */
0009 #ifndef _GEMINI_ETHERNET_H
0010 #define _GEMINI_ETHERNET_H
0011 
0012 #include <linux/bitops.h>
0013 
0014 /* Base Registers */
0015 #define TOE_NONTOE_QUE_HDR_BASE     0x2000
0016 #define TOE_TOE_QUE_HDR_BASE        0x3000
0017 
0018 /* Queue ID */
0019 #define TOE_SW_FREE_QID         0x00
0020 #define TOE_HW_FREE_QID         0x01
0021 #define TOE_GMAC0_SW_TXQ0_QID       0x02
0022 #define TOE_GMAC0_SW_TXQ1_QID       0x03
0023 #define TOE_GMAC0_SW_TXQ2_QID       0x04
0024 #define TOE_GMAC0_SW_TXQ3_QID       0x05
0025 #define TOE_GMAC0_SW_TXQ4_QID       0x06
0026 #define TOE_GMAC0_SW_TXQ5_QID       0x07
0027 #define TOE_GMAC0_HW_TXQ0_QID       0x08
0028 #define TOE_GMAC0_HW_TXQ1_QID       0x09
0029 #define TOE_GMAC0_HW_TXQ2_QID       0x0A
0030 #define TOE_GMAC0_HW_TXQ3_QID       0x0B
0031 #define TOE_GMAC1_SW_TXQ0_QID       0x12
0032 #define TOE_GMAC1_SW_TXQ1_QID       0x13
0033 #define TOE_GMAC1_SW_TXQ2_QID       0x14
0034 #define TOE_GMAC1_SW_TXQ3_QID       0x15
0035 #define TOE_GMAC1_SW_TXQ4_QID       0x16
0036 #define TOE_GMAC1_SW_TXQ5_QID       0x17
0037 #define TOE_GMAC1_HW_TXQ0_QID       0x18
0038 #define TOE_GMAC1_HW_TXQ1_QID       0x19
0039 #define TOE_GMAC1_HW_TXQ2_QID       0x1A
0040 #define TOE_GMAC1_HW_TXQ3_QID       0x1B
0041 #define TOE_GMAC0_DEFAULT_QID       0x20
0042 #define TOE_GMAC1_DEFAULT_QID       0x21
0043 #define TOE_CLASSIFICATION_QID(x)   (0x22 + x)  /* 0x22 ~ 0x2F */
0044 #define TOE_TOE_QID(x)          (0x40 + x)  /* 0x40 ~ 0x7F */
0045 
0046 /* TOE DMA Queue Size should be 2^n, n = 6...12
0047  * TOE DMA Queues are the following queue types:
0048  *      SW Free Queue, HW Free Queue,
0049  *      GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
0050  * The base address and descriptor number are configured at
0051  * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
0052  */
0053 #define GET_WPTR(addr)          readw((addr) + 2)
0054 #define GET_RPTR(addr)          readw((addr))
0055 #define SET_WPTR(addr, data)        writew((data), (addr) + 2)
0056 #define SET_RPTR(addr, data)        writew((data), (addr))
0057 #define __RWPTR_NEXT(x, mask)       (((unsigned int)(x) + 1) & (mask))
0058 #define __RWPTR_PREV(x, mask)       (((unsigned int)(x) - 1) & (mask))
0059 #define __RWPTR_DISTANCE(r, w, mask)    (((unsigned int)(w) - (r)) & (mask))
0060 #define __RWPTR_MASK(order)     ((1 << (order)) - 1)
0061 #define RWPTR_NEXT(x, order)        __RWPTR_NEXT((x), __RWPTR_MASK((order)))
0062 #define RWPTR_PREV(x, order)        __RWPTR_PREV((x), __RWPTR_MASK((order)))
0063 #define RWPTR_DISTANCE(r, w, order) __RWPTR_DISTANCE((r), (w), \
0064                         __RWPTR_MASK((order)))
0065 
0066 /* Global registers */
0067 #define GLOBAL_TOE_VERSION_REG      0x0000
0068 #define GLOBAL_SW_FREEQ_BASE_SIZE_REG   0x0004
0069 #define GLOBAL_HW_FREEQ_BASE_SIZE_REG   0x0008
0070 #define GLOBAL_DMA_SKB_SIZE_REG     0x0010
0071 #define GLOBAL_SWFQ_RWPTR_REG       0x0014
0072 #define GLOBAL_HWFQ_RWPTR_REG       0x0018
0073 #define GLOBAL_INTERRUPT_STATUS_0_REG   0x0020
0074 #define GLOBAL_INTERRUPT_ENABLE_0_REG   0x0024
0075 #define GLOBAL_INTERRUPT_SELECT_0_REG   0x0028
0076 #define GLOBAL_INTERRUPT_STATUS_1_REG   0x0030
0077 #define GLOBAL_INTERRUPT_ENABLE_1_REG   0x0034
0078 #define GLOBAL_INTERRUPT_SELECT_1_REG   0x0038
0079 #define GLOBAL_INTERRUPT_STATUS_2_REG   0x0040
0080 #define GLOBAL_INTERRUPT_ENABLE_2_REG   0x0044
0081 #define GLOBAL_INTERRUPT_SELECT_2_REG   0x0048
0082 #define GLOBAL_INTERRUPT_STATUS_3_REG   0x0050
0083 #define GLOBAL_INTERRUPT_ENABLE_3_REG   0x0054
0084 #define GLOBAL_INTERRUPT_SELECT_3_REG   0x0058
0085 #define GLOBAL_INTERRUPT_STATUS_4_REG   0x0060
0086 #define GLOBAL_INTERRUPT_ENABLE_4_REG   0x0064
0087 #define GLOBAL_INTERRUPT_SELECT_4_REG   0x0068
0088 #define GLOBAL_HASH_TABLE_BASE_REG  0x006C
0089 #define GLOBAL_QUEUE_THRESHOLD_REG  0x0070
0090 
0091 /* GMAC 0/1 DMA/TOE register */
0092 #define GMAC_DMA_CTRL_REG       0x0000
0093 #define GMAC_TX_WEIGHTING_CTRL_0_REG    0x0004
0094 #define GMAC_TX_WEIGHTING_CTRL_1_REG    0x0008
0095 #define GMAC_SW_TX_QUEUE0_PTR_REG   0x000C
0096 #define GMAC_SW_TX_QUEUE1_PTR_REG   0x0010
0097 #define GMAC_SW_TX_QUEUE2_PTR_REG   0x0014
0098 #define GMAC_SW_TX_QUEUE3_PTR_REG   0x0018
0099 #define GMAC_SW_TX_QUEUE4_PTR_REG   0x001C
0100 #define GMAC_SW_TX_QUEUE5_PTR_REG   0x0020
0101 #define GMAC_SW_TX_QUEUE_PTR_REG(i) (GMAC_SW_TX_QUEUE0_PTR_REG + 4 * (i))
0102 #define GMAC_HW_TX_QUEUE0_PTR_REG   0x0024
0103 #define GMAC_HW_TX_QUEUE1_PTR_REG   0x0028
0104 #define GMAC_HW_TX_QUEUE2_PTR_REG   0x002C
0105 #define GMAC_HW_TX_QUEUE3_PTR_REG   0x0030
0106 #define GMAC_HW_TX_QUEUE_PTR_REG(i) (GMAC_HW_TX_QUEUE0_PTR_REG + 4 * (i))
0107 #define GMAC_DMA_TX_FIRST_DESC_REG  0x0038
0108 #define GMAC_DMA_TX_CURR_DESC_REG   0x003C
0109 #define GMAC_DMA_TX_DESC_WORD0_REG  0x0040
0110 #define GMAC_DMA_TX_DESC_WORD1_REG  0x0044
0111 #define GMAC_DMA_TX_DESC_WORD2_REG  0x0048
0112 #define GMAC_DMA_TX_DESC_WORD3_REG  0x004C
0113 #define GMAC_SW_TX_QUEUE_BASE_REG   0x0050
0114 #define GMAC_HW_TX_QUEUE_BASE_REG   0x0054
0115 #define GMAC_DMA_RX_FIRST_DESC_REG  0x0058
0116 #define GMAC_DMA_RX_CURR_DESC_REG   0x005C
0117 #define GMAC_DMA_RX_DESC_WORD0_REG  0x0060
0118 #define GMAC_DMA_RX_DESC_WORD1_REG  0x0064
0119 #define GMAC_DMA_RX_DESC_WORD2_REG  0x0068
0120 #define GMAC_DMA_RX_DESC_WORD3_REG  0x006C
0121 #define GMAC_HASH_ENGINE_REG0       0x0070
0122 #define GMAC_HASH_ENGINE_REG1       0x0074
0123 /* matching rule 0 Control register 0 */
0124 #define GMAC_MR0CR0         0x0078
0125 #define GMAC_MR0CR1         0x007C
0126 #define GMAC_MR0CR2         0x0080
0127 #define GMAC_MR1CR0         0x0084
0128 #define GMAC_MR1CR1         0x0088
0129 #define GMAC_MR1CR2         0x008C
0130 #define GMAC_MR2CR0         0x0090
0131 #define GMAC_MR2CR1         0x0094
0132 #define GMAC_MR2CR2         0x0098
0133 #define GMAC_MR3CR0         0x009C
0134 #define GMAC_MR3CR1         0x00A0
0135 #define GMAC_MR3CR2         0x00A4
0136 /* Support Protocol Register 0 */
0137 #define GMAC_SPR0           0x00A8
0138 #define GMAC_SPR1           0x00AC
0139 #define GMAC_SPR2           0x00B0
0140 #define GMAC_SPR3           0x00B4
0141 #define GMAC_SPR4           0x00B8
0142 #define GMAC_SPR5           0x00BC
0143 #define GMAC_SPR6           0x00C0
0144 #define GMAC_SPR7           0x00C4
0145 /* GMAC Hash/Rx/Tx AHB Weighting register */
0146 #define GMAC_AHB_WEIGHT_REG     0x00C8
0147 
0148 /* TOE GMAC 0/1 register */
0149 #define GMAC_STA_ADD0           0x0000
0150 #define GMAC_STA_ADD1           0x0004
0151 #define GMAC_STA_ADD2           0x0008
0152 #define GMAC_RX_FLTR            0x000c
0153 #define GMAC_MCAST_FIL0         0x0010
0154 #define GMAC_MCAST_FIL1         0x0014
0155 #define GMAC_CONFIG0            0x0018
0156 #define GMAC_CONFIG1            0x001c
0157 #define GMAC_CONFIG2            0x0020
0158 #define GMAC_CONFIG3            0x0024
0159 #define GMAC_RESERVED           0x0028
0160 #define GMAC_STATUS         0x002c
0161 #define GMAC_IN_DISCARDS        0x0030
0162 #define GMAC_IN_ERRORS          0x0034
0163 #define GMAC_IN_MCAST           0x0038
0164 #define GMAC_IN_BCAST           0x003c
0165 #define GMAC_IN_MAC1            0x0040  /* for STA 1 MAC Address */
0166 #define GMAC_IN_MAC2            0x0044  /* for STA 2 MAC Address */
0167 
0168 #define RX_STATS_NUM    6
0169 
0170 /* DMA Queues description Ring Base Address/Size Register (offset 0x0004) */
0171 union dma_q_base_size {
0172     unsigned int bits32;
0173     unsigned int base_size;
0174 };
0175 
0176 #define DMA_Q_BASE_MASK     (~0x0f)
0177 
0178 /* DMA SKB Buffer register (offset 0x0008) */
0179 union dma_skb_size {
0180     unsigned int bits32;
0181     struct bit_0008 {
0182         unsigned int sw_skb_size : 16;  /* SW Free poll SKB Size */
0183         unsigned int hw_skb_size : 16;  /* HW Free poll SKB Size */
0184     } bits;
0185 };
0186 
0187 /* DMA SW Free Queue Read/Write Pointer Register (offset 0x000c) */
0188 union dma_rwptr {
0189     unsigned int bits32;
0190     struct bit_000c {
0191         unsigned int rptr   : 16;   /* Read Ptr, RO */
0192         unsigned int wptr   : 16;   /* Write Ptr, RW */
0193     } bits;
0194 };
0195 
0196 /* Interrupt Status Register 0  (offset 0x0020)
0197  * Interrupt Mask Register 0    (offset 0x0024)
0198  * Interrupt Select Register 0  (offset 0x0028)
0199  */
0200 #define GMAC1_TXDERR_INT_BIT        BIT(31)
0201 #define GMAC1_TXPERR_INT_BIT        BIT(30)
0202 #define GMAC0_TXDERR_INT_BIT        BIT(29)
0203 #define GMAC0_TXPERR_INT_BIT        BIT(28)
0204 #define GMAC1_RXDERR_INT_BIT        BIT(27)
0205 #define GMAC1_RXPERR_INT_BIT        BIT(26)
0206 #define GMAC0_RXDERR_INT_BIT        BIT(25)
0207 #define GMAC0_RXPERR_INT_BIT        BIT(24)
0208 #define GMAC1_SWTQ15_FIN_INT_BIT    BIT(23)
0209 #define GMAC1_SWTQ14_FIN_INT_BIT    BIT(22)
0210 #define GMAC1_SWTQ13_FIN_INT_BIT    BIT(21)
0211 #define GMAC1_SWTQ12_FIN_INT_BIT    BIT(20)
0212 #define GMAC1_SWTQ11_FIN_INT_BIT    BIT(19)
0213 #define GMAC1_SWTQ10_FIN_INT_BIT    BIT(18)
0214 #define GMAC0_SWTQ05_FIN_INT_BIT    BIT(17)
0215 #define GMAC0_SWTQ04_FIN_INT_BIT    BIT(16)
0216 #define GMAC0_SWTQ03_FIN_INT_BIT    BIT(15)
0217 #define GMAC0_SWTQ02_FIN_INT_BIT    BIT(14)
0218 #define GMAC0_SWTQ01_FIN_INT_BIT    BIT(13)
0219 #define GMAC0_SWTQ00_FIN_INT_BIT    BIT(12)
0220 #define GMAC1_SWTQ15_EOF_INT_BIT    BIT(11)
0221 #define GMAC1_SWTQ14_EOF_INT_BIT    BIT(10)
0222 #define GMAC1_SWTQ13_EOF_INT_BIT    BIT(9)
0223 #define GMAC1_SWTQ12_EOF_INT_BIT    BIT(8)
0224 #define GMAC1_SWTQ11_EOF_INT_BIT    BIT(7)
0225 #define GMAC1_SWTQ10_EOF_INT_BIT    BIT(6)
0226 #define GMAC0_SWTQ05_EOF_INT_BIT    BIT(5)
0227 #define GMAC0_SWTQ04_EOF_INT_BIT    BIT(4)
0228 #define GMAC0_SWTQ03_EOF_INT_BIT    BIT(3)
0229 #define GMAC0_SWTQ02_EOF_INT_BIT    BIT(2)
0230 #define GMAC0_SWTQ01_EOF_INT_BIT    BIT(1)
0231 #define GMAC0_SWTQ00_EOF_INT_BIT    BIT(0)
0232 
0233 /* Interrupt Status Register 1  (offset 0x0030)
0234  * Interrupt Mask Register 1    (offset 0x0034)
0235  * Interrupt Select Register 1  (offset 0x0038)
0236  */
0237 #define TOE_IQ3_FULL_INT_BIT        BIT(31)
0238 #define TOE_IQ2_FULL_INT_BIT        BIT(30)
0239 #define TOE_IQ1_FULL_INT_BIT        BIT(29)
0240 #define TOE_IQ0_FULL_INT_BIT        BIT(28)
0241 #define TOE_IQ3_INT_BIT         BIT(27)
0242 #define TOE_IQ2_INT_BIT         BIT(26)
0243 #define TOE_IQ1_INT_BIT         BIT(25)
0244 #define TOE_IQ0_INT_BIT         BIT(24)
0245 #define GMAC1_HWTQ13_EOF_INT_BIT    BIT(23)
0246 #define GMAC1_HWTQ12_EOF_INT_BIT    BIT(22)
0247 #define GMAC1_HWTQ11_EOF_INT_BIT    BIT(21)
0248 #define GMAC1_HWTQ10_EOF_INT_BIT    BIT(20)
0249 #define GMAC0_HWTQ03_EOF_INT_BIT    BIT(19)
0250 #define GMAC0_HWTQ02_EOF_INT_BIT    BIT(18)
0251 #define GMAC0_HWTQ01_EOF_INT_BIT    BIT(17)
0252 #define GMAC0_HWTQ00_EOF_INT_BIT    BIT(16)
0253 #define CLASS_RX_INT_BIT(x)     BIT((x + 2))
0254 #define DEFAULT_Q1_INT_BIT      BIT(1)
0255 #define DEFAULT_Q0_INT_BIT      BIT(0)
0256 
0257 #define TOE_IQ_INT_BITS     (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
0258                  TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
0259 #define TOE_IQ_FULL_BITS    (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
0260                  TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
0261 #define TOE_IQ_ALL_BITS     (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
0262 #define TOE_CLASS_RX_INT_BITS   0xfffc
0263 
0264 /* Interrupt Status Register 2  (offset 0x0040)
0265  * Interrupt Mask Register 2    (offset 0x0044)
0266  * Interrupt Select Register 2  (offset 0x0048)
0267  */
0268 #define TOE_QL_FULL_INT_BIT(x)      BIT(x)
0269 
0270 /* Interrupt Status Register 3  (offset 0x0050)
0271  * Interrupt Mask Register 3    (offset 0x0054)
0272  * Interrupt Select Register 3  (offset 0x0058)
0273  */
0274 #define TOE_QH_FULL_INT_BIT(x)      BIT(x - 32)
0275 
0276 /* Interrupt Status Register 4  (offset 0x0060)
0277  * Interrupt Mask Register 4    (offset 0x0064)
0278  * Interrupt Select Register 4  (offset 0x0068)
0279  */
0280 #define GMAC1_RESERVED_INT_BIT      BIT(31)
0281 #define GMAC1_MIB_INT_BIT       BIT(30)
0282 #define GMAC1_RX_PAUSE_ON_INT_BIT   BIT(29)
0283 #define GMAC1_TX_PAUSE_ON_INT_BIT   BIT(28)
0284 #define GMAC1_RX_PAUSE_OFF_INT_BIT  BIT(27)
0285 #define GMAC1_TX_PAUSE_OFF_INT_BIT  BIT(26)
0286 #define GMAC1_RX_OVERRUN_INT_BIT    BIT(25)
0287 #define GMAC1_STATUS_CHANGE_INT_BIT BIT(24)
0288 #define GMAC0_RESERVED_INT_BIT      BIT(23)
0289 #define GMAC0_MIB_INT_BIT       BIT(22)
0290 #define GMAC0_RX_PAUSE_ON_INT_BIT   BIT(21)
0291 #define GMAC0_TX_PAUSE_ON_INT_BIT   BIT(20)
0292 #define GMAC0_RX_PAUSE_OFF_INT_BIT  BIT(19)
0293 #define GMAC0_TX_PAUSE_OFF_INT_BIT  BIT(18)
0294 #define GMAC0_RX_OVERRUN_INT_BIT    BIT(17)
0295 #define GMAC0_STATUS_CHANGE_INT_BIT BIT(16)
0296 #define CLASS_RX_FULL_INT_BIT(x)    BIT(x + 2)
0297 #define HWFQ_EMPTY_INT_BIT      BIT(1)
0298 #define SWFQ_EMPTY_INT_BIT      BIT(0)
0299 
0300 #define GMAC0_INT_BITS  (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
0301              GMAC0_RX_PAUSE_ON_INT_BIT | \
0302              GMAC0_TX_PAUSE_ON_INT_BIT | \
0303              GMAC0_RX_PAUSE_OFF_INT_BIT | \
0304              GMAC0_TX_PAUSE_OFF_INT_BIT | \
0305              GMAC0_RX_OVERRUN_INT_BIT | \
0306              GMAC0_STATUS_CHANGE_INT_BIT)
0307 #define GMAC1_INT_BITS  (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
0308              GMAC1_RX_PAUSE_ON_INT_BIT | \
0309              GMAC1_TX_PAUSE_ON_INT_BIT | \
0310              GMAC1_RX_PAUSE_OFF_INT_BIT | \
0311              GMAC1_TX_PAUSE_OFF_INT_BIT | \
0312              GMAC1_RX_OVERRUN_INT_BIT | \
0313              GMAC1_STATUS_CHANGE_INT_BIT)
0314 
0315 #define CLASS_RX_FULL_INT_BITS      0xfffc
0316 
0317 /* GLOBAL_QUEUE_THRESHOLD_REG   (offset 0x0070) */
0318 union queue_threshold {
0319     unsigned int bits32;
0320     struct bit_0070_2 {
0321         /*  7:0 Software Free Queue Empty Threshold */
0322         unsigned int swfq_empty:8;
0323         /* 15:8 Hardware Free Queue Empty Threshold */
0324         unsigned int hwfq_empty:8;
0325         /* 23:16 */
0326         unsigned int intrq:8;
0327         /* 31:24 */
0328         unsigned int toe_class:8;
0329     } bits;
0330 };
0331 
0332 /* GMAC DMA Control Register
0333  * GMAC0 offset 0x8000
0334  * GMAC1 offset 0xC000
0335  */
0336 union gmac_dma_ctrl {
0337     unsigned int bits32;
0338     struct bit_8000 {
0339         /* bit 1:0 Peripheral Bus Width */
0340         unsigned int td_bus:2;
0341         /* bit 3:2 TxDMA max burst size for every AHB request */
0342         unsigned int td_burst_size:2;
0343         /* bit 7:4 TxDMA protection control */
0344         unsigned int td_prot:4;
0345         /* bit 9:8 Peripheral Bus Width */
0346         unsigned int rd_bus:2;
0347         /* bit 11:10 DMA max burst size for every AHB request */
0348         unsigned int rd_burst_size:2;
0349         /* bit 15:12 DMA Protection Control */
0350         unsigned int rd_prot:4;
0351         /* bit 17:16 */
0352         unsigned int rd_insert_bytes:2;
0353         /* bit 27:18 */
0354         unsigned int reserved:10;
0355         /* bit 28 1: Drop, 0: Accept */
0356         unsigned int drop_small_ack:1;
0357         /* bit 29 Loopback TxDMA to RxDMA */
0358         unsigned int loopback:1;
0359         /* bit 30 Tx DMA Enable */
0360         unsigned int td_enable:1;
0361         /* bit 31 Rx DMA Enable */
0362         unsigned int rd_enable:1;
0363     } bits;
0364 };
0365 
0366 /* GMAC Tx Weighting Control Register 0
0367  * GMAC0 offset 0x8004
0368  * GMAC1 offset 0xC004
0369  */
0370 union gmac_tx_wcr0 {
0371     unsigned int bits32;
0372     struct bit_8004 {
0373         /* bit 5:0 HW TX Queue 3 */
0374         unsigned int hw_tq0:6;
0375         /* bit 11:6 HW TX Queue 2 */
0376         unsigned int hw_tq1:6;
0377         /* bit 17:12 HW TX Queue 1 */
0378         unsigned int hw_tq2:6;
0379         /* bit 23:18 HW TX Queue 0 */
0380         unsigned int hw_tq3:6;
0381         /* bit 31:24 */
0382         unsigned int reserved:8;
0383     } bits;
0384 };
0385 
0386 /* GMAC Tx Weighting Control Register 1
0387  * GMAC0 offset 0x8008
0388  * GMAC1 offset 0xC008
0389  */
0390 union gmac_tx_wcr1 {
0391     unsigned int bits32;
0392     struct bit_8008 {
0393         /* bit 4:0 SW TX Queue 0 */
0394         unsigned int sw_tq0:5;
0395         /* bit 9:5 SW TX Queue 1 */
0396         unsigned int sw_tq1:5;
0397         /* bit 14:10 SW TX Queue 2 */
0398         unsigned int sw_tq2:5;
0399         /* bit 19:15 SW TX Queue 3 */
0400         unsigned int sw_tq3:5;
0401         /* bit 24:20 SW TX Queue 4 */
0402         unsigned int sw_tq4:5;
0403         /* bit 29:25 SW TX Queue 5 */
0404         unsigned int sw_tq5:5;
0405         /* bit 31:30 */
0406         unsigned int reserved:2;
0407     } bits;
0408 };
0409 
0410 /* GMAC DMA Tx Description Word 0 Register
0411  * GMAC0 offset 0x8040
0412  * GMAC1 offset 0xC040
0413  */
0414 union gmac_txdesc_0 {
0415     unsigned int bits32;
0416     struct bit_8040 {
0417         /* bit 15:0 Transfer size */
0418         unsigned int buffer_size:16;
0419         /* bit 21:16 number of descriptors used for the current frame */
0420         unsigned int desc_count:6;
0421         /* bit 22 Tx Status, 1: Successful 0: Failed */
0422         unsigned int status_tx_ok:1;
0423         /* bit 28:23 Tx Status, Reserved bits */
0424         unsigned int status_rvd:6;
0425         /* bit 29 protocol error during processing this descriptor */
0426         unsigned int perr:1;
0427         /* bit 30 data error during processing this descriptor */
0428         unsigned int derr:1;
0429         /* bit 31 */
0430         unsigned int reserved:1;
0431     } bits;
0432 };
0433 
0434 /* GMAC DMA Tx Description Word 1 Register
0435  * GMAC0 offset 0x8044
0436  * GMAC1 offset 0xC044
0437  */
0438 union gmac_txdesc_1 {
0439     unsigned int bits32;
0440     struct txdesc_word1 {
0441         /* bit 15: 0 Tx Frame Byte Count */
0442         unsigned int byte_count:16;
0443         /* bit 16 TSS segmentation use MTU setting */
0444         unsigned int mtu_enable:1;
0445         /* bit 17 IPV4 Header Checksum Enable */
0446         unsigned int ip_chksum:1;
0447         /* bit 18 IPV6 Tx Enable */
0448         unsigned int ipv6_enable:1;
0449         /* bit 19 TCP Checksum Enable */
0450         unsigned int tcp_chksum:1;
0451         /* bit 20 UDP Checksum Enable */
0452         unsigned int udp_chksum:1;
0453         /* bit 21 Bypass HW offload engine */
0454         unsigned int bypass_tss:1;
0455         /* bit 22 Don't update IP length field */
0456         unsigned int ip_fixed_len:1;
0457         /* bit 31:23 Tx Flag, Reserved */
0458         unsigned int reserved:9;
0459     } bits;
0460 };
0461 
0462 #define TSS_IP_FIXED_LEN_BIT    BIT(22)
0463 #define TSS_BYPASS_BIT      BIT(21)
0464 #define TSS_UDP_CHKSUM_BIT  BIT(20)
0465 #define TSS_TCP_CHKSUM_BIT  BIT(19)
0466 #define TSS_IPV6_ENABLE_BIT BIT(18)
0467 #define TSS_IP_CHKSUM_BIT   BIT(17)
0468 #define TSS_MTU_ENABLE_BIT  BIT(16)
0469 
0470 #define TSS_CHECKUM_ENABLE  \
0471     (TSS_IP_CHKSUM_BIT | TSS_IPV6_ENABLE_BIT | \
0472      TSS_TCP_CHKSUM_BIT | TSS_UDP_CHKSUM_BIT)
0473 
0474 /* GMAC DMA Tx Description Word 2 Register
0475  * GMAC0 offset 0x8048
0476  * GMAC1 offset 0xC048
0477  */
0478 union gmac_txdesc_2 {
0479     unsigned int    bits32;
0480     unsigned int    buf_adr;
0481 };
0482 
0483 /* GMAC DMA Tx Description Word 3 Register
0484  * GMAC0 offset 0x804C
0485  * GMAC1 offset 0xC04C
0486  */
0487 union gmac_txdesc_3 {
0488     unsigned int bits32;
0489     struct txdesc_word3 {
0490         /* bit 12: 0 Tx Frame Byte Count */
0491         unsigned int mtu_size:13;
0492         /* bit 28:13 */
0493         unsigned int reserved:16;
0494         /* bit 29 End of frame interrupt enable */
0495         unsigned int eofie:1;
0496         /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
0497         unsigned int sof_eof:2;
0498     } bits;
0499 };
0500 
0501 #define SOF_EOF_BIT_MASK    0x3fffffff
0502 #define SOF_BIT         0x80000000
0503 #define EOF_BIT         0x40000000
0504 #define EOFIE_BIT       BIT(29)
0505 #define MTU_SIZE_BIT_MASK   0x1fff
0506 
0507 /* GMAC Tx Descriptor */
0508 struct gmac_txdesc {
0509     union gmac_txdesc_0 word0;
0510     union gmac_txdesc_1 word1;
0511     union gmac_txdesc_2 word2;
0512     union gmac_txdesc_3 word3;
0513 };
0514 
0515 /* GMAC DMA Rx Description Word 0 Register
0516  * GMAC0 offset 0x8060
0517  * GMAC1 offset 0xC060
0518  */
0519 union gmac_rxdesc_0 {
0520     unsigned int bits32;
0521     struct bit_8060 {
0522         /* bit 15:0 number of descriptors used for the current frame */
0523         unsigned int buffer_size:16;
0524         /* bit 21:16 number of descriptors used for the current frame */
0525         unsigned int desc_count:6;
0526         /* bit 24:22 Status of rx frame */
0527         unsigned int status:4;
0528         /* bit 28:26 Check Sum Status */
0529         unsigned int chksum_status:3;
0530         /* bit 29 protocol error during processing this descriptor */
0531         unsigned int perr:1;
0532         /* bit 30 data error during processing this descriptor */
0533         unsigned int derr:1;
0534         /* bit 31 TOE/CIS Queue Full dropped packet to default queue */
0535         unsigned int drop:1;
0536     } bits;
0537 };
0538 
0539 #define GMAC_RXDESC_0_T_derr            BIT(30)
0540 #define GMAC_RXDESC_0_T_perr            BIT(29)
0541 #define GMAC_RXDESC_0_T_chksum_status(x)    BIT(x + 26)
0542 #define GMAC_RXDESC_0_T_status(x)       BIT(x + 22)
0543 #define GMAC_RXDESC_0_T_desc_count(x)       BIT(x + 16)
0544 
0545 #define RX_CHKSUM_IP_UDP_TCP_OK         0
0546 #define RX_CHKSUM_IP_OK_ONLY            1
0547 #define RX_CHKSUM_NONE              2
0548 #define RX_CHKSUM_IP_ERR_UNKNOWN        4
0549 #define RX_CHKSUM_IP_ERR            5
0550 #define RX_CHKSUM_TCP_UDP_ERR           6
0551 #define RX_CHKSUM_NUM               8
0552 
0553 #define RX_STATUS_GOOD_FRAME            0
0554 #define RX_STATUS_TOO_LONG_GOOD_CRC     1
0555 #define RX_STATUS_RUNT_FRAME            2
0556 #define RX_STATUS_SFD_NOT_FOUND         3
0557 #define RX_STATUS_CRC_ERROR         4
0558 #define RX_STATUS_TOO_LONG_BAD_CRC      5
0559 #define RX_STATUS_ALIGNMENT_ERROR       6
0560 #define RX_STATUS_TOO_LONG_BAD_ALIGN        7
0561 #define RX_STATUS_RX_ERR            8
0562 #define RX_STATUS_DA_FILTERED           9
0563 #define RX_STATUS_BUFFER_FULL           10
0564 #define RX_STATUS_NUM               16
0565 
0566 #define RX_ERROR_LENGTH(s) \
0567     ((s) == RX_STATUS_TOO_LONG_GOOD_CRC || \
0568      (s) == RX_STATUS_TOO_LONG_BAD_CRC || \
0569      (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
0570 #define RX_ERROR_OVER(s) \
0571     ((s) == RX_STATUS_BUFFER_FULL)
0572 #define RX_ERROR_CRC(s) \
0573     ((s) == RX_STATUS_CRC_ERROR || \
0574      (s) == RX_STATUS_TOO_LONG_BAD_CRC)
0575 #define RX_ERROR_FRAME(s) \
0576     ((s) == RX_STATUS_ALIGNMENT_ERROR || \
0577      (s) == RX_STATUS_TOO_LONG_BAD_ALIGN)
0578 #define RX_ERROR_FIFO(s) \
0579     (0)
0580 
0581 /* GMAC DMA Rx Description Word 1 Register
0582  * GMAC0 offset 0x8064
0583  * GMAC1 offset 0xC064
0584  */
0585 union gmac_rxdesc_1 {
0586     unsigned int bits32;
0587     struct rxdesc_word1 {
0588         /* bit 15: 0 Rx Frame Byte Count */
0589         unsigned int byte_count:16;
0590         /* bit 31:16 Software ID */
0591         unsigned int sw_id:16;
0592     } bits;
0593 };
0594 
0595 /* GMAC DMA Rx Description Word 2 Register
0596  * GMAC0 offset 0x8068
0597  * GMAC1 offset 0xC068
0598  */
0599 union gmac_rxdesc_2 {
0600     unsigned int    bits32;
0601     unsigned int    buf_adr;
0602 };
0603 
0604 #define RX_INSERT_NONE      0
0605 #define RX_INSERT_1_BYTE    1
0606 #define RX_INSERT_2_BYTE    2
0607 #define RX_INSERT_3_BYTE    3
0608 
0609 /* GMAC DMA Rx Description Word 3 Register
0610  * GMAC0 offset 0x806C
0611  * GMAC1 offset 0xC06C
0612  */
0613 union gmac_rxdesc_3 {
0614     unsigned int bits32;
0615     struct rxdesc_word3 {
0616         /* bit 7: 0 L3 data offset */
0617         unsigned int l3_offset:8;
0618         /* bit 15: 8 L4 data offset */
0619         unsigned int l4_offset:8;
0620         /* bit 23: 16 L7 data offset */
0621         unsigned int l7_offset:8;
0622         /* bit 24 Duplicated ACK detected */
0623         unsigned int dup_ack:1;
0624         /* bit 25 abnormal case found */
0625         unsigned int abnormal:1;
0626         /* bit 26 IPV4 option or IPV6 extension header */
0627         unsigned int option:1;
0628         /* bit 27 Out of Sequence packet */
0629         unsigned int out_of_seq:1;
0630         /* bit 28 Control Flag is present */
0631         unsigned int ctrl_flag:1;
0632         /* bit 29 End of frame interrupt enable */
0633         unsigned int eofie:1;
0634         /* bit 31:30 11: only one, 10: first, 01: last, 00: linking */
0635         unsigned int sof_eof:2;
0636     } bits;
0637 };
0638 
0639 /* GMAC Rx Descriptor, this is simply fitted over the queue registers */
0640 struct gmac_rxdesc {
0641     union gmac_rxdesc_0 word0;
0642     union gmac_rxdesc_1 word1;
0643     union gmac_rxdesc_2 word2;
0644     union gmac_rxdesc_3 word3;
0645 };
0646 
0647 /* GMAC Matching Rule Control Register 0
0648  * GMAC0 offset 0x8078
0649  * GMAC1 offset 0xC078
0650  */
0651 #define MR_L2_BIT       BIT(31)
0652 #define MR_L3_BIT       BIT(30)
0653 #define MR_L4_BIT       BIT(29)
0654 #define MR_L7_BIT       BIT(28)
0655 #define MR_PORT_BIT     BIT(27)
0656 #define MR_PRIORITY_BIT     BIT(26)
0657 #define MR_DA_BIT       BIT(23)
0658 #define MR_SA_BIT       BIT(22)
0659 #define MR_ETHER_TYPE_BIT   BIT(21)
0660 #define MR_VLAN_BIT     BIT(20)
0661 #define MR_PPPOE_BIT        BIT(19)
0662 #define MR_IP_VER_BIT       BIT(15)
0663 #define MR_IP_HDR_LEN_BIT   BIT(14)
0664 #define MR_FLOW_LABLE_BIT   BIT(13)
0665 #define MR_TOS_TRAFFIC_BIT  BIT(12)
0666 #define MR_SPR_BIT(x)       BIT(x)
0667 #define MR_SPR_BITS     0xff
0668 
0669 /* GMAC_AHB_WEIGHT registers
0670  * GMAC0 offset 0x80C8
0671  * GMAC1 offset 0xC0C8
0672  */
0673 union gmac_ahb_weight {
0674     unsigned int bits32;
0675     struct bit_80C8 {
0676         /* 4:0 */
0677         unsigned int hash_weight:5;
0678         /* 9:5 */
0679         unsigned int rx_weight:5;
0680         /* 14:10 */
0681         unsigned int tx_weight:5;
0682         /* 19:15 Rx Data Pre Request FIFO Threshold */
0683         unsigned int pre_req:5;
0684         /* 24:20 DMA TqCtrl to Start tqDV FIFO Threshold */
0685         unsigned int tq_dv_threshold:5;
0686         /* 31:25 */
0687         unsigned int reserved:7;
0688     } bits;
0689 };
0690 
0691 /* GMAC RX FLTR
0692  * GMAC0 Offset 0xA00C
0693  * GMAC1 Offset 0xE00C
0694  */
0695 union gmac_rx_fltr {
0696     unsigned int bits32;
0697     struct bit1_000c {
0698         /* Enable receive of unicast frames that are sent to STA
0699          * address
0700          */
0701         unsigned int unicast:1;
0702         /* Enable receive of multicast frames that pass multicast
0703          * filter
0704          */
0705         unsigned int multicast:1;
0706         /* Enable receive of broadcast frames */
0707         unsigned int broadcast:1;
0708         /* Enable receive of all frames */
0709         unsigned int promiscuous:1;
0710         /* Enable receive of all error frames */
0711         unsigned int error:1;
0712         unsigned int reserved:27;
0713     } bits;
0714 };
0715 
0716 /* GMAC Configuration 0
0717  * GMAC0 Offset 0xA018
0718  * GMAC1 Offset 0xE018
0719  */
0720 union gmac_config0 {
0721     unsigned int bits32;
0722     struct bit1_0018 {
0723         /* 0: disable transmit */
0724         unsigned int dis_tx:1;
0725         /* 1: disable receive */
0726         unsigned int dis_rx:1;
0727         /* 2: transmit data loopback enable */
0728         unsigned int loop_back:1;
0729         /* 3: flow control also trigged by Rx queues */
0730         unsigned int flow_ctrl:1;
0731         /* 4-7: adjust IFG from 96+/-56 */
0732         unsigned int adj_ifg:4;
0733         /* 8-10 maximum receive frame length allowed */
0734         unsigned int max_len:3;
0735         /* 11: disable back-off function */
0736         unsigned int dis_bkoff:1;
0737         /* 12: disable 16 collisions abort function */
0738         unsigned int dis_col:1;
0739         /* 13: speed up timers in simulation */
0740         unsigned int sim_test:1;
0741         /* 14: RX flow control enable */
0742         unsigned int rx_fc_en:1;
0743         /* 15: TX flow control enable */
0744         unsigned int tx_fc_en:1;
0745         /* 16: RGMII in-band status enable */
0746         unsigned int rgmii_en:1;
0747         /* 17: IPv4 RX Checksum enable */
0748         unsigned int ipv4_rx_chksum:1;
0749         /* 18: IPv6 RX Checksum enable */
0750         unsigned int ipv6_rx_chksum:1;
0751         /* 19: Remove Rx VLAN tag */
0752         unsigned int rx_tag_remove:1;
0753         /* 20 */
0754         unsigned int rgmm_edge:1;
0755         /* 21 */
0756         unsigned int rxc_inv:1;
0757         /* 22 */
0758         unsigned int ipv6_exthdr_order:1;
0759         /* 23 */
0760         unsigned int rx_err_detect:1;
0761         /* 24 */
0762         unsigned int port0_chk_hwq:1;
0763         /* 25 */
0764         unsigned int port1_chk_hwq:1;
0765         /* 26 */
0766         unsigned int port0_chk_toeq:1;
0767         /* 27 */
0768         unsigned int port1_chk_toeq:1;
0769         /* 28 */
0770         unsigned int port0_chk_classq:1;
0771         /* 29 */
0772         unsigned int port1_chk_classq:1;
0773         /* 30, 31 */
0774         unsigned int reserved:2;
0775     } bits;
0776 };
0777 
0778 #define CONFIG0_TX_RX_DISABLE   (BIT(1) | BIT(0))
0779 #define CONFIG0_RX_CHKSUM   (BIT(18) | BIT(17))
0780 #define CONFIG0_FLOW_RX     BIT(14)
0781 #define CONFIG0_FLOW_TX     BIT(15)
0782 #define CONFIG0_FLOW_TX_RX  (BIT(14) | BIT(15))
0783 #define CONFIG0_FLOW_CTL    (BIT(14) | BIT(15))
0784 
0785 #define CONFIG0_MAXLEN_SHIFT    8
0786 #define CONFIG0_MAXLEN_MASK (7 << CONFIG0_MAXLEN_SHIFT)
0787 #define  CONFIG0_MAXLEN_1536    0
0788 #define  CONFIG0_MAXLEN_1518    1
0789 #define  CONFIG0_MAXLEN_1522    2
0790 #define  CONFIG0_MAXLEN_1542    3
0791 #define  CONFIG0_MAXLEN_9k  4   /* 9212 */
0792 #define  CONFIG0_MAXLEN_10k 5   /* 10236 */
0793 #define  CONFIG0_MAXLEN_1518__6 6
0794 #define  CONFIG0_MAXLEN_1518__7 7
0795 
0796 /* GMAC Configuration 1
0797  * GMAC0 Offset 0xA01C
0798  * GMAC1 Offset 0xE01C
0799  */
0800 union gmac_config1 {
0801     unsigned int bits32;
0802     struct bit1_001c {
0803         /* Flow control set threshold */
0804         unsigned int set_threshold:8;
0805         /* Flow control release threshold */
0806         unsigned int rel_threshold:8;
0807         unsigned int reserved:16;
0808     } bits;
0809 };
0810 
0811 #define GMAC_FLOWCTRL_SET_MAX       32
0812 #define GMAC_FLOWCTRL_SET_MIN       0
0813 #define GMAC_FLOWCTRL_RELEASE_MAX   32
0814 #define GMAC_FLOWCTRL_RELEASE_MIN   0
0815 
0816 /* GMAC Configuration 2
0817  * GMAC0 Offset 0xA020
0818  * GMAC1 Offset 0xE020
0819  */
0820 union gmac_config2 {
0821     unsigned int bits32;
0822     struct bit1_0020 {
0823         /* Flow control set threshold */
0824         unsigned int set_threshold:16;
0825         /* Flow control release threshold */
0826         unsigned int rel_threshold:16;
0827     } bits;
0828 };
0829 
0830 /* GMAC Configuration 3
0831  * GMAC0 Offset 0xA024
0832  * GMAC1 Offset 0xE024
0833  */
0834 union gmac_config3 {
0835     unsigned int bits32;
0836     struct bit1_0024 {
0837         /* Flow control set threshold */
0838         unsigned int set_threshold:16;
0839         /* Flow control release threshold */
0840         unsigned int rel_threshold:16;
0841     } bits;
0842 };
0843 
0844 /* GMAC STATUS
0845  * GMAC0 Offset 0xA02C
0846  * GMAC1 Offset 0xE02C
0847  */
0848 union gmac_status {
0849     unsigned int bits32;
0850     struct bit1_002c {
0851         /* Link status */
0852         unsigned int link:1;
0853         /* Link speed(00->2.5M 01->25M 10->125M) */
0854         unsigned int speed:2;
0855         /* Duplex mode */
0856         unsigned int duplex:1;
0857         unsigned int reserved_1:1;
0858         /* PHY interface type */
0859         unsigned int mii_rmii:2;
0860         unsigned int reserved_2:25;
0861     } bits;
0862 };
0863 
0864 #define GMAC_SPEED_10           0
0865 #define GMAC_SPEED_100          1
0866 #define GMAC_SPEED_1000         2
0867 
0868 #define GMAC_PHY_MII            0
0869 #define GMAC_PHY_GMII           1
0870 #define GMAC_PHY_RGMII_100_10       2
0871 #define GMAC_PHY_RGMII_1000     3
0872 
0873 /* Queue Header
0874  *  (1) TOE Queue Header
0875  *  (2) Non-TOE Queue Header
0876  *  (3) Interrupt Queue Header
0877  *
0878  * memory Layout
0879  *  TOE Queue Header
0880  *           0x60003000 +---------------------------+ 0x0000
0881  *              |     TOE Queue 0 Header    |
0882  *              |         8 * 4 Bytes       |
0883  *              +---------------------------+ 0x0020
0884  *              |     TOE Queue 1 Header    |
0885  *              |         8 * 4 Bytes       |
0886  *              +---------------------------+ 0x0040
0887  *              |          ......           |
0888  *              |                           |
0889  *              +---------------------------+
0890  *
0891  *  Non TOE Queue Header
0892  *           0x60002000 +---------------------------+ 0x0000
0893  *              |   Default Queue 0 Header  |
0894  *              |         2 * 4 Bytes       |
0895  *              +---------------------------+ 0x0008
0896  *              |   Default Queue 1 Header  |
0897  *              |         2 * 4 Bytes       |
0898  *              +---------------------------+ 0x0010
0899  *              |   Classification Queue 0  |
0900  *              |     2 * 4 Bytes       |
0901  *              +---------------------------+
0902  *              |   Classification Queue 1  |
0903  *              |     2 * 4 Bytes       |
0904  *              +---------------------------+ (n * 8 + 0x10)
0905  *              |       ...     |
0906  *              |     2 * 4 Bytes       |
0907  *              +---------------------------+ (13 * 8 + 0x10)
0908  *              |   Classification Queue 13 |
0909  *              |     2 * 4 Bytes       |
0910  *              +---------------------------+ 0x80
0911  *              |      Interrupt Queue 0    |
0912  *              |     2 * 4 Bytes       |
0913  *              +---------------------------+
0914  *              |      Interrupt Queue 1    |
0915  *              |     2 * 4 Bytes       |
0916  *              +---------------------------+
0917  *              |      Interrupt Queue 2    |
0918  *              |     2 * 4 Bytes       |
0919  *              +---------------------------+
0920  *              |      Interrupt Queue 3    |
0921  *              |     2 * 4 Bytes       |
0922  *              +---------------------------+
0923  *
0924  */
0925 #define TOE_QUEUE_HDR_ADDR(n)   (TOE_TOE_QUE_HDR_BASE + n * 32)
0926 #define TOE_Q_HDR_AREA_END  (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX + 1))
0927 #define TOE_DEFAULT_Q_HDR_BASE(x) (TOE_NONTOE_QUE_HDR_BASE + 0x08 * (x))
0928 #define TOE_CLASS_Q_HDR_BASE    (TOE_NONTOE_QUE_HDR_BASE + 0x10)
0929 #define TOE_INTR_Q_HDR_BASE (TOE_NONTOE_QUE_HDR_BASE + 0x80)
0930 #define INTERRUPT_QUEUE_HDR_ADDR(n) (TOE_INTR_Q_HDR_BASE + n * 8)
0931 #define NONTOE_Q_HDR_AREA_END (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX + 1))
0932 
0933 /* NONTOE Queue Header Word 0 */
0934 union nontoe_qhdr0 {
0935     unsigned int bits32;
0936     unsigned int base_size;
0937 };
0938 
0939 #define NONTOE_QHDR0_BASE_MASK  (~0x0f)
0940 
0941 /* NONTOE Queue Header Word 1 */
0942 union nontoe_qhdr1 {
0943     unsigned int bits32;
0944     struct bit_nonqhdr1 {
0945         /* bit 15:0 */
0946         unsigned int rptr:16;
0947         /* bit 31:16 */
0948         unsigned int wptr:16;
0949     } bits;
0950 };
0951 
0952 /* Non-TOE Queue Header */
0953 struct nontoe_qhdr {
0954     union nontoe_qhdr0 word0;
0955     union nontoe_qhdr1 word1;
0956 };
0957 
0958 #endif /* _GEMINI_ETHERNET_H */
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