cisco/enic/vnic_wq.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.
0004  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
0005  */
0006
0007 #ifndef _VNIC_WQ_H_
0008 #define _VNIC_WQ_H_
0009
0010 #include <linux/pci.h>
0011
0012 #include "vnic_dev.h"
0013 #include "vnic_cq.h"
0014
0015 /* Work queue control */
0016 struct vnic_wq_ctrl {
0017     u64 ring_base;          /* 0x00 */
0018     u32 ring_size;          /* 0x08 */
0019     u32 pad0;
0020     u32 posted_index;       /* 0x10 */
0021     u32 pad1;
0022     u32 cq_index;           /* 0x18 */
0023     u32 pad2;
0024     u32 enable;         /* 0x20 */
0025     u32 pad3;
0026     u32 running;            /* 0x28 */
0027     u32 pad4;
0028     u32 fetch_index;        /* 0x30 */
0029     u32 pad5;
0030     u32 dca_value;          /* 0x38 */
0031     u32 pad6;
0032     u32 error_interrupt_enable; /* 0x40 */
0033     u32 pad7;
0034     u32 error_interrupt_offset; /* 0x48 */
0035     u32 pad8;
0036     u32 error_status;       /* 0x50 */
0037     u32 pad9;
0038 };
0039
0040 struct vnic_wq_buf {
0041     struct vnic_wq_buf *next;
0042     dma_addr_t dma_addr;
0043     void *os_buf;
0044     unsigned int len;
0045     unsigned int index;
0046     int sop;
0047     void *desc;
0048     uint64_t wr_id; /* Cookie */
0049     uint8_t cq_entry; /* Gets completion event from hw */
0050     uint8_t desc_skip_cnt; /* Num descs to occupy */
0051     uint8_t compressed_send; /* Both hdr and payload in one desc */
0052     struct vnic_wq_buf *prev;
0053 };
0054
0055 /* Break the vnic_wq_buf allocations into blocks of 32/64 entries */
0056 #define VNIC_WQ_BUF_MIN_BLK_ENTRIES 32
0057 #define VNIC_WQ_BUF_DFLT_BLK_ENTRIES 64
0058 #define VNIC_WQ_BUF_BLK_ENTRIES(entries) \
0059     ((unsigned int)((entries < VNIC_WQ_BUF_DFLT_BLK_ENTRIES) ? \
0060     VNIC_WQ_BUF_MIN_BLK_ENTRIES : VNIC_WQ_BUF_DFLT_BLK_ENTRIES))
0061 #define VNIC_WQ_BUF_BLK_SZ(entries) \
0062     (VNIC_WQ_BUF_BLK_ENTRIES(entries) * sizeof(struct vnic_wq_buf))
0063 #define VNIC_WQ_BUF_BLKS_NEEDED(entries) \
0064     DIV_ROUND_UP(entries, VNIC_WQ_BUF_BLK_ENTRIES(entries))
0065 #define VNIC_WQ_BUF_BLKS_MAX VNIC_WQ_BUF_BLKS_NEEDED(4096)
0066
0067 struct vnic_wq {
0068     unsigned int index;
0069     struct vnic_dev *vdev;
0070     struct vnic_wq_ctrl __iomem *ctrl;              /* memory-mapped */
0071     struct vnic_dev_ring ring;
0072     struct vnic_wq_buf *bufs[VNIC_WQ_BUF_BLKS_MAX];
0073     struct vnic_wq_buf *to_use;
0074     struct vnic_wq_buf *to_clean;
0075     unsigned int pkts_outstanding;
0076 };
0077
0078 struct devcmd2_controller {
0079     struct vnic_wq_ctrl __iomem *wq_ctrl;
0080     struct vnic_devcmd2 *cmd_ring;
0081     struct devcmd2_result *result;
0082     u16 next_result;
0083     u16 result_size;
0084     int color;
0085     struct vnic_dev_ring results_ring;
0086     struct vnic_wq wq;
0087     u32 posted;
0088 };
0089
0090 static inline unsigned int vnic_wq_desc_avail(struct vnic_wq *wq)
0091 {
0092     /* how many does SW own? */
0093     return wq->ring.desc_avail;
0094 }
0095
0096 static inline unsigned int vnic_wq_desc_used(struct vnic_wq *wq)
0097 {
0098     /* how many does HW own? */
0099     return wq->ring.desc_count - wq->ring.desc_avail - 1;
0100 }
0101
0102 static inline void *vnic_wq_next_desc(struct vnic_wq *wq)
0103 {
0104     return wq->to_use->desc;
0105 }
0106
0107 static inline void vnic_wq_doorbell(struct vnic_wq *wq)
0108 {
0109     /* Adding write memory barrier prevents compiler and/or CPU
0110      * reordering, thus avoiding descriptor posting before
0111      * descriptor is initialized. Otherwise, hardware can read
0112      * stale descriptor fields.
0113      */
0114     wmb();
0115     iowrite32(wq->to_use->index, &wq->ctrl->posted_index);
0116 }
0117
0118 static inline void vnic_wq_post(struct vnic_wq *wq,
0119     void *os_buf, dma_addr_t dma_addr,
0120     unsigned int len, int sop, int eop,
0121     uint8_t desc_skip_cnt, uint8_t cq_entry,
0122     uint8_t compressed_send, uint64_t wrid)
0123 {
0124     struct vnic_wq_buf *buf = wq->to_use;
0125
0126     buf->sop = sop;
0127     buf->cq_entry = cq_entry;
0128     buf->compressed_send = compressed_send;
0129     buf->desc_skip_cnt = desc_skip_cnt;
0130     buf->os_buf = eop ? os_buf : NULL;
0131     buf->dma_addr = dma_addr;
0132     buf->len = len;
0133     buf->wr_id = wrid;
0134
0135     buf = buf->next;
0136     wq->to_use = buf;
0137
0138     wq->ring.desc_avail -= desc_skip_cnt;
0139 }
0140
0141 static inline void vnic_wq_service(struct vnic_wq *wq,
0142     struct cq_desc *cq_desc, u16 completed_index,
0143     void (*buf_service)(struct vnic_wq *wq,
0144     struct cq_desc *cq_desc, struct vnic_wq_buf *buf, void *opaque),
0145     void *opaque)
0146 {
0147     struct vnic_wq_buf *buf;
0148
0149     buf = wq->to_clean;
0150     while (1) {
0151
0152         (*buf_service)(wq, cq_desc, buf, opaque);
0153
0154         wq->ring.desc_avail++;
0155
0156         wq->to_clean = buf->next;
0157
0158         if (buf->index == completed_index)
0159             break;
0160
0161         buf = wq->to_clean;
0162     }
0163 }
0164
0165 void vnic_wq_free(struct vnic_wq *wq);
0166 int vnic_wq_alloc(struct vnic_dev *vdev, struct vnic_wq *wq, unsigned int index,
0167     unsigned int desc_count, unsigned int desc_size);
0168 void vnic_wq_init(struct vnic_wq *wq, unsigned int cq_index,
0169     unsigned int error_interrupt_enable,
0170     unsigned int error_interrupt_offset);
0171 unsigned int vnic_wq_error_status(struct vnic_wq *wq);
0172 void vnic_wq_enable(struct vnic_wq *wq);
0173 int vnic_wq_disable(struct vnic_wq *wq);
0174 void vnic_wq_clean(struct vnic_wq *wq,
0175     void (*buf_clean)(struct vnic_wq *wq, struct vnic_wq_buf *buf));
0176 int enic_wq_devcmd2_alloc(struct vnic_dev *vdev, struct vnic_wq *wq,
0177               unsigned int desc_count, unsigned int desc_size);
0178 void enic_wq_init_start(struct vnic_wq *wq, unsigned int cq_index,
0179             unsigned int fetch_index, unsigned int posted_index,
0180             unsigned int error_interrupt_enable,
0181             unsigned int error_interrupt_offset);
0182
0183 #endif /* _VNIC_WQ_H_ */