cisco/enic/cq_enet_desc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright 2008-2010 Cisco Systems, Inc.  All rights reserved.
0004  * Copyright 2007 Nuova Systems, Inc.  All rights reserved.
0005  */
0006
0007 #ifndef _CQ_ENET_DESC_H_
0008 #define _CQ_ENET_DESC_H_
0009
0010 #include "cq_desc.h"
0011
0012 /* Ethernet completion queue descriptor: 16B */
0013 struct cq_enet_wq_desc {
0014     __le16 completed_index;
0015     __le16 q_number;
0016     u8 reserved[11];
0017     u8 type_color;
0018 };
0019
0020 static inline void cq_enet_wq_desc_dec(struct cq_enet_wq_desc *desc,
0021     u8 *type, u8 *color, u16 *q_number, u16 *completed_index)
0022 {
0023     cq_desc_dec((struct cq_desc *)desc, type,
0024         color, q_number, completed_index);
0025 }
0026
0027 /* Completion queue descriptor: Ethernet receive queue, 16B */
0028 struct cq_enet_rq_desc {
0029     __le16 completed_index_flags;
0030     __le16 q_number_rss_type_flags;
0031     __le32 rss_hash;
0032     __le16 bytes_written_flags;
0033     __le16 vlan;
0034     __le16 checksum_fcoe;
0035     u8 flags;
0036     u8 type_color;
0037 };
0038
0039 #define CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT          (0x1 << 12)
0040 #define CQ_ENET_RQ_DESC_FLAGS_FCOE                  (0x1 << 13)
0041 #define CQ_ENET_RQ_DESC_FLAGS_EOP                   (0x1 << 14)
0042 #define CQ_ENET_RQ_DESC_FLAGS_SOP                   (0x1 << 15)
0043
0044 #define CQ_ENET_RQ_DESC_RSS_TYPE_BITS               4
0045 #define CQ_ENET_RQ_DESC_RSS_TYPE_MASK \
0046     ((1 << CQ_ENET_RQ_DESC_RSS_TYPE_BITS) - 1)
0047 #define CQ_ENET_RQ_DESC_RSS_TYPE_NONE               0
0048 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv4               1
0049 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv4           2
0050 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6               3
0051 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6           4
0052 #define CQ_ENET_RQ_DESC_RSS_TYPE_IPv6_EX            5
0053 #define CQ_ENET_RQ_DESC_RSS_TYPE_TCP_IPv6_EX        6
0054
0055 #define CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC         (0x1 << 14)
0056
0057 #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS          14
0058 #define CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK \
0059     ((1 << CQ_ENET_RQ_DESC_BYTES_WRITTEN_BITS) - 1)
0060 #define CQ_ENET_RQ_DESC_FLAGS_TRUNCATED             (0x1 << 14)
0061 #define CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED         (0x1 << 15)
0062
0063 #define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS          12
0064 #define CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_MASK \
0065     ((1 << CQ_ENET_RQ_DESC_VLAN_TCI_VLAN_BITS) - 1)
0066 #define CQ_ENET_RQ_DESC_VLAN_TCI_CFI_MASK           (0x1 << 12)
0067 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS     3
0068 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_MASK \
0069     ((1 << CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_BITS) - 1)
0070 #define CQ_ENET_RQ_DESC_VLAN_TCI_USER_PRIO_SHIFT    13
0071
0072 #define CQ_ENET_RQ_DESC_FCOE_SOF_BITS               8
0073 #define CQ_ENET_RQ_DESC_FCOE_SOF_MASK \
0074     ((1 << CQ_ENET_RQ_DESC_FCOE_SOF_BITS) - 1)
0075 #define CQ_ENET_RQ_DESC_FCOE_EOF_BITS               8
0076 #define CQ_ENET_RQ_DESC_FCOE_EOF_MASK \
0077     ((1 << CQ_ENET_RQ_DESC_FCOE_EOF_BITS) - 1)
0078 #define CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT              8
0079
0080 #define CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK       (0x1 << 0)
0081 #define CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK              (0x1 << 0)
0082 #define CQ_ENET_RQ_DESC_FLAGS_UDP                   (0x1 << 1)
0083 #define CQ_ENET_RQ_DESC_FCOE_ENC_ERROR              (0x1 << 1)
0084 #define CQ_ENET_RQ_DESC_FLAGS_TCP                   (0x1 << 2)
0085 #define CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK          (0x1 << 3)
0086 #define CQ_ENET_RQ_DESC_FLAGS_IPV6                  (0x1 << 4)
0087 #define CQ_ENET_RQ_DESC_FLAGS_IPV4                  (0x1 << 5)
0088 #define CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT         (0x1 << 6)
0089 #define CQ_ENET_RQ_DESC_FLAGS_FCS_OK                (0x1 << 7)
0090
0091 static inline void cq_enet_rq_desc_dec(struct cq_enet_rq_desc *desc,
0092     u8 *type, u8 *color, u16 *q_number, u16 *completed_index,
0093     u8 *ingress_port, u8 *fcoe, u8 *eop, u8 *sop, u8 *rss_type,
0094     u8 *csum_not_calc, u32 *rss_hash, u16 *bytes_written, u8 *packet_error,
0095     u8 *vlan_stripped, u16 *vlan_tci, u16 *checksum, u8 *fcoe_sof,
0096     u8 *fcoe_fc_crc_ok, u8 *fcoe_enc_error, u8 *fcoe_eof,
0097     u8 *tcp_udp_csum_ok, u8 *udp, u8 *tcp, u8 *ipv4_csum_ok,
0098     u8 *ipv6, u8 *ipv4, u8 *ipv4_fragment, u8 *fcs_ok)
0099 {
0100     u16 completed_index_flags;
0101     u16 q_number_rss_type_flags;
0102     u16 bytes_written_flags;
0103
0104     cq_desc_dec((struct cq_desc *)desc, type,
0105         color, q_number, completed_index);
0106
0107     completed_index_flags = le16_to_cpu(desc->completed_index_flags);
0108     q_number_rss_type_flags =
0109         le16_to_cpu(desc->q_number_rss_type_flags);
0110     bytes_written_flags = le16_to_cpu(desc->bytes_written_flags);
0111
0112     *ingress_port = (completed_index_flags &
0113         CQ_ENET_RQ_DESC_FLAGS_INGRESS_PORT) ? 1 : 0;
0114     *fcoe = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_FCOE) ?
0115         1 : 0;
0116     *eop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_EOP) ?
0117         1 : 0;
0118     *sop = (completed_index_flags & CQ_ENET_RQ_DESC_FLAGS_SOP) ?
0119         1 : 0;
0120
0121     *rss_type = (u8)((q_number_rss_type_flags >> CQ_DESC_Q_NUM_BITS) &
0122         CQ_ENET_RQ_DESC_RSS_TYPE_MASK);
0123     *csum_not_calc = (q_number_rss_type_flags &
0124         CQ_ENET_RQ_DESC_FLAGS_CSUM_NOT_CALC) ? 1 : 0;
0125
0126     *rss_hash = le32_to_cpu(desc->rss_hash);
0127
0128     *bytes_written = bytes_written_flags &
0129         CQ_ENET_RQ_DESC_BYTES_WRITTEN_MASK;
0130     *packet_error = (bytes_written_flags &
0131         CQ_ENET_RQ_DESC_FLAGS_TRUNCATED) ? 1 : 0;
0132     *vlan_stripped = (bytes_written_flags &
0133         CQ_ENET_RQ_DESC_FLAGS_VLAN_STRIPPED) ? 1 : 0;
0134
0135     /*
0136      * Tag Control Information(16) = user_priority(3) + cfi(1) + vlan(12)
0137      */
0138     *vlan_tci = le16_to_cpu(desc->vlan);
0139
0140     if (*fcoe) {
0141         *fcoe_sof = (u8)(le16_to_cpu(desc->checksum_fcoe) &
0142             CQ_ENET_RQ_DESC_FCOE_SOF_MASK);
0143         *fcoe_fc_crc_ok = (desc->flags &
0144             CQ_ENET_RQ_DESC_FCOE_FC_CRC_OK) ? 1 : 0;
0145         *fcoe_enc_error = (desc->flags &
0146             CQ_ENET_RQ_DESC_FCOE_ENC_ERROR) ? 1 : 0;
0147         *fcoe_eof = (u8)((le16_to_cpu(desc->checksum_fcoe) >>
0148             CQ_ENET_RQ_DESC_FCOE_EOF_SHIFT) &
0149             CQ_ENET_RQ_DESC_FCOE_EOF_MASK);
0150         *checksum = 0;
0151     } else {
0152         *fcoe_sof = 0;
0153         *fcoe_fc_crc_ok = 0;
0154         *fcoe_enc_error = 0;
0155         *fcoe_eof = 0;
0156         *checksum = le16_to_cpu(desc->checksum_fcoe);
0157     }
0158
0159     *tcp_udp_csum_ok =
0160         (desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP_UDP_CSUM_OK) ? 1 : 0;
0161     *udp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_UDP) ? 1 : 0;
0162     *tcp = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_TCP) ? 1 : 0;
0163     *ipv4_csum_ok =
0164         (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_CSUM_OK) ? 1 : 0;
0165     *ipv6 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV6) ? 1 : 0;
0166     *ipv4 = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4) ? 1 : 0;
0167     *ipv4_fragment =
0168         (desc->flags & CQ_ENET_RQ_DESC_FLAGS_IPV4_FRAGMENT) ? 1 : 0;
0169     *fcs_ok = (desc->flags & CQ_ENET_RQ_DESC_FLAGS_FCS_OK) ? 1 : 0;
0170 }
0171
0172 #endif /* _CQ_ENET_DESC_H_ */