chelsio/cxgb4vf/t4vf_defs.h

0001 /*
0002  * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
0003  * driver for Linux.
0004  *
0005  * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
0006  *
0007  * This software is available to you under a choice of one of two
0008  * licenses.  You may choose to be licensed under the terms of the GNU
0009  * General Public License (GPL) Version 2, available from the file
0010  * COPYING in the main directory of this source tree, or the
0011  * OpenIB.org BSD license below:
0012  *
0013  *     Redistribution and use in source and binary forms, with or
0014  *     without modification, are permitted provided that the following
0015  *     conditions are met:
0016  *
0017  *      - Redistributions of source code must retain the above
0018  *        copyright notice, this list of conditions and the following
0019  *        disclaimer.
0020  *
0021  *      - Redistributions in binary form must reproduce the above
0022  *        copyright notice, this list of conditions and the following
0023  *        disclaimer in the documentation and/or other materials
0024  *        provided with the distribution.
0025  *
0026  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0027  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0028  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0029  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0030  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0031  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0032  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0033  * SOFTWARE.
0034  */
0035
0036 #ifndef __T4VF_DEFS_H__
0037 #define __T4VF_DEFS_H__
0038
0039 #include "../cxgb4/t4_regs.h"
0040
0041 /*
0042  * The VF Register Map.
0043  *
0044  * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
0045  * bus module (PL) and CPU Interface Module (CIM) components are mapped via
0046  * the Slice to Module Map Table (see below) in the Physical Function Register
0047  * Map.  The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
0048  * and Offset registers in the PF Register Map.  The MBDATA base address is
0049  * quite constrained as it determines the Mailbox Data addresses for both PFs
0050  * and VFs, and therefore must fit in both the VF and PF Register Maps without
0051  * overlapping other registers.
0052  */
0053 #define T4VF_SGE_BASE_ADDR  0x0000
0054 #define T4VF_MPS_BASE_ADDR  0x0100
0055 #define T4VF_PL_BASE_ADDR   0x0200
0056 #define T4VF_MBDATA_BASE_ADDR   0x0240
0057 #define T6VF_MBDATA_BASE_ADDR   0x0280
0058 #define T4VF_CIM_BASE_ADDR  0x0300
0059
0060 #define T4VF_REGMAP_START   0x0000
0061 #define T4VF_REGMAP_SIZE    0x0400
0062
0063 /*
0064  * There's no hardware limitation which requires that the addresses of the
0065  * Mailbox Data in the fixed CIM PF map and the programmable VF map must
0066  * match.  However, it's a useful convention ...
0067  */
0068 #if T4VF_MBDATA_BASE_ADDR != CIM_PF_MAILBOX_DATA_A
0069 #error T4VF_MBDATA_BASE_ADDR must match CIM_PF_MAILBOX_DATA_A!
0070 #endif
0071
0072 /*
0073  * Virtual Function "Slice to Module Map Table" definitions.
0074  *
0075  * This table allows us to map subsets of the various module register sets
0076  * into the T4VF Register Map.  Each table entry identifies the index of the
0077  * module whose registers are being mapped, the offset within the module's
0078  * register set that the mapping should start at, the limit of the mapping,
0079  * and the offset within the T4VF Register Map to which the module's registers
0080  * are being mapped.  All addresses and qualtities are in terms of 32-bit
0081  * words.  The "limit" value is also in terms of 32-bit words and is equal to
0082  * the last address mapped in the T4VF Register Map 1 (i.e. it's a "<="
0083  * relation rather than a "<").
0084  */
0085 #define T4VF_MOD_MAP(module, index, first, last) \
0086     T4VF_MOD_MAP_##module##_INDEX  = (index), \
0087     T4VF_MOD_MAP_##module##_FIRST  = (first), \
0088     T4VF_MOD_MAP_##module##_LAST   = (last), \
0089     T4VF_MOD_MAP_##module##_OFFSET = ((first)/4), \
0090     T4VF_MOD_MAP_##module##_BASE = \
0091         (T4VF_##module##_BASE_ADDR/4 + (first)/4), \
0092     T4VF_MOD_MAP_##module##_LIMIT = \
0093         (T4VF_##module##_BASE_ADDR/4 + (last)/4),
0094
0095 #define SGE_VF_KDOORBELL 0x0
0096 #define SGE_VF_GTS 0x4
0097 #define MPS_VF_CTL 0x0
0098 #define MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
0099 #define PL_VF_WHOAMI 0x0
0100 #define CIM_VF_EXT_MAILBOX_CTRL 0x0
0101 #define CIM_VF_EXT_MAILBOX_STATUS 0x4
0102
0103 enum {
0104     T4VF_MOD_MAP(SGE, 2, SGE_VF_KDOORBELL, SGE_VF_GTS)
0105     T4VF_MOD_MAP(MPS, 0, MPS_VF_CTL, MPS_VF_STAT_RX_VF_ERR_FRAMES_H)
0106     T4VF_MOD_MAP(PL,  3, PL_VF_WHOAMI, PL_VF_WHOAMI)
0107     T4VF_MOD_MAP(CIM, 1, CIM_VF_EXT_MAILBOX_CTRL, CIM_VF_EXT_MAILBOX_STATUS)
0108 };
0109
0110 /*
0111  * There isn't a Slice to Module Map Table entry for the Mailbox Data
0112  * registers, but it's convenient to use similar names as above.  There are 8
0113  * little-endian 64-bit Mailbox Data registers.  Note that the "instances"
0114  * value below is in terms of 32-bit words which matches the "word" addressing
0115  * space we use above for the Slice to Module Map Space.
0116  */
0117 #define NUM_CIM_VF_MAILBOX_DATA_INSTANCES 16
0118
0119 #define T4VF_MBDATA_FIRST   0
0120 #define T4VF_MBDATA_LAST    ((NUM_CIM_VF_MAILBOX_DATA_INSTANCES-1)*4)
0121
0122 #endif /* __T4T4VF_DEFS_H__ */