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0001 /* 0002 * This file is part of the Chelsio T4 Ethernet driver for Linux. 0003 * 0004 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 0005 * 0006 * This software is available to you under a choice of one of two 0007 * licenses. You may choose to be licensed under the terms of the GNU 0008 * General Public License (GPL) Version 2, available from the file 0009 * COPYING in the main directory of this source tree, or the 0010 * OpenIB.org BSD license below: 0011 * 0012 * Redistribution and use in source and binary forms, with or 0013 * without modification, are permitted provided that the following 0014 * conditions are met: 0015 * 0016 * - Redistributions of source code must retain the above 0017 * copyright notice, this list of conditions and the following 0018 * disclaimer. 0019 * 0020 * - Redistributions in binary form must reproduce the above 0021 * copyright notice, this list of conditions and the following 0022 * disclaimer in the documentation and/or other materials 0023 * provided with the distribution. 0024 * 0025 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 0026 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 0027 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 0028 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 0029 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 0030 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 0031 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 0032 * SOFTWARE. 0033 */ 0034 0035 #ifndef __T4_VALUES_H__ 0036 #define __T4_VALUES_H__ 0037 0038 /* This file contains definitions for various T4 register value hardware 0039 * constants. The types of values encoded here are predominantly those for 0040 * register fields which control "modal" behavior. For the most part, we do 0041 * not include definitions for register fields which are simple numeric 0042 * metrics, etc. 0043 */ 0044 0045 /* SGE register field values. 0046 */ 0047 0048 /* CONTROL1 register */ 0049 #define RXPKTCPLMODE_SPLIT_X 1 0050 0051 #define INGPCIEBOUNDARY_SHIFT_X 5 0052 #define INGPCIEBOUNDARY_32B_X 0 0053 0054 #define INGPADBOUNDARY_SHIFT_X 5 0055 0056 #define T6_INGPADBOUNDARY_SHIFT_X 3 0057 #define T6_INGPADBOUNDARY_8B_X 0 0058 #define T6_INGPADBOUNDARY_32B_X 2 0059 0060 #define INGPADBOUNDARY_32B_X 0 0061 0062 /* CONTROL2 register */ 0063 #define INGPACKBOUNDARY_SHIFT_X 5 0064 #define INGPACKBOUNDARY_16B_X 0 0065 #define INGPACKBOUNDARY_64B_X 1 0066 0067 /* GTS register */ 0068 #define SGE_TIMERREGS 6 0069 #define TIMERREG_COUNTER0_X 0 0070 0071 #define FETCHBURSTMIN_64B_X 2 0072 #define FETCHBURSTMIN_128B_X 3 0073 0074 /* T6 and later use a single-bit encoding for FetchBurstMin */ 0075 #define FETCHBURSTMIN_64B_T6_X 0 0076 #define FETCHBURSTMIN_128B_T6_X 1 0077 0078 #define FETCHBURSTMAX_256B_X 2 0079 #define FETCHBURSTMAX_512B_X 3 0080 0081 #define HOSTFCMODE_INGRESS_QUEUE_X 1 0082 #define HOSTFCMODE_STATUS_PAGE_X 2 0083 0084 #define CIDXFLUSHTHRESH_32_X 5 0085 #define CIDXFLUSHTHRESH_128_X 7 0086 0087 #define UPDATEDELIVERY_INTERRUPT_X 1 0088 0089 #define RSPD_TYPE_FLBUF_X 0 0090 #define RSPD_TYPE_CPL_X 1 0091 #define RSPD_TYPE_INTR_X 2 0092 0093 /* Congestion Manager Definitions. 0094 */ 0095 #define CONMCTXT_CNGTPMODE_S 19 0096 #define CONMCTXT_CNGTPMODE_V(x) ((x) << CONMCTXT_CNGTPMODE_S) 0097 #define CONMCTXT_CNGCHMAP_S 0 0098 #define CONMCTXT_CNGCHMAP_V(x) ((x) << CONMCTXT_CNGCHMAP_S) 0099 #define CONMCTXT_CNGTPMODE_CHANNEL_X 2 0100 #define CONMCTXT_CNGTPMODE_QUEUE_X 1 0101 0102 /* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues. 0103 * The User Doorbells are each 128 bytes in length with a Simple Doorbell at 0104 * offsets 8x and a Write Combining single 64-byte Egress Queue Unit 0105 * (IDXSIZE_UNIT_X) Gather Buffer interface at offset 64. For Ingress Queues, 0106 * we have a Going To Sleep register at offsets 8x+4. 0107 * 0108 * As noted above, we have many instances of the Simple Doorbell and Going To 0109 * Sleep registers at offsets 8x and 8x+4, respectively. We want to use a 0110 * non-64-byte aligned offset for the Simple Doorbell in order to attempt to 0111 * avoid buffering of the writes to the Simple Doorbell and we want to use a 0112 * non-contiguous offset for the Going To Sleep writes in order to avoid 0113 * possible combining between them. 0114 */ 0115 #define SGE_UDB_SIZE 128 0116 #define SGE_UDB_KDOORBELL 8 0117 #define SGE_UDB_GTS 20 0118 #define SGE_UDB_WCDOORBELL 64 0119 0120 /* CIM register field values. 0121 */ 0122 #define X_MBOWNER_FW 1 0123 #define X_MBOWNER_PL 2 0124 0125 /* PCI-E definitions */ 0126 #define WINDOW_SHIFT_X 10 0127 #define PCIEOFST_SHIFT_X 10 0128 0129 /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the 0130 * Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP 0131 * selects for a particular field being present. These fields, when present 0132 * in the Compressed Filter Tuple, have the following widths in bits. 0133 */ 0134 #define FT_FCOE_W 1 0135 #define FT_PORT_W 3 0136 #define FT_VNIC_ID_W 17 0137 #define FT_VLAN_W 17 0138 #define FT_TOS_W 8 0139 #define FT_PROTOCOL_W 8 0140 #define FT_ETHERTYPE_W 16 0141 #define FT_MACMATCH_W 9 0142 #define FT_MPSHITTYPE_W 3 0143 #define FT_FRAGMENTATION_W 1 0144 0145 /* Some of the Compressed Filter Tuple fields have internal structure. These 0146 * bit shifts/masks describe those structures. All shifts are relative to the 0147 * base position of the fields within the Compressed Filter Tuple 0148 */ 0149 #define FT_VLAN_VLD_S 16 0150 #define FT_VLAN_VLD_V(x) ((x) << FT_VLAN_VLD_S) 0151 #define FT_VLAN_VLD_F FT_VLAN_VLD_V(1U) 0152 0153 #define FT_VNID_ID_VF_S 0 0154 #define FT_VNID_ID_VF_V(x) ((x) << FT_VNID_ID_VF_S) 0155 0156 #define FT_VNID_ID_PF_S 7 0157 #define FT_VNID_ID_PF_V(x) ((x) << FT_VNID_ID_PF_S) 0158 0159 #define FT_VNID_ID_VLD_S 16 0160 #define FT_VNID_ID_VLD_V(x) ((x) << FT_VNID_ID_VLD_S) 0161 0162 #endif /* __T4_VALUES_H__ */
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