chelsio/cxgb4/t4_hw.h

0001 /*
0002  * This file is part of the Chelsio T4 Ethernet driver for Linux.
0003  *
0004  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
0005  *
0006  * This software is available to you under a choice of one of two
0007  * licenses.  You may choose to be licensed under the terms of the GNU
0008  * General Public License (GPL) Version 2, available from the file
0009  * COPYING in the main directory of this source tree, or the
0010  * OpenIB.org BSD license below:
0011  *
0012  *     Redistribution and use in source and binary forms, with or
0013  *     without modification, are permitted provided that the following
0014  *     conditions are met:
0015  *
0016  *      - Redistributions of source code must retain the above
0017  *        copyright notice, this list of conditions and the following
0018  *        disclaimer.
0019  *
0020  *      - Redistributions in binary form must reproduce the above
0021  *        copyright notice, this list of conditions and the following
0022  *        disclaimer in the documentation and/or other materials
0023  *        provided with the distribution.
0024  *
0025  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0026  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0027  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0028  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0029  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0030  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0031  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0032  * SOFTWARE.
0033  */
0034
0035 #ifndef __T4_HW_H
0036 #define __T4_HW_H
0037
0038 #include <linux/types.h>
0039
0040 enum {
0041     NCHAN           = 4,    /* # of HW channels */
0042     MAX_MTU         = 9600, /* max MAC MTU, excluding header + FCS */
0043     EEPROMSIZE      = 17408,/* Serial EEPROM physical size */
0044     EEPROMVSIZE     = 32768,/* Serial EEPROM virtual address space size */
0045     EEPROMPFSIZE    = 1024, /* EEPROM writable area size for PFn, n>0 */
0046     RSS_NENTRIES    = 2048, /* # of entries in RSS mapping table */
0047     T6_RSS_NENTRIES = 4096, /* # of entries in RSS mapping table */
0048     TCB_SIZE        = 128,  /* TCB size */
0049     NMTUS           = 16,   /* size of MTU table */
0050     NCCTRL_WIN      = 32,   /* # of congestion control windows */
0051     NTX_SCHED       = 8,    /* # of HW Tx scheduling queues */
0052     PM_NSTATS       = 5,    /* # of PM stats */
0053     T6_PM_NSTATS    = 7,    /* # of PM stats in T6 */
0054     MBOX_LEN        = 64,   /* mailbox size in bytes */
0055     TRACE_LEN       = 112,  /* length of trace data and mask */
0056     FILTER_OPT_LEN  = 36,   /* filter tuple width for optional components */
0057 };
0058
0059 enum {
0060     CIM_NUM_IBQ    = 6,     /* # of CIM IBQs */
0061     CIM_NUM_OBQ    = 6,     /* # of CIM OBQs */
0062     CIM_NUM_OBQ_T5 = 8,     /* # of CIM OBQs for T5 adapter */
0063     CIMLA_SIZE     = 2048,  /* # of 32-bit words in CIM LA */
0064     CIM_PIFLA_SIZE = 64,    /* # of 192-bit words in CIM PIF LA */
0065     CIM_MALA_SIZE  = 64,    /* # of 160-bit words in CIM MA LA */
0066     CIM_IBQ_SIZE   = 128,   /* # of 128-bit words in a CIM IBQ */
0067     CIM_OBQ_SIZE   = 128,   /* # of 128-bit words in a CIM OBQ */
0068     TPLA_SIZE      = 128,   /* # of 64-bit words in TP LA */
0069     ULPRX_LA_SIZE  = 512,   /* # of 256-bit words in ULP_RX LA */
0070 };
0071
0072 /* SGE context types */
0073 enum ctxt_type {
0074     CTXT_EGRESS,
0075     CTXT_INGRESS,
0076     CTXT_FLM,
0077     CTXT_CNM,
0078 };
0079
0080 enum {
0081     SF_PAGE_SIZE = 256,           /* serial flash page size */
0082     SF_SEC_SIZE = 64 * 1024,      /* serial flash sector size */
0083 };
0084
0085 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
0086
0087 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV };    /* mailbox owners */
0088
0089 enum {
0090     SGE_MAX_WR_LEN = 512,     /* max WR size in bytes */
0091     SGE_CTXT_SIZE = 24,       /* size of SGE context */
0092     SGE_NTIMERS = 6,          /* # of interrupt holdoff timer values */
0093     SGE_NCOUNTERS = 4,        /* # of interrupt packet counter values */
0094     SGE_NDBQTIMERS = 8,       /* # of Doorbell Queue Timer values */
0095     SGE_MAX_IQ_SIZE = 65520,
0096
0097     SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */
0098     SGE_TIMER_UPD_CIDX = 7,   /* update cidx only */
0099
0100     SGE_EQ_IDXSIZE = 64,      /* egress queue pidx/cidx unit size */
0101
0102     SGE_INTRDST_PCI = 0,      /* interrupt destination is PCI-E */
0103     SGE_INTRDST_IQ = 1,       /*   destination is an ingress queue */
0104
0105     SGE_UPDATEDEL_NONE = 0,   /* ingress queue pidx update delivery */
0106     SGE_UPDATEDEL_INTR = 1,   /*   interrupt */
0107     SGE_UPDATEDEL_STPG = 2,   /*   status page */
0108     SGE_UPDATEDEL_BOTH = 3,   /*   interrupt and status page */
0109
0110     SGE_HOSTFCMODE_NONE = 0,  /* egress queue cidx updates */
0111     SGE_HOSTFCMODE_IQ = 1,    /*   sent to ingress queue */
0112     SGE_HOSTFCMODE_STPG = 2,  /*   sent to status page */
0113     SGE_HOSTFCMODE_BOTH = 3,  /*   ingress queue and status page */
0114
0115     SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */
0116     SGE_FETCHBURSTMIN_32B = 1,
0117     SGE_FETCHBURSTMIN_64B = 2,
0118     SGE_FETCHBURSTMIN_128B = 3,
0119
0120     SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */
0121     SGE_FETCHBURSTMAX_128B = 1,
0122     SGE_FETCHBURSTMAX_256B = 2,
0123     SGE_FETCHBURSTMAX_512B = 3,
0124
0125     SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */
0126     SGE_CIDXFLUSHTHRESH_2 = 1,
0127     SGE_CIDXFLUSHTHRESH_4 = 2,
0128     SGE_CIDXFLUSHTHRESH_8 = 3,
0129     SGE_CIDXFLUSHTHRESH_16 = 4,
0130     SGE_CIDXFLUSHTHRESH_32 = 5,
0131     SGE_CIDXFLUSHTHRESH_64 = 6,
0132     SGE_CIDXFLUSHTHRESH_128 = 7,
0133
0134     SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */
0135 };
0136
0137 /* PCI-e memory window access */
0138 enum pcie_memwin {
0139     MEMWIN_NIC      = 0,
0140     MEMWIN_RSVD1    = 1,
0141     MEMWIN_RSVD2    = 2,
0142     MEMWIN_RDMA     = 3,
0143     MEMWIN_RSVD4    = 4,
0144     MEMWIN_FOISCSI  = 5,
0145     MEMWIN_CSIOSTOR = 6,
0146     MEMWIN_RSVD7    = 7,
0147 };
0148
0149 struct sge_qstat {                /* data written to SGE queue status entries */
0150     __be32 qid;
0151     __be16 cidx;
0152     __be16 pidx;
0153 };
0154
0155 /*
0156  * Structure for last 128 bits of response descriptors
0157  */
0158 struct rsp_ctrl {
0159     __be32 hdrbuflen_pidx;
0160     __be32 pldbuflen_qid;
0161     union {
0162         u8 type_gen;
0163         __be64 last_flit;
0164     };
0165 };
0166
0167 #define RSPD_NEWBUF_S    31
0168 #define RSPD_NEWBUF_V(x) ((x) << RSPD_NEWBUF_S)
0169 #define RSPD_NEWBUF_F    RSPD_NEWBUF_V(1U)
0170
0171 #define RSPD_LEN_S    0
0172 #define RSPD_LEN_M    0x7fffffff
0173 #define RSPD_LEN_G(x) (((x) >> RSPD_LEN_S) & RSPD_LEN_M)
0174
0175 #define RSPD_QID_S    RSPD_LEN_S
0176 #define RSPD_QID_M    RSPD_LEN_M
0177 #define RSPD_QID_G(x) RSPD_LEN_G(x)
0178
0179 #define RSPD_GEN_S    7
0180
0181 #define RSPD_TYPE_S    4
0182 #define RSPD_TYPE_M    0x3
0183 #define RSPD_TYPE_G(x) (((x) >> RSPD_TYPE_S) & RSPD_TYPE_M)
0184
0185 /* Rx queue interrupt deferral fields: counter enable and timer index */
0186 #define QINTR_CNT_EN_S    0
0187 #define QINTR_CNT_EN_V(x) ((x) << QINTR_CNT_EN_S)
0188 #define QINTR_CNT_EN_F    QINTR_CNT_EN_V(1U)
0189
0190 #define QINTR_TIMER_IDX_S    1
0191 #define QINTR_TIMER_IDX_M    0x7
0192 #define QINTR_TIMER_IDX_V(x) ((x) << QINTR_TIMER_IDX_S)
0193 #define QINTR_TIMER_IDX_G(x) (((x) >> QINTR_TIMER_IDX_S) & QINTR_TIMER_IDX_M)
0194
0195 /*
0196  * Flash layout.
0197  */
0198 #define FLASH_START(start)  ((start) * SF_SEC_SIZE)
0199 #define FLASH_MAX_SIZE(nsecs)   ((nsecs) * SF_SEC_SIZE)
0200
0201 enum {
0202     /*
0203      * Various Expansion-ROM boot images, etc.
0204      */
0205     FLASH_EXP_ROM_START_SEC = 0,
0206     FLASH_EXP_ROM_NSECS = 6,
0207     FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
0208     FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
0209
0210     /*
0211      * iSCSI Boot Firmware Table (iBFT) and other driver-related
0212      * parameters ...
0213      */
0214     FLASH_IBFT_START_SEC = 6,
0215     FLASH_IBFT_NSECS = 1,
0216     FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
0217     FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
0218
0219     /*
0220      * Boot configuration data.
0221      */
0222     FLASH_BOOTCFG_START_SEC = 7,
0223     FLASH_BOOTCFG_NSECS = 1,
0224     FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
0225     FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
0226
0227     /*
0228      * Location of firmware image in FLASH.
0229      */
0230     FLASH_FW_START_SEC = 8,
0231     FLASH_FW_NSECS = 16,
0232     FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
0233     FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
0234
0235     /* Location of bootstrap firmware image in FLASH.
0236      */
0237     FLASH_FWBOOTSTRAP_START_SEC = 27,
0238     FLASH_FWBOOTSTRAP_NSECS = 1,
0239     FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
0240     FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
0241
0242     /*
0243      * iSCSI persistent/crash information.
0244      */
0245     FLASH_ISCSI_CRASH_START_SEC = 29,
0246     FLASH_ISCSI_CRASH_NSECS = 1,
0247     FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
0248     FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
0249
0250     /*
0251      * FCoE persistent/crash information.
0252      */
0253     FLASH_FCOE_CRASH_START_SEC = 30,
0254     FLASH_FCOE_CRASH_NSECS = 1,
0255     FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
0256     FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
0257
0258     /*
0259      * Location of Firmware Configuration File in FLASH.  Since the FPGA
0260      * "FLASH" is smaller we need to store the Configuration File in a
0261      * different location -- which will overlap the end of the firmware
0262      * image if firmware ever gets that large ...
0263      */
0264     FLASH_CFG_START_SEC = 31,
0265     FLASH_CFG_NSECS = 1,
0266     FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
0267     FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
0268
0269     /* We don't support FLASH devices which can't support the full
0270      * standard set of sections which we need for normal
0271      * operations.
0272      */
0273     FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
0274
0275     FLASH_FPGA_CFG_START_SEC = 15,
0276     FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
0277
0278     /*
0279      * Sectors 32-63 are reserved for FLASH failover.
0280      */
0281 };
0282
0283 #undef FLASH_START
0284 #undef FLASH_MAX_SIZE
0285
0286 #define SGE_TIMESTAMP_S 0
0287 #define SGE_TIMESTAMP_M 0xfffffffffffffffULL
0288 #define SGE_TIMESTAMP_V(x) ((__u64)(x) << SGE_TIMESTAMP_S)
0289 #define SGE_TIMESTAMP_G(x) (((__u64)(x) >> SGE_TIMESTAMP_S) & SGE_TIMESTAMP_M)
0290
0291 #define I2C_DEV_ADDR_A0     0xa0
0292 #define I2C_DEV_ADDR_A2     0xa2
0293 #define I2C_PAGE_SIZE       0x100
0294 #define SFP_DIAG_TYPE_ADDR  0x5c
0295 #define SFP_DIAG_TYPE_LEN   0x1
0296 #define SFP_DIAG_ADDRMODE   BIT(2)
0297 #define SFP_DIAG_IMPLEMENTED    BIT(6)
0298 #define SFF_8472_COMP_ADDR  0x5e
0299 #define SFF_8472_COMP_LEN   0x1
0300 #define SFF_REV_ADDR        0x1
0301 #define SFF_REV_LEN     0x1
0302
0303 #endif /* __T4_HW_H */