chelsio/cxgb4/cxgb4_dcb.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  Copyright (C) 2013-2014 Chelsio Communications.  All rights reserved.
0004  *
0005  *  Written by Anish Bhatt (anish@chelsio.com)
0006  */
0007
0008 #ifndef __CXGB4_DCB_H
0009 #define __CXGB4_DCB_H
0010
0011 #include <linux/netdevice.h>
0012 #include <linux/dcbnl.h>
0013 #include <net/dcbnl.h>
0014
0015 #ifdef CONFIG_CHELSIO_T4_DCB
0016
0017 #define CXGB4_DCBX_FW_SUPPORT \
0018     (DCB_CAP_DCBX_VER_CEE | \
0019      DCB_CAP_DCBX_VER_IEEE | \
0020      DCB_CAP_DCBX_LLD_MANAGED)
0021 #define CXGB4_DCBX_HOST_SUPPORT \
0022     (DCB_CAP_DCBX_VER_CEE | \
0023      DCB_CAP_DCBX_VER_IEEE | \
0024      DCB_CAP_DCBX_HOST)
0025
0026 #define CXGB4_MAX_PRIORITY      CXGB4_MAX_DCBX_APP_SUPPORTED
0027 #define CXGB4_MAX_TCS           CXGB4_MAX_DCBX_APP_SUPPORTED
0028
0029 #define INIT_PORT_DCB_CMD(__pcmd, __port, __op, __action) \
0030     do { \
0031         memset(&(__pcmd), 0, sizeof(__pcmd)); \
0032         (__pcmd).op_to_portid = \
0033             cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) | \
0034                     FW_CMD_REQUEST_F | \
0035                     FW_CMD_##__op##_F | \
0036                     FW_PORT_CMD_PORTID_V(__port)); \
0037         (__pcmd).action_to_len16 = \
0038             cpu_to_be32(FW_PORT_CMD_ACTION_V(__action) | \
0039                     FW_LEN16(pcmd)); \
0040     } while (0)
0041
0042 #define INIT_PORT_DCB_READ_PEER_CMD(__pcmd, __port) \
0043     INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_RECV)
0044
0045 #define INIT_PORT_DCB_READ_LOCAL_CMD(__pcmd, __port) \
0046     INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_TRANS)
0047
0048 #define INIT_PORT_DCB_READ_SYNC_CMD(__pcmd, __port) \
0049     INIT_PORT_DCB_CMD(__pcmd, __port, READ, FW_PORT_ACTION_DCB_READ_DET)
0050
0051 #define INIT_PORT_DCB_WRITE_CMD(__pcmd, __port) \
0052     INIT_PORT_DCB_CMD(__pcmd, __port, EXEC, FW_PORT_ACTION_L2_DCB_CFG)
0053
0054 #define IEEE_FAUX_SYNC(__dev, __dcb) \
0055     do { \
0056         if ((__dcb)->dcb_version == FW_PORT_DCB_VER_IEEE) \
0057             cxgb4_dcb_state_fsm((__dev), \
0058                         CXGB4_DCB_INPUT_FW_ALLSYNCED); \
0059     } while (0)
0060
0061 /* States we can be in for a port's Data Center Bridging.
0062  */
0063 enum cxgb4_dcb_state {
0064     CXGB4_DCB_STATE_START,      /* initial unknown state */
0065     CXGB4_DCB_STATE_HOST,       /* we're using Host DCB (if at all) */
0066     CXGB4_DCB_STATE_FW_INCOMPLETE,  /* using firmware DCB, incomplete */
0067     CXGB4_DCB_STATE_FW_ALLSYNCED,   /* using firmware DCB, all sync'ed */
0068 };
0069
0070 /* Data Center Bridging state input for the Finite State Machine.
0071  */
0072 enum cxgb4_dcb_state_input {
0073     /* Input from the firmware.
0074      */
0075     CXGB4_DCB_INPUT_FW_DISABLED,    /* firmware DCB disabled */
0076     CXGB4_DCB_INPUT_FW_ENABLED, /* firmware DCB enabled */
0077     CXGB4_DCB_INPUT_FW_INCOMPLETE,  /* firmware reports incomplete DCB */
0078     CXGB4_DCB_INPUT_FW_ALLSYNCED,   /* firmware reports all sync'ed */
0079
0080 };
0081
0082 /* Firmware DCB messages that we've received so far ...
0083  */
0084 enum cxgb4_dcb_fw_msgs {
0085     CXGB4_DCB_FW_PGID   = 0x01,
0086     CXGB4_DCB_FW_PGRATE = 0x02,
0087     CXGB4_DCB_FW_PRIORATE   = 0x04,
0088     CXGB4_DCB_FW_PFC    = 0x08,
0089     CXGB4_DCB_FW_APP_ID = 0x10,
0090 };
0091
0092 #define CXGB4_MAX_DCBX_APP_SUPPORTED 8
0093
0094 /* Data Center Bridging support;
0095  */
0096 struct port_dcb_info {
0097     enum cxgb4_dcb_state state; /* DCB State Machine */
0098     enum cxgb4_dcb_fw_msgs msgs;    /* DCB Firmware messages received */
0099     unsigned int supported;     /* OS DCB capabilities supported */
0100     bool enabled;           /* OS Enabled state */
0101
0102     /* Cached copies of DCB information sent by the firmware (in Host
0103      * Native Endian format).
0104      */
0105     u32 pgid;           /* Priority Group[0..7] */
0106     u8  dcb_version;        /* Running DCBx version */
0107     u8  pfcen;          /* Priority Flow Control[0..7] */
0108     u8  pg_num_tcs_supported;   /* max PG Traffic Classes */
0109     u8  pfc_num_tcs_supported;  /* max PFC Traffic Classes */
0110     u8  pgrate[8];      /* Priority Group Rate[0..7] */
0111     u8  priorate[8];        /* Priority Rate[0..7] */
0112     u8  tsa[8];         /* TSA Algorithm[0..7] */
0113     struct app_priority { /* Application Information */
0114         u8  user_prio_map;  /* Priority Map bitfield */
0115         u8  sel_field;  /* Protocol ID interpretation */
0116         u16 protocolid; /* Protocol ID */
0117     } app_priority[CXGB4_MAX_DCBX_APP_SUPPORTED];
0118 };
0119
0120 void cxgb4_dcb_state_init(struct net_device *);
0121 void cxgb4_dcb_version_init(struct net_device *);
0122 void cxgb4_dcb_reset(struct net_device *dev);
0123 void cxgb4_dcb_state_fsm(struct net_device *, enum cxgb4_dcb_state_input);
0124 void cxgb4_dcb_handle_fw_update(struct adapter *, const struct fw_port_cmd *);
0125 void cxgb4_dcb_set_caps(struct adapter *, const struct fw_port_cmd *);
0126 extern const struct dcbnl_rtnl_ops cxgb4_dcb_ops;
0127
0128 static inline __u8 bitswap_1(unsigned char val)
0129 {
0130     return ((val & 0x80) >> 7) |
0131            ((val & 0x40) >> 5) |
0132            ((val & 0x20) >> 3) |
0133            ((val & 0x10) >> 1) |
0134            ((val & 0x08) << 1) |
0135            ((val & 0x04) << 3) |
0136            ((val & 0x02) << 5) |
0137            ((val & 0x01) << 7);
0138 }
0139
0140 extern const char * const dcb_ver_array[];
0141
0142 #define CXGB4_DCB_ENABLED true
0143
0144 #else /* !CONFIG_CHELSIO_T4_DCB */
0145
0146 static inline void cxgb4_dcb_state_init(struct net_device *dev)
0147 {
0148 }
0149
0150 #define CXGB4_DCB_ENABLED false
0151
0152 #endif /* !CONFIG_CHELSIO_T4_DCB */
0153
0154 #endif /* __CXGB4_DCB_H */