chelsio/cxgb4/cudbg_entity.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  Copyright (C) 2017 Chelsio Communications.  All rights reserved.
0004  */
0005
0006 #ifndef __CUDBG_ENTITY_H__
0007 #define __CUDBG_ENTITY_H__
0008
0009 #define EDC0_FLAG 0
0010 #define EDC1_FLAG 1
0011 #define MC_FLAG 2
0012 #define MC0_FLAG 3
0013 #define MC1_FLAG 4
0014 #define HMA_FLAG 5
0015
0016 #define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
0017
0018 struct cudbg_mbox_log {
0019     struct mbox_cmd entry;
0020     u32 hi[MBOX_LEN / 8];
0021     u32 lo[MBOX_LEN / 8];
0022 };
0023
0024 struct cudbg_cim_qcfg {
0025     u8 chip;
0026     u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
0027     u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
0028     u16 thres[CIM_NUM_IBQ];
0029     u32 obq_wr[2 * CIM_NUM_OBQ_T5];
0030     u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
0031 };
0032
0033 struct cudbg_rss_vf_conf {
0034     u32 rss_vf_vfl;
0035     u32 rss_vf_vfh;
0036 };
0037
0038 struct cudbg_pm_stats {
0039     u32 tx_cnt[T6_PM_NSTATS];
0040     u32 rx_cnt[T6_PM_NSTATS];
0041     u64 tx_cyc[T6_PM_NSTATS];
0042     u64 rx_cyc[T6_PM_NSTATS];
0043 };
0044
0045 struct cudbg_hw_sched {
0046     u32 kbps[NTX_SCHED];
0047     u32 ipg[NTX_SCHED];
0048     u32 pace_tab[NTX_SCHED];
0049     u32 mode;
0050     u32 map;
0051 };
0052
0053 #define SGE_QBASE_DATA_REG_NUM 4
0054
0055 struct sge_qbase_reg_field {
0056     u32 reg_addr;
0057     u32 reg_data[SGE_QBASE_DATA_REG_NUM];
0058     /* Max supported PFs */
0059     u32 pf_data_value[PCIE_FW_MASTER_M + 1][SGE_QBASE_DATA_REG_NUM];
0060     /* Max supported VFs */
0061     u32 vf_data_value[T6_VF_M + 1][SGE_QBASE_DATA_REG_NUM];
0062     u32 vfcount; /* Actual number of max vfs in current configuration */
0063 };
0064
0065 struct ireg_field {
0066     u32 ireg_addr;
0067     u32 ireg_data;
0068     u32 ireg_local_offset;
0069     u32 ireg_offset_range;
0070 };
0071
0072 struct ireg_buf {
0073     struct ireg_field tp_pio;
0074     u32 outbuf[32];
0075 };
0076
0077 struct cudbg_ulprx_la {
0078     u32 data[ULPRX_LA_SIZE * 8];
0079     u32 size;
0080 };
0081
0082 struct cudbg_tp_la {
0083     u32 size;
0084     u32 mode;
0085     u8 data[];
0086 };
0087
0088 static const char * const cudbg_region[] = {
0089     "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
0090     "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
0091     "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
0092     "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
0093     "RQUDP region:", "PBL region:", "TXPBL region:",
0094     "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
0095     "On-chip queues:"
0096 };
0097
0098 /* Memory region info relative to current memory (i.e. wrt 0). */
0099 struct cudbg_region_info {
0100     bool exist; /* Does region exists in current memory? */
0101     u32 start;  /* Start wrt 0 */
0102     u32 end;    /* End wrt 0 */
0103 };
0104
0105 struct cudbg_mem_desc {
0106     u32 base;
0107     u32 limit;
0108     u32 idx;
0109 };
0110
0111 #define CUDBG_MEMINFO_REV 1
0112
0113 struct cudbg_meminfo {
0114     struct cudbg_mem_desc avail[4];
0115     struct cudbg_mem_desc mem[ARRAY_SIZE(cudbg_region) + 3];
0116     u32 avail_c;
0117     u32 mem_c;
0118     u32 up_ram_lo;
0119     u32 up_ram_hi;
0120     u32 up_extmem2_lo;
0121     u32 up_extmem2_hi;
0122     u32 rx_pages_data[3];
0123     u32 tx_pages_data[4];
0124     u32 p_structs;
0125     u32 reserved[12];
0126     u32 port_used[4];
0127     u32 port_alloc[4];
0128     u32 loopback_used[NCHAN];
0129     u32 loopback_alloc[NCHAN];
0130     u32 p_structs_free_cnt;
0131     u32 free_rx_cnt;
0132     u32 free_tx_cnt;
0133 };
0134
0135 struct cudbg_cim_pif_la {
0136     int size;
0137     u8 data[];
0138 };
0139
0140 struct cudbg_clk_info {
0141     u64 retransmit_min;
0142     u64 retransmit_max;
0143     u64 persist_timer_min;
0144     u64 persist_timer_max;
0145     u64 keepalive_idle_timer;
0146     u64 keepalive_interval;
0147     u64 initial_srtt;
0148     u64 finwait2_timer;
0149     u32 dack_timer;
0150     u32 res;
0151     u32 cclk_ps;
0152     u32 tre;
0153     u32 dack_re;
0154 };
0155
0156 struct cudbg_tid_info_region {
0157     u32 ntids;
0158     u32 nstids;
0159     u32 stid_base;
0160     u32 hash_base;
0161
0162     u32 natids;
0163     u32 nftids;
0164     u32 ftid_base;
0165     u32 aftid_base;
0166     u32 aftid_end;
0167
0168     u32 sftid_base;
0169     u32 nsftids;
0170
0171     u32 uotid_base;
0172     u32 nuotids;
0173
0174     u32 sb;
0175     u32 flags;
0176     u32 le_db_conf;
0177     u32 ip_users;
0178     u32 ipv6_users;
0179
0180     u32 hpftid_base;
0181     u32 nhpftids;
0182 };
0183
0184 #define CUDBG_TID_INFO_REV 1
0185
0186 struct cudbg_tid_info_region_rev1 {
0187     struct cudbg_ver_hdr ver_hdr;
0188     struct cudbg_tid_info_region tid;
0189     u32 tid_start;
0190     u32 reserved[16];
0191 };
0192
0193 #define CUDBG_LOWMEM_MAX_CTXT_QIDS 256
0194 #define CUDBG_MAX_FL_QIDS 1024
0195
0196 struct cudbg_ch_cntxt {
0197     u32 cntxt_type;
0198     u32 cntxt_id;
0199     u32 data[SGE_CTXT_SIZE / 4];
0200 };
0201
0202 #define CUDBG_MAX_RPLC_SIZE 128
0203
0204 struct cudbg_mps_tcam {
0205     u64 mask;
0206     u32 rplc[8];
0207     u32 idx;
0208     u32 cls_lo;
0209     u32 cls_hi;
0210     u32 rplc_size;
0211     u32 vniy;
0212     u32 vnix;
0213     u32 dip_hit;
0214     u32 vlan_vld;
0215     u32 repli;
0216     u16 ivlan;
0217     u8 addr[ETH_ALEN];
0218     u8 lookup_type;
0219     u8 port_num;
0220     u8 reserved[2];
0221 };
0222
0223 #define CUDBG_VPD_VER_ADDR 0x18c7
0224 #define CUDBG_VPD_VER_LEN 2
0225
0226 struct cudbg_vpd_data {
0227     u8 sn[SERNUM_LEN + 1];
0228     u8 bn[PN_LEN + 1];
0229     u8 na[MACADDR_LEN + 1];
0230     u8 mn[ID_LEN + 1];
0231     u16 fw_major;
0232     u16 fw_minor;
0233     u16 fw_micro;
0234     u16 fw_build;
0235     u32 scfg_vers;
0236     u32 vpd_vers;
0237 };
0238
0239 #define CUDBG_MAX_TCAM_TID 0x800
0240 #define CUDBG_T6_CLIP 1536
0241 #define CUDBG_MAX_TID_COMP_EN 6144
0242 #define CUDBG_MAX_TID_COMP_DIS 3072
0243
0244 enum cudbg_le_entry_types {
0245     LE_ET_UNKNOWN = 0,
0246     LE_ET_TCAM_CON = 1,
0247     LE_ET_TCAM_SERVER = 2,
0248     LE_ET_TCAM_FILTER = 3,
0249     LE_ET_TCAM_CLIP = 4,
0250     LE_ET_TCAM_ROUTING = 5,
0251     LE_ET_HASH_CON = 6,
0252     LE_ET_INVALID_TID = 8,
0253 };
0254
0255 struct cudbg_tcam {
0256     u32 filter_start;
0257     u32 server_start;
0258     u32 clip_start;
0259     u32 routing_start;
0260     u32 tid_hash_base;
0261     u32 max_tid;
0262 };
0263
0264 struct cudbg_tid_data {
0265     u32 tid;
0266     u32 dbig_cmd;
0267     u32 dbig_conf;
0268     u32 dbig_rsp_stat;
0269     u32 data[NUM_LE_DB_DBGI_RSP_DATA_INSTANCES];
0270 };
0271
0272 #define CUDBG_NUM_ULPTX 11
0273 #define CUDBG_NUM_ULPTX_READ 512
0274 #define CUDBG_NUM_ULPTX_ASIC 6
0275 #define CUDBG_NUM_ULPTX_ASIC_READ 128
0276
0277 #define CUDBG_ULPTX_LA_REV 1
0278
0279 struct cudbg_ulptx_la {
0280     u32 rdptr[CUDBG_NUM_ULPTX];
0281     u32 wrptr[CUDBG_NUM_ULPTX];
0282     u32 rddata[CUDBG_NUM_ULPTX];
0283     u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
0284     u32 rdptr_asic[CUDBG_NUM_ULPTX_ASIC_READ];
0285     u32 rddata_asic[CUDBG_NUM_ULPTX_ASIC_READ][CUDBG_NUM_ULPTX_ASIC];
0286 };
0287
0288 #define CUDBG_CHAC_PBT_ADDR 0x2800
0289 #define CUDBG_CHAC_PBT_LRF  0x3000
0290 #define CUDBG_CHAC_PBT_DATA 0x3800
0291 #define CUDBG_PBT_DYNAMIC_ENTRIES 8
0292 #define CUDBG_PBT_STATIC_ENTRIES 16
0293 #define CUDBG_LRF_ENTRIES 8
0294 #define CUDBG_PBT_DATA_ENTRIES 512
0295
0296 struct cudbg_pbt_tables {
0297     u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
0298     u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
0299     u32 lrf_table[CUDBG_LRF_ENTRIES];
0300     u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
0301 };
0302
0303 enum cudbg_qdesc_qtype {
0304     CUDBG_QTYPE_UNKNOWN = 0,
0305     CUDBG_QTYPE_NIC_TXQ,
0306     CUDBG_QTYPE_NIC_RXQ,
0307     CUDBG_QTYPE_NIC_FLQ,
0308     CUDBG_QTYPE_CTRLQ,
0309     CUDBG_QTYPE_FWEVTQ,
0310     CUDBG_QTYPE_INTRQ,
0311     CUDBG_QTYPE_PTP_TXQ,
0312     CUDBG_QTYPE_OFLD_TXQ,
0313     CUDBG_QTYPE_RDMA_RXQ,
0314     CUDBG_QTYPE_RDMA_FLQ,
0315     CUDBG_QTYPE_RDMA_CIQ,
0316     CUDBG_QTYPE_ISCSI_RXQ,
0317     CUDBG_QTYPE_ISCSI_FLQ,
0318     CUDBG_QTYPE_ISCSIT_RXQ,
0319     CUDBG_QTYPE_ISCSIT_FLQ,
0320     CUDBG_QTYPE_CRYPTO_TXQ,
0321     CUDBG_QTYPE_CRYPTO_RXQ,
0322     CUDBG_QTYPE_CRYPTO_FLQ,
0323     CUDBG_QTYPE_TLS_RXQ,
0324     CUDBG_QTYPE_TLS_FLQ,
0325     CUDBG_QTYPE_ETHOFLD_TXQ,
0326     CUDBG_QTYPE_ETHOFLD_RXQ,
0327     CUDBG_QTYPE_ETHOFLD_FLQ,
0328     CUDBG_QTYPE_MAX,
0329 };
0330
0331 #define CUDBG_QDESC_REV 1
0332
0333 struct cudbg_qdesc_entry {
0334     u32 data_size;
0335     u32 qtype;
0336     u32 qid;
0337     u32 desc_size;
0338     u32 num_desc;
0339     u8 data[]; /* Must be last */
0340 };
0341
0342 struct cudbg_qdesc_info {
0343     u32 qdesc_entry_size;
0344     u32 num_queues;
0345     u8 data[]; /* Must be last */
0346 };
0347
0348 #define IREG_NUM_ELEM 4
0349
0350 #define CUDBG_NUM_PCIE_CONFIG_REGS 0x61
0351
0352 #endif /* __CUDBG_ENTITY_H__ */