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0001 /*
0002  * Copyright (c) 2004-2008 Chelsio, Inc. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032 #ifndef T3_CPL_H
0033 #define T3_CPL_H
0034 
0035 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
0036 # include <asm/byteorder.h>
0037 #endif
0038 
0039 enum CPL_opcode {
0040     CPL_PASS_OPEN_REQ = 0x1,
0041     CPL_PASS_ACCEPT_RPL = 0x2,
0042     CPL_ACT_OPEN_REQ = 0x3,
0043     CPL_SET_TCB = 0x4,
0044     CPL_SET_TCB_FIELD = 0x5,
0045     CPL_GET_TCB = 0x6,
0046     CPL_PCMD = 0x7,
0047     CPL_CLOSE_CON_REQ = 0x8,
0048     CPL_CLOSE_LISTSRV_REQ = 0x9,
0049     CPL_ABORT_REQ = 0xA,
0050     CPL_ABORT_RPL = 0xB,
0051     CPL_TX_DATA = 0xC,
0052     CPL_RX_DATA_ACK = 0xD,
0053     CPL_TX_PKT = 0xE,
0054     CPL_RTE_DELETE_REQ = 0xF,
0055     CPL_RTE_WRITE_REQ = 0x10,
0056     CPL_RTE_READ_REQ = 0x11,
0057     CPL_L2T_WRITE_REQ = 0x12,
0058     CPL_L2T_READ_REQ = 0x13,
0059     CPL_SMT_WRITE_REQ = 0x14,
0060     CPL_SMT_READ_REQ = 0x15,
0061     CPL_TX_PKT_LSO = 0x16,
0062     CPL_PCMD_READ = 0x17,
0063     CPL_BARRIER = 0x18,
0064     CPL_TID_RELEASE = 0x1A,
0065 
0066     CPL_CLOSE_LISTSRV_RPL = 0x20,
0067     CPL_ERROR = 0x21,
0068     CPL_GET_TCB_RPL = 0x22,
0069     CPL_L2T_WRITE_RPL = 0x23,
0070     CPL_PCMD_READ_RPL = 0x24,
0071     CPL_PCMD_RPL = 0x25,
0072     CPL_PEER_CLOSE = 0x26,
0073     CPL_RTE_DELETE_RPL = 0x27,
0074     CPL_RTE_WRITE_RPL = 0x28,
0075     CPL_RX_DDP_COMPLETE = 0x29,
0076     CPL_RX_PHYS_ADDR = 0x2A,
0077     CPL_RX_PKT = 0x2B,
0078     CPL_RX_URG_NOTIFY = 0x2C,
0079     CPL_SET_TCB_RPL = 0x2D,
0080     CPL_SMT_WRITE_RPL = 0x2E,
0081     CPL_TX_DATA_ACK = 0x2F,
0082 
0083     CPL_ABORT_REQ_RSS = 0x30,
0084     CPL_ABORT_RPL_RSS = 0x31,
0085     CPL_CLOSE_CON_RPL = 0x32,
0086     CPL_ISCSI_HDR = 0x33,
0087     CPL_L2T_READ_RPL = 0x34,
0088     CPL_RDMA_CQE = 0x35,
0089     CPL_RDMA_CQE_READ_RSP = 0x36,
0090     CPL_RDMA_CQE_ERR = 0x37,
0091     CPL_RTE_READ_RPL = 0x38,
0092     CPL_RX_DATA = 0x39,
0093 
0094     CPL_ACT_OPEN_RPL = 0x40,
0095     CPL_PASS_OPEN_RPL = 0x41,
0096     CPL_RX_DATA_DDP = 0x42,
0097     CPL_SMT_READ_RPL = 0x43,
0098 
0099     CPL_ACT_ESTABLISH = 0x50,
0100     CPL_PASS_ESTABLISH = 0x51,
0101 
0102     CPL_PASS_ACCEPT_REQ = 0x70,
0103 
0104     CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */
0105 
0106     CPL_TX_DMA_ACK = 0xA0,
0107     CPL_RDMA_READ_REQ = 0xA1,
0108     CPL_RDMA_TERMINATE = 0xA2,
0109     CPL_TRACE_PKT = 0xA3,
0110     CPL_RDMA_EC_STATUS = 0xA5,
0111 
0112     NUM_CPL_CMDS        /* must be last and previous entries must be sorted */
0113 };
0114 
0115 enum CPL_error {
0116     CPL_ERR_NONE = 0,
0117     CPL_ERR_TCAM_PARITY = 1,
0118     CPL_ERR_TCAM_FULL = 3,
0119     CPL_ERR_CONN_RESET = 20,
0120     CPL_ERR_CONN_EXIST = 22,
0121     CPL_ERR_ARP_MISS = 23,
0122     CPL_ERR_BAD_SYN = 24,
0123     CPL_ERR_CONN_TIMEDOUT = 30,
0124     CPL_ERR_XMIT_TIMEDOUT = 31,
0125     CPL_ERR_PERSIST_TIMEDOUT = 32,
0126     CPL_ERR_FINWAIT2_TIMEDOUT = 33,
0127     CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
0128     CPL_ERR_RTX_NEG_ADVICE = 35,
0129     CPL_ERR_PERSIST_NEG_ADVICE = 36,
0130     CPL_ERR_ABORT_FAILED = 42,
0131     CPL_ERR_GENERAL = 99
0132 };
0133 
0134 enum {
0135     CPL_CONN_POLICY_AUTO = 0,
0136     CPL_CONN_POLICY_ASK = 1,
0137     CPL_CONN_POLICY_DENY = 3
0138 };
0139 
0140 enum {
0141     ULP_MODE_NONE = 0,
0142     ULP_MODE_ISCSI = 2,
0143     ULP_MODE_RDMA = 4,
0144     ULP_MODE_TCPDDP = 5
0145 };
0146 
0147 enum {
0148     ULP_CRC_HEADER = 1 << 0,
0149     ULP_CRC_DATA = 1 << 1
0150 };
0151 
0152 enum {
0153     CPL_PASS_OPEN_ACCEPT,
0154     CPL_PASS_OPEN_REJECT
0155 };
0156 
0157 enum {
0158     CPL_ABORT_SEND_RST = 0,
0159     CPL_ABORT_NO_RST,
0160     CPL_ABORT_POST_CLOSE_REQ = 2
0161 };
0162 
0163 enum {              /* TX_PKT_LSO ethernet types */
0164     CPL_ETH_II,
0165     CPL_ETH_II_VLAN,
0166     CPL_ETH_802_3,
0167     CPL_ETH_802_3_VLAN
0168 };
0169 
0170 enum {              /* TCP congestion control algorithms */
0171     CONG_ALG_RENO,
0172     CONG_ALG_TAHOE,
0173     CONG_ALG_NEWRENO,
0174     CONG_ALG_HIGHSPEED
0175 };
0176 
0177 enum {          /* RSS hash type */
0178     RSS_HASH_NONE = 0,
0179     RSS_HASH_2_TUPLE = 1,
0180     RSS_HASH_4_TUPLE = 2,
0181     RSS_HASH_TCPV6 = 3
0182 };
0183 
0184 union opcode_tid {
0185     __be32 opcode_tid;
0186     __u8 opcode;
0187 };
0188 
0189 #define S_OPCODE 24
0190 #define V_OPCODE(x) ((x) << S_OPCODE)
0191 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
0192 #define G_TID(x)    ((x) & 0xFFFFFF)
0193 
0194 #define S_QNUM 0
0195 #define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF)
0196 
0197 #define S_HASHTYPE 22
0198 #define M_HASHTYPE 0x3
0199 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
0200 
0201 /* tid is assumed to be 24-bits */
0202 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
0203 
0204 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
0205 
0206 /* extract the TID from a CPL command */
0207 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
0208 
0209 struct tcp_options {
0210     __be16 mss;
0211     __u8 wsf;
0212 #if defined(__LITTLE_ENDIAN_BITFIELD)
0213      __u8:5;
0214     __u8 ecn:1;
0215     __u8 sack:1;
0216     __u8 tstamp:1;
0217 #else
0218     __u8 tstamp:1;
0219     __u8 sack:1;
0220     __u8 ecn:1;
0221      __u8:5;
0222 #endif
0223 };
0224 
0225 struct rss_header {
0226     __u8 opcode;
0227 #if defined(__LITTLE_ENDIAN_BITFIELD)
0228     __u8 cpu_idx:6;
0229     __u8 hash_type:2;
0230 #else
0231     __u8 hash_type:2;
0232     __u8 cpu_idx:6;
0233 #endif
0234     __be16 cq_idx;
0235     __be32 rss_hash_val;
0236 };
0237 
0238 #ifndef CHELSIO_FW
0239 struct work_request_hdr {
0240     __be32 wr_hi;
0241     __be32 wr_lo;
0242 };
0243 
0244 /* wr_hi fields */
0245 #define S_WR_SGE_CREDITS    0
0246 #define M_WR_SGE_CREDITS    0xFF
0247 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
0248 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
0249 
0250 #define S_WR_SGLSFLT    8
0251 #define M_WR_SGLSFLT    0xFF
0252 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
0253 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
0254 
0255 #define S_WR_BCNTLFLT    16
0256 #define M_WR_BCNTLFLT    0xF
0257 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
0258 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
0259 
0260 #define S_WR_DATATYPE    20
0261 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
0262 #define F_WR_DATATYPE    V_WR_DATATYPE(1U)
0263 
0264 #define S_WR_COMPL    21
0265 #define V_WR_COMPL(x) ((x) << S_WR_COMPL)
0266 #define F_WR_COMPL    V_WR_COMPL(1U)
0267 
0268 #define S_WR_EOP    22
0269 #define V_WR_EOP(x) ((x) << S_WR_EOP)
0270 #define F_WR_EOP    V_WR_EOP(1U)
0271 
0272 #define S_WR_SOP    23
0273 #define V_WR_SOP(x) ((x) << S_WR_SOP)
0274 #define F_WR_SOP    V_WR_SOP(1U)
0275 
0276 #define S_WR_OP    24
0277 #define M_WR_OP    0xFF
0278 #define V_WR_OP(x) ((x) << S_WR_OP)
0279 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
0280 
0281 /* wr_lo fields */
0282 #define S_WR_LEN    0
0283 #define M_WR_LEN    0xFF
0284 #define V_WR_LEN(x) ((x) << S_WR_LEN)
0285 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
0286 
0287 #define S_WR_TID    8
0288 #define M_WR_TID    0xFFFFF
0289 #define V_WR_TID(x) ((x) << S_WR_TID)
0290 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
0291 
0292 #define S_WR_CR_FLUSH    30
0293 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
0294 #define F_WR_CR_FLUSH    V_WR_CR_FLUSH(1U)
0295 
0296 #define S_WR_GEN    31
0297 #define V_WR_GEN(x) ((x) << S_WR_GEN)
0298 #define F_WR_GEN    V_WR_GEN(1U)
0299 
0300 # define WR_HDR struct work_request_hdr wr
0301 # define RSS_HDR
0302 #else
0303 # define WR_HDR
0304 # define RSS_HDR struct rss_header rss_hdr;
0305 #endif
0306 
0307 /* option 0 lower-half fields */
0308 #define S_CPL_STATUS    0
0309 #define M_CPL_STATUS    0xFF
0310 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
0311 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
0312 
0313 #define S_INJECT_TIMER    6
0314 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
0315 #define F_INJECT_TIMER    V_INJECT_TIMER(1U)
0316 
0317 #define S_NO_OFFLOAD    7
0318 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
0319 #define F_NO_OFFLOAD    V_NO_OFFLOAD(1U)
0320 
0321 #define S_ULP_MODE    8
0322 #define M_ULP_MODE    0xF
0323 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
0324 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
0325 
0326 #define S_RCV_BUFSIZ    12
0327 #define M_RCV_BUFSIZ    0x3FFF
0328 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
0329 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
0330 
0331 #define S_TOS    26
0332 #define M_TOS    0x3F
0333 #define V_TOS(x) ((x) << S_TOS)
0334 #define G_TOS(x) (((x) >> S_TOS) & M_TOS)
0335 
0336 /* option 0 upper-half fields */
0337 #define S_DELACK    0
0338 #define V_DELACK(x) ((x) << S_DELACK)
0339 #define F_DELACK    V_DELACK(1U)
0340 
0341 #define S_NO_CONG    1
0342 #define V_NO_CONG(x) ((x) << S_NO_CONG)
0343 #define F_NO_CONG    V_NO_CONG(1U)
0344 
0345 #define S_SRC_MAC_SEL    2
0346 #define M_SRC_MAC_SEL    0x3
0347 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
0348 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
0349 
0350 #define S_L2T_IDX    4
0351 #define M_L2T_IDX    0x7FF
0352 #define V_L2T_IDX(x) ((x) << S_L2T_IDX)
0353 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
0354 
0355 #define S_TX_CHANNEL    15
0356 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
0357 #define F_TX_CHANNEL    V_TX_CHANNEL(1U)
0358 
0359 #define S_TCAM_BYPASS    16
0360 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
0361 #define F_TCAM_BYPASS    V_TCAM_BYPASS(1U)
0362 
0363 #define S_NAGLE    17
0364 #define V_NAGLE(x) ((x) << S_NAGLE)
0365 #define F_NAGLE    V_NAGLE(1U)
0366 
0367 #define S_WND_SCALE    18
0368 #define M_WND_SCALE    0xF
0369 #define V_WND_SCALE(x) ((x) << S_WND_SCALE)
0370 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
0371 
0372 #define S_KEEP_ALIVE    22
0373 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
0374 #define F_KEEP_ALIVE    V_KEEP_ALIVE(1U)
0375 
0376 #define S_MAX_RETRANS    23
0377 #define M_MAX_RETRANS    0xF
0378 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
0379 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
0380 
0381 #define S_MAX_RETRANS_OVERRIDE    27
0382 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
0383 #define F_MAX_RETRANS_OVERRIDE    V_MAX_RETRANS_OVERRIDE(1U)
0384 
0385 #define S_MSS_IDX    28
0386 #define M_MSS_IDX    0xF
0387 #define V_MSS_IDX(x) ((x) << S_MSS_IDX)
0388 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
0389 
0390 /* option 1 fields */
0391 #define S_RSS_ENABLE    0
0392 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
0393 #define F_RSS_ENABLE    V_RSS_ENABLE(1U)
0394 
0395 #define S_RSS_MASK_LEN    1
0396 #define M_RSS_MASK_LEN    0x7
0397 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
0398 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
0399 
0400 #define S_CPU_IDX    4
0401 #define M_CPU_IDX    0x3F
0402 #define V_CPU_IDX(x) ((x) << S_CPU_IDX)
0403 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
0404 
0405 #define S_MAC_MATCH_VALID    18
0406 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
0407 #define F_MAC_MATCH_VALID    V_MAC_MATCH_VALID(1U)
0408 
0409 #define S_CONN_POLICY    19
0410 #define M_CONN_POLICY    0x3
0411 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
0412 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
0413 
0414 #define S_SYN_DEFENSE    21
0415 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
0416 #define F_SYN_DEFENSE    V_SYN_DEFENSE(1U)
0417 
0418 #define S_VLAN_PRI    22
0419 #define M_VLAN_PRI    0x3
0420 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
0421 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
0422 
0423 #define S_VLAN_PRI_VALID    24
0424 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
0425 #define F_VLAN_PRI_VALID    V_VLAN_PRI_VALID(1U)
0426 
0427 #define S_PKT_TYPE    25
0428 #define M_PKT_TYPE    0x3
0429 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
0430 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
0431 
0432 #define S_MAC_MATCH    27
0433 #define M_MAC_MATCH    0x1F
0434 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
0435 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
0436 
0437 /* option 2 fields */
0438 #define S_CPU_INDEX    0
0439 #define M_CPU_INDEX    0x7F
0440 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
0441 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
0442 
0443 #define S_CPU_INDEX_VALID    7
0444 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
0445 #define F_CPU_INDEX_VALID    V_CPU_INDEX_VALID(1U)
0446 
0447 #define S_RX_COALESCE    8
0448 #define M_RX_COALESCE    0x3
0449 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
0450 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
0451 
0452 #define S_RX_COALESCE_VALID    10
0453 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
0454 #define F_RX_COALESCE_VALID    V_RX_COALESCE_VALID(1U)
0455 
0456 #define S_CONG_CONTROL_FLAVOR    11
0457 #define M_CONG_CONTROL_FLAVOR    0x3
0458 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
0459 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
0460 
0461 #define S_PACING_FLAVOR    13
0462 #define M_PACING_FLAVOR    0x3
0463 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
0464 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
0465 
0466 #define S_FLAVORS_VALID    15
0467 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
0468 #define F_FLAVORS_VALID    V_FLAVORS_VALID(1U)
0469 
0470 #define S_RX_FC_DISABLE    16
0471 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
0472 #define F_RX_FC_DISABLE    V_RX_FC_DISABLE(1U)
0473 
0474 #define S_RX_FC_VALID    17
0475 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
0476 #define F_RX_FC_VALID    V_RX_FC_VALID(1U)
0477 
0478 struct cpl_pass_open_req {
0479     WR_HDR;
0480     union opcode_tid ot;
0481     __be16 local_port;
0482     __be16 peer_port;
0483     __be32 local_ip;
0484     __be32 peer_ip;
0485     __be32 opt0h;
0486     __be32 opt0l;
0487     __be32 peer_netmask;
0488     __be32 opt1;
0489 };
0490 
0491 struct cpl_pass_open_rpl {
0492     RSS_HDR union opcode_tid ot;
0493     __be16 local_port;
0494     __be16 peer_port;
0495     __be32 local_ip;
0496     __be32 peer_ip;
0497     __u8 resvd[7];
0498     __u8 status;
0499 };
0500 
0501 struct cpl_pass_establish {
0502     RSS_HDR union opcode_tid ot;
0503     __be16 local_port;
0504     __be16 peer_port;
0505     __be32 local_ip;
0506     __be32 peer_ip;
0507     __be32 tos_tid;
0508     __be16 l2t_idx;
0509     __be16 tcp_opt;
0510     __be32 snd_isn;
0511     __be32 rcv_isn;
0512 };
0513 
0514 /* cpl_pass_establish.tos_tid fields */
0515 #define S_PASS_OPEN_TID    0
0516 #define M_PASS_OPEN_TID    0xFFFFFF
0517 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
0518 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
0519 
0520 #define S_PASS_OPEN_TOS    24
0521 #define M_PASS_OPEN_TOS    0xFF
0522 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
0523 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
0524 
0525 /* cpl_pass_establish.l2t_idx fields */
0526 #define S_L2T_IDX16    5
0527 #define M_L2T_IDX16    0x7FF
0528 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
0529 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
0530 
0531 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
0532 #define G_TCPOPT_WSCALE_OK(x)  (((x) >> 5) & 1)
0533 #define G_TCPOPT_SACK(x)       (((x) >> 6) & 1)
0534 #define G_TCPOPT_TSTAMP(x)     (((x) >> 7) & 1)
0535 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
0536 #define G_TCPOPT_MSS(x)        (((x) >> 12) & 0xf)
0537 
0538 struct cpl_pass_accept_req {
0539     RSS_HDR union opcode_tid ot;
0540     __be16 local_port;
0541     __be16 peer_port;
0542     __be32 local_ip;
0543     __be32 peer_ip;
0544     __be32 tos_tid;
0545     struct tcp_options tcp_options;
0546     __u8 dst_mac[6];
0547     __be16 vlan_tag;
0548     __u8 src_mac[6];
0549 #if defined(__LITTLE_ENDIAN_BITFIELD)
0550      __u8:3;
0551     __u8 addr_idx:3;
0552     __u8 port_idx:1;
0553     __u8 exact_match:1;
0554 #else
0555     __u8 exact_match:1;
0556     __u8 port_idx:1;
0557     __u8 addr_idx:3;
0558      __u8:3;
0559 #endif
0560     __u8 rsvd;
0561     __be32 rcv_isn;
0562     __be32 rsvd2;
0563 };
0564 
0565 struct cpl_pass_accept_rpl {
0566     WR_HDR;
0567     union opcode_tid ot;
0568     __be32 opt2;
0569     __be32 rsvd;
0570     __be32 peer_ip;
0571     __be32 opt0h;
0572     __be32 opt0l_status;
0573 };
0574 
0575 struct cpl_act_open_req {
0576     WR_HDR;
0577     union opcode_tid ot;
0578     __be16 local_port;
0579     __be16 peer_port;
0580     __be32 local_ip;
0581     __be32 peer_ip;
0582     __be32 opt0h;
0583     __be32 opt0l;
0584     __be32 params;
0585     __be32 opt2;
0586 };
0587 
0588 /* cpl_act_open_req.params fields */
0589 #define S_AOPEN_VLAN_PRI    9
0590 #define M_AOPEN_VLAN_PRI    0x3
0591 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
0592 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
0593 
0594 #define S_AOPEN_VLAN_PRI_VALID    11
0595 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
0596 #define F_AOPEN_VLAN_PRI_VALID    V_AOPEN_VLAN_PRI_VALID(1U)
0597 
0598 #define S_AOPEN_PKT_TYPE    12
0599 #define M_AOPEN_PKT_TYPE    0x3
0600 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
0601 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
0602 
0603 #define S_AOPEN_MAC_MATCH    14
0604 #define M_AOPEN_MAC_MATCH    0x1F
0605 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
0606 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
0607 
0608 #define S_AOPEN_MAC_MATCH_VALID    19
0609 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
0610 #define F_AOPEN_MAC_MATCH_VALID    V_AOPEN_MAC_MATCH_VALID(1U)
0611 
0612 #define S_AOPEN_IFF_VLAN    20
0613 #define M_AOPEN_IFF_VLAN    0xFFF
0614 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
0615 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
0616 
0617 struct cpl_act_open_rpl {
0618     RSS_HDR union opcode_tid ot;
0619     __be16 local_port;
0620     __be16 peer_port;
0621     __be32 local_ip;
0622     __be32 peer_ip;
0623     __be32 atid;
0624     __u8 rsvd[3];
0625     __u8 status;
0626 };
0627 
0628 struct cpl_act_establish {
0629     RSS_HDR union opcode_tid ot;
0630     __be16 local_port;
0631     __be16 peer_port;
0632     __be32 local_ip;
0633     __be32 peer_ip;
0634     __be32 tos_tid;
0635     __be16 l2t_idx;
0636     __be16 tcp_opt;
0637     __be32 snd_isn;
0638     __be32 rcv_isn;
0639 };
0640 
0641 struct cpl_get_tcb {
0642     WR_HDR;
0643     union opcode_tid ot;
0644     __be16 cpuno;
0645     __be16 rsvd;
0646 };
0647 
0648 struct cpl_get_tcb_rpl {
0649     RSS_HDR union opcode_tid ot;
0650     __u8 rsvd;
0651     __u8 status;
0652     __be16 len;
0653 };
0654 
0655 struct cpl_set_tcb {
0656     WR_HDR;
0657     union opcode_tid ot;
0658     __u8 reply;
0659     __u8 cpu_idx;
0660     __be16 len;
0661 };
0662 
0663 /* cpl_set_tcb.reply fields */
0664 #define S_NO_REPLY    7
0665 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
0666 #define F_NO_REPLY    V_NO_REPLY(1U)
0667 
0668 struct cpl_set_tcb_field {
0669     WR_HDR;
0670     union opcode_tid ot;
0671     __u8 reply;
0672     __u8 cpu_idx;
0673     __be16 word;
0674     __be64 mask;
0675     __be64 val;
0676 };
0677 
0678 struct cpl_set_tcb_rpl {
0679     RSS_HDR union opcode_tid ot;
0680     __u8 rsvd[3];
0681     __u8 status;
0682 };
0683 
0684 struct cpl_pcmd {
0685     WR_HDR;
0686     union opcode_tid ot;
0687     __u8 rsvd[3];
0688 #if defined(__LITTLE_ENDIAN_BITFIELD)
0689     __u8 src:1;
0690     __u8 bundle:1;
0691     __u8 channel:1;
0692      __u8:5;
0693 #else
0694      __u8:5;
0695     __u8 channel:1;
0696     __u8 bundle:1;
0697     __u8 src:1;
0698 #endif
0699     __be32 pcmd_parm[2];
0700 };
0701 
0702 struct cpl_pcmd_reply {
0703     RSS_HDR union opcode_tid ot;
0704     __u8 status;
0705     __u8 rsvd;
0706     __be16 len;
0707 };
0708 
0709 struct cpl_close_con_req {
0710     WR_HDR;
0711     union opcode_tid ot;
0712     __be32 rsvd;
0713 };
0714 
0715 struct cpl_close_con_rpl {
0716     RSS_HDR union opcode_tid ot;
0717     __u8 rsvd[3];
0718     __u8 status;
0719     __be32 snd_nxt;
0720     __be32 rcv_nxt;
0721 };
0722 
0723 struct cpl_close_listserv_req {
0724     WR_HDR;
0725     union opcode_tid ot;
0726     __u8 rsvd0;
0727     __u8 cpu_idx;
0728     __be16 rsvd1;
0729 };
0730 
0731 struct cpl_close_listserv_rpl {
0732     RSS_HDR union opcode_tid ot;
0733     __u8 rsvd[3];
0734     __u8 status;
0735 };
0736 
0737 struct cpl_abort_req_rss {
0738     RSS_HDR union opcode_tid ot;
0739     __be32 rsvd0;
0740     __u8 rsvd1;
0741     __u8 status;
0742     __u8 rsvd2[6];
0743 };
0744 
0745 struct cpl_abort_req {
0746     WR_HDR;
0747     union opcode_tid ot;
0748     __be32 rsvd0;
0749     __u8 rsvd1;
0750     __u8 cmd;
0751     __u8 rsvd2[6];
0752 };
0753 
0754 struct cpl_abort_rpl_rss {
0755     RSS_HDR union opcode_tid ot;
0756     __be32 rsvd0;
0757     __u8 rsvd1;
0758     __u8 status;
0759     __u8 rsvd2[6];
0760 };
0761 
0762 struct cpl_abort_rpl {
0763     WR_HDR;
0764     union opcode_tid ot;
0765     __be32 rsvd0;
0766     __u8 rsvd1;
0767     __u8 cmd;
0768     __u8 rsvd2[6];
0769 };
0770 
0771 struct cpl_peer_close {
0772     RSS_HDR union opcode_tid ot;
0773     __be32 rcv_nxt;
0774 };
0775 
0776 struct tx_data_wr {
0777     __be32 wr_hi;
0778     __be32 wr_lo;
0779     __be32 len;
0780     __be32 flags;
0781     __be32 sndseq;
0782     __be32 param;
0783 };
0784 
0785 /* tx_data_wr.flags fields */
0786 #define S_TX_ACK_PAGES  21
0787 #define M_TX_ACK_PAGES  0x7
0788 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
0789 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
0790 
0791 /* tx_data_wr.param fields */
0792 #define S_TX_PORT    0
0793 #define M_TX_PORT    0x7
0794 #define V_TX_PORT(x) ((x) << S_TX_PORT)
0795 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
0796 
0797 #define S_TX_MSS    4
0798 #define M_TX_MSS    0xF
0799 #define V_TX_MSS(x) ((x) << S_TX_MSS)
0800 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
0801 
0802 #define S_TX_QOS    8
0803 #define M_TX_QOS    0xFF
0804 #define V_TX_QOS(x) ((x) << S_TX_QOS)
0805 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
0806 
0807 #define S_TX_SNDBUF 16
0808 #define M_TX_SNDBUF 0xFFFF
0809 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
0810 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
0811 
0812 struct cpl_tx_data {
0813     union opcode_tid ot;
0814     __be32 len;
0815     __be32 rsvd;
0816     __be16 urg;
0817     __be16 flags;
0818 };
0819 
0820 /* cpl_tx_data.flags fields */
0821 #define S_TX_ULP_SUBMODE    6
0822 #define M_TX_ULP_SUBMODE    0xF
0823 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
0824 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
0825 
0826 #define S_TX_ULP_MODE    10
0827 #define M_TX_ULP_MODE    0xF
0828 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
0829 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
0830 
0831 #define S_TX_SHOVE    14
0832 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
0833 #define F_TX_SHOVE    V_TX_SHOVE(1U)
0834 
0835 #define S_TX_MORE    15
0836 #define V_TX_MORE(x) ((x) << S_TX_MORE)
0837 #define F_TX_MORE    V_TX_MORE(1U)
0838 
0839 /* additional tx_data_wr.flags fields */
0840 #define S_TX_CPU_IDX    0
0841 #define M_TX_CPU_IDX    0x3F
0842 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
0843 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
0844 
0845 #define S_TX_URG    16
0846 #define V_TX_URG(x) ((x) << S_TX_URG)
0847 #define F_TX_URG    V_TX_URG(1U)
0848 
0849 #define S_TX_CLOSE    17
0850 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
0851 #define F_TX_CLOSE    V_TX_CLOSE(1U)
0852 
0853 #define S_TX_INIT    18
0854 #define V_TX_INIT(x) ((x) << S_TX_INIT)
0855 #define F_TX_INIT    V_TX_INIT(1U)
0856 
0857 #define S_TX_IMM_ACK    19
0858 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
0859 #define F_TX_IMM_ACK    V_TX_IMM_ACK(1U)
0860 
0861 #define S_TX_IMM_DMA    20
0862 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
0863 #define F_TX_IMM_DMA    V_TX_IMM_DMA(1U)
0864 
0865 struct cpl_tx_data_ack {
0866     RSS_HDR union opcode_tid ot;
0867     __be32 ack_seq;
0868 };
0869 
0870 struct cpl_wr_ack {
0871     RSS_HDR union opcode_tid ot;
0872     __be16 credits;
0873     __be16 rsvd;
0874     __be32 snd_nxt;
0875     __be32 snd_una;
0876 };
0877 
0878 struct cpl_rdma_ec_status {
0879     RSS_HDR union opcode_tid ot;
0880     __u8 rsvd[3];
0881     __u8 status;
0882 };
0883 
0884 struct mngt_pktsched_wr {
0885     __be32 wr_hi;
0886     __be32 wr_lo;
0887     __u8 mngt_opcode;
0888     __u8 rsvd[7];
0889     __u8 sched;
0890     __u8 idx;
0891     __u8 min;
0892     __u8 max;
0893     __u8 binding;
0894     __u8 rsvd1[3];
0895 };
0896 
0897 struct cpl_iscsi_hdr {
0898     RSS_HDR union opcode_tid ot;
0899     __be16 pdu_len_ddp;
0900     __be16 len;
0901     __be32 seq;
0902     __be16 urg;
0903     __u8 rsvd;
0904     __u8 status;
0905 };
0906 
0907 /* cpl_iscsi_hdr.pdu_len_ddp fields */
0908 #define S_ISCSI_PDU_LEN    0
0909 #define M_ISCSI_PDU_LEN    0x7FFF
0910 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
0911 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
0912 
0913 #define S_ISCSI_DDP    15
0914 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
0915 #define F_ISCSI_DDP    V_ISCSI_DDP(1U)
0916 
0917 struct cpl_rx_data {
0918     RSS_HDR union opcode_tid ot;
0919     __be16 rsvd;
0920     __be16 len;
0921     __be32 seq;
0922     __be16 urg;
0923 #if defined(__LITTLE_ENDIAN_BITFIELD)
0924     __u8 dack_mode:2;
0925     __u8 psh:1;
0926     __u8 heartbeat:1;
0927      __u8:4;
0928 #else
0929      __u8:4;
0930     __u8 heartbeat:1;
0931     __u8 psh:1;
0932     __u8 dack_mode:2;
0933 #endif
0934     __u8 status;
0935 };
0936 
0937 struct cpl_rx_data_ack {
0938     WR_HDR;
0939     union opcode_tid ot;
0940     __be32 credit_dack;
0941 };
0942 
0943 /* cpl_rx_data_ack.ack_seq fields */
0944 #define S_RX_CREDITS    0
0945 #define M_RX_CREDITS    0x7FFFFFF
0946 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
0947 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
0948 
0949 #define S_RX_MODULATE    27
0950 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
0951 #define F_RX_MODULATE    V_RX_MODULATE(1U)
0952 
0953 #define S_RX_FORCE_ACK    28
0954 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
0955 #define F_RX_FORCE_ACK    V_RX_FORCE_ACK(1U)
0956 
0957 #define S_RX_DACK_MODE    29
0958 #define M_RX_DACK_MODE    0x3
0959 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
0960 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
0961 
0962 #define S_RX_DACK_CHANGE    31
0963 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
0964 #define F_RX_DACK_CHANGE    V_RX_DACK_CHANGE(1U)
0965 
0966 struct cpl_rx_urg_notify {
0967     RSS_HDR union opcode_tid ot;
0968     __be32 seq;
0969 };
0970 
0971 struct cpl_rx_ddp_complete {
0972     RSS_HDR union opcode_tid ot;
0973     __be32 ddp_report;
0974 };
0975 
0976 struct cpl_rx_data_ddp {
0977     RSS_HDR union opcode_tid ot;
0978     __be16 urg;
0979     __be16 len;
0980     __be32 seq;
0981     union {
0982         __be32 nxt_seq;
0983         __be32 ddp_report;
0984     };
0985     __be32 ulp_crc;
0986     __be32 ddpvld_status;
0987 };
0988 
0989 /* cpl_rx_data_ddp.ddpvld_status fields */
0990 #define S_DDP_STATUS    0
0991 #define M_DDP_STATUS    0xFF
0992 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
0993 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
0994 
0995 #define S_DDP_VALID    15
0996 #define M_DDP_VALID    0x1FFFF
0997 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
0998 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
0999 
1000 #define S_DDP_PPOD_MISMATCH    15
1001 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1002 #define F_DDP_PPOD_MISMATCH    V_DDP_PPOD_MISMATCH(1U)
1003 
1004 #define S_DDP_PDU    16
1005 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1006 #define F_DDP_PDU    V_DDP_PDU(1U)
1007 
1008 #define S_DDP_LLIMIT_ERR    17
1009 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1010 #define F_DDP_LLIMIT_ERR    V_DDP_LLIMIT_ERR(1U)
1011 
1012 #define S_DDP_PPOD_PARITY_ERR    18
1013 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1014 #define F_DDP_PPOD_PARITY_ERR    V_DDP_PPOD_PARITY_ERR(1U)
1015 
1016 #define S_DDP_PADDING_ERR    19
1017 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1018 #define F_DDP_PADDING_ERR    V_DDP_PADDING_ERR(1U)
1019 
1020 #define S_DDP_HDRCRC_ERR    20
1021 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1022 #define F_DDP_HDRCRC_ERR    V_DDP_HDRCRC_ERR(1U)
1023 
1024 #define S_DDP_DATACRC_ERR    21
1025 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1026 #define F_DDP_DATACRC_ERR    V_DDP_DATACRC_ERR(1U)
1027 
1028 #define S_DDP_INVALID_TAG    22
1029 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1030 #define F_DDP_INVALID_TAG    V_DDP_INVALID_TAG(1U)
1031 
1032 #define S_DDP_ULIMIT_ERR    23
1033 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1034 #define F_DDP_ULIMIT_ERR    V_DDP_ULIMIT_ERR(1U)
1035 
1036 #define S_DDP_OFFSET_ERR    24
1037 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1038 #define F_DDP_OFFSET_ERR    V_DDP_OFFSET_ERR(1U)
1039 
1040 #define S_DDP_COLOR_ERR    25
1041 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1042 #define F_DDP_COLOR_ERR    V_DDP_COLOR_ERR(1U)
1043 
1044 #define S_DDP_TID_MISMATCH    26
1045 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1046 #define F_DDP_TID_MISMATCH    V_DDP_TID_MISMATCH(1U)
1047 
1048 #define S_DDP_INVALID_PPOD    27
1049 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1050 #define F_DDP_INVALID_PPOD    V_DDP_INVALID_PPOD(1U)
1051 
1052 #define S_DDP_ULP_MODE    28
1053 #define M_DDP_ULP_MODE    0xF
1054 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1055 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1056 
1057 /* cpl_rx_data_ddp.ddp_report fields */
1058 #define S_DDP_OFFSET    0
1059 #define M_DDP_OFFSET    0x3FFFFF
1060 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1061 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1062 
1063 #define S_DDP_URG    24
1064 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1065 #define F_DDP_URG    V_DDP_URG(1U)
1066 
1067 #define S_DDP_PSH    25
1068 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1069 #define F_DDP_PSH    V_DDP_PSH(1U)
1070 
1071 #define S_DDP_BUF_COMPLETE    26
1072 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1073 #define F_DDP_BUF_COMPLETE    V_DDP_BUF_COMPLETE(1U)
1074 
1075 #define S_DDP_BUF_TIMED_OUT    27
1076 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1077 #define F_DDP_BUF_TIMED_OUT    V_DDP_BUF_TIMED_OUT(1U)
1078 
1079 #define S_DDP_BUF_IDX    28
1080 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1081 #define F_DDP_BUF_IDX    V_DDP_BUF_IDX(1U)
1082 
1083 struct cpl_tx_pkt {
1084     WR_HDR;
1085     __be32 cntrl;
1086     __be32 len;
1087 };
1088 
1089 struct cpl_tx_pkt_lso {
1090     WR_HDR;
1091     __be32 cntrl;
1092     __be32 len;
1093 
1094     __be32 rsvd;
1095     __be32 lso_info;
1096 };
1097 
1098 /* cpl_tx_pkt*.cntrl fields */
1099 #define S_TXPKT_VLAN    0
1100 #define M_TXPKT_VLAN    0xFFFF
1101 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1102 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1103 
1104 #define S_TXPKT_INTF    16
1105 #define M_TXPKT_INTF    0xF
1106 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1107 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1108 
1109 #define S_TXPKT_IPCSUM_DIS    20
1110 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1111 #define F_TXPKT_IPCSUM_DIS    V_TXPKT_IPCSUM_DIS(1U)
1112 
1113 #define S_TXPKT_L4CSUM_DIS    21
1114 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1115 #define F_TXPKT_L4CSUM_DIS    V_TXPKT_L4CSUM_DIS(1U)
1116 
1117 #define S_TXPKT_VLAN_VLD    22
1118 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1119 #define F_TXPKT_VLAN_VLD    V_TXPKT_VLAN_VLD(1U)
1120 
1121 #define S_TXPKT_LOOPBACK    23
1122 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1123 #define F_TXPKT_LOOPBACK    V_TXPKT_LOOPBACK(1U)
1124 
1125 #define S_TXPKT_OPCODE    24
1126 #define M_TXPKT_OPCODE    0xFF
1127 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1128 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1129 
1130 /* cpl_tx_pkt_lso.lso_info fields */
1131 #define S_LSO_MSS    0
1132 #define M_LSO_MSS    0x3FFF
1133 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1134 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1135 
1136 #define S_LSO_ETH_TYPE    14
1137 #define M_LSO_ETH_TYPE    0x3
1138 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1139 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1140 
1141 #define S_LSO_TCPHDR_WORDS    16
1142 #define M_LSO_TCPHDR_WORDS    0xF
1143 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1144 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1145 
1146 #define S_LSO_IPHDR_WORDS    20
1147 #define M_LSO_IPHDR_WORDS    0xF
1148 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1149 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1150 
1151 #define S_LSO_IPV6    24
1152 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1153 #define F_LSO_IPV6    V_LSO_IPV6(1U)
1154 
1155 struct cpl_trace_pkt {
1156 #ifdef CHELSIO_FW
1157     __u8 rss_opcode;
1158 #if defined(__LITTLE_ENDIAN_BITFIELD)
1159     __u8 err:1;
1160      __u8:7;
1161 #else
1162      __u8:7;
1163     __u8 err:1;
1164 #endif
1165     __u8 rsvd0;
1166 #if defined(__LITTLE_ENDIAN_BITFIELD)
1167     __u8 qid:4;
1168      __u8:4;
1169 #else
1170      __u8:4;
1171     __u8 qid:4;
1172 #endif
1173     __be32 tstamp;
1174 #endif              /* CHELSIO_FW */
1175 
1176     __u8 opcode;
1177 #if defined(__LITTLE_ENDIAN_BITFIELD)
1178     __u8 iff:4;
1179      __u8:4;
1180 #else
1181      __u8:4;
1182     __u8 iff:4;
1183 #endif
1184     __u8 rsvd[4];
1185     __be16 len;
1186 };
1187 
1188 struct cpl_rx_pkt {
1189     RSS_HDR __u8 opcode;
1190 #if defined(__LITTLE_ENDIAN_BITFIELD)
1191     __u8 iff:4;
1192     __u8 csum_valid:1;
1193     __u8 ipmi_pkt:1;
1194     __u8 vlan_valid:1;
1195     __u8 fragment:1;
1196 #else
1197     __u8 fragment:1;
1198     __u8 vlan_valid:1;
1199     __u8 ipmi_pkt:1;
1200     __u8 csum_valid:1;
1201     __u8 iff:4;
1202 #endif
1203     __be16 csum;
1204     __be16 vlan;
1205     __be16 len;
1206 };
1207 
1208 struct cpl_l2t_write_req {
1209     WR_HDR;
1210     union opcode_tid ot;
1211     __be32 params;
1212     __u8 rsvd[2];
1213     __u8 dst_mac[6];
1214 };
1215 
1216 /* cpl_l2t_write_req.params fields */
1217 #define S_L2T_W_IDX    0
1218 #define M_L2T_W_IDX    0x7FF
1219 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1220 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1221 
1222 #define S_L2T_W_VLAN    11
1223 #define M_L2T_W_VLAN    0xFFF
1224 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1225 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1226 
1227 #define S_L2T_W_IFF    23
1228 #define M_L2T_W_IFF    0xF
1229 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1230 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1231 
1232 #define S_L2T_W_PRIO    27
1233 #define M_L2T_W_PRIO    0x7
1234 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1235 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1236 
1237 struct cpl_l2t_write_rpl {
1238     RSS_HDR union opcode_tid ot;
1239     __u8 status;
1240     __u8 rsvd[3];
1241 };
1242 
1243 struct cpl_l2t_read_req {
1244     WR_HDR;
1245     union opcode_tid ot;
1246     __be16 rsvd;
1247     __be16 l2t_idx;
1248 };
1249 
1250 struct cpl_l2t_read_rpl {
1251     RSS_HDR union opcode_tid ot;
1252     __be32 params;
1253     __u8 rsvd[2];
1254     __u8 dst_mac[6];
1255 };
1256 
1257 /* cpl_l2t_read_rpl.params fields */
1258 #define S_L2T_R_PRIO    0
1259 #define M_L2T_R_PRIO    0x7
1260 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1261 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1262 
1263 #define S_L2T_R_VLAN    8
1264 #define M_L2T_R_VLAN    0xFFF
1265 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1266 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1267 
1268 #define S_L2T_R_IFF    20
1269 #define M_L2T_R_IFF    0xF
1270 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1271 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1272 
1273 #define S_L2T_STATUS    24
1274 #define M_L2T_STATUS    0xFF
1275 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1276 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1277 
1278 struct cpl_smt_write_req {
1279     WR_HDR;
1280     union opcode_tid ot;
1281     __u8 rsvd0;
1282 #if defined(__LITTLE_ENDIAN_BITFIELD)
1283     __u8 mtu_idx:4;
1284     __u8 iff:4;
1285 #else
1286     __u8 iff:4;
1287     __u8 mtu_idx:4;
1288 #endif
1289     __be16 rsvd2;
1290     __be16 rsvd3;
1291     __u8 src_mac1[6];
1292     __be16 rsvd4;
1293     __u8 src_mac0[6];
1294 };
1295 
1296 struct cpl_smt_write_rpl {
1297     RSS_HDR union opcode_tid ot;
1298     __u8 status;
1299     __u8 rsvd[3];
1300 };
1301 
1302 struct cpl_smt_read_req {
1303     WR_HDR;
1304     union opcode_tid ot;
1305     __u8 rsvd0;
1306 #if defined(__LITTLE_ENDIAN_BITFIELD)
1307      __u8:4;
1308     __u8 iff:4;
1309 #else
1310     __u8 iff:4;
1311      __u8:4;
1312 #endif
1313     __be16 rsvd2;
1314 };
1315 
1316 struct cpl_smt_read_rpl {
1317     RSS_HDR union opcode_tid ot;
1318     __u8 status;
1319 #if defined(__LITTLE_ENDIAN_BITFIELD)
1320     __u8 mtu_idx:4;
1321      __u8:4;
1322 #else
1323      __u8:4;
1324     __u8 mtu_idx:4;
1325 #endif
1326     __be16 rsvd2;
1327     __be16 rsvd3;
1328     __u8 src_mac1[6];
1329     __be16 rsvd4;
1330     __u8 src_mac0[6];
1331 };
1332 
1333 struct cpl_rte_delete_req {
1334     WR_HDR;
1335     union opcode_tid ot;
1336     __be32 params;
1337 };
1338 
1339 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
1340 #define S_RTE_REQ_LUT_IX    8
1341 #define M_RTE_REQ_LUT_IX    0x7FF
1342 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1343 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1344 
1345 #define S_RTE_REQ_LUT_BASE    19
1346 #define M_RTE_REQ_LUT_BASE    0x7FF
1347 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1348 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1349 
1350 #define S_RTE_READ_REQ_SELECT    31
1351 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1352 #define F_RTE_READ_REQ_SELECT    V_RTE_READ_REQ_SELECT(1U)
1353 
1354 struct cpl_rte_delete_rpl {
1355     RSS_HDR union opcode_tid ot;
1356     __u8 status;
1357     __u8 rsvd[3];
1358 };
1359 
1360 struct cpl_rte_write_req {
1361     WR_HDR;
1362     union opcode_tid ot;
1363 #if defined(__LITTLE_ENDIAN_BITFIELD)
1364      __u8:6;
1365     __u8 write_tcam:1;
1366     __u8 write_l2t_lut:1;
1367 #else
1368     __u8 write_l2t_lut:1;
1369     __u8 write_tcam:1;
1370      __u8:6;
1371 #endif
1372     __u8 rsvd[3];
1373     __be32 lut_params;
1374     __be16 rsvd2;
1375     __be16 l2t_idx;
1376     __be32 netmask;
1377     __be32 faddr;
1378 };
1379 
1380 /* cpl_rte_write_req.lut_params fields */
1381 #define S_RTE_WRITE_REQ_LUT_IX    10
1382 #define M_RTE_WRITE_REQ_LUT_IX    0x7FF
1383 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1384 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1385 
1386 #define S_RTE_WRITE_REQ_LUT_BASE    21
1387 #define M_RTE_WRITE_REQ_LUT_BASE    0x7FF
1388 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1389 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1390 
1391 struct cpl_rte_write_rpl {
1392     RSS_HDR union opcode_tid ot;
1393     __u8 status;
1394     __u8 rsvd[3];
1395 };
1396 
1397 struct cpl_rte_read_req {
1398     WR_HDR;
1399     union opcode_tid ot;
1400     __be32 params;
1401 };
1402 
1403 struct cpl_rte_read_rpl {
1404     RSS_HDR union opcode_tid ot;
1405     __u8 status;
1406     __u8 rsvd0;
1407     __be16 l2t_idx;
1408 #if defined(__LITTLE_ENDIAN_BITFIELD)
1409      __u8:7;
1410     __u8 select:1;
1411 #else
1412     __u8 select:1;
1413      __u8:7;
1414 #endif
1415     __u8 rsvd2[3];
1416     __be32 addr;
1417 };
1418 
1419 struct cpl_tid_release {
1420     WR_HDR;
1421     union opcode_tid ot;
1422     __be32 rsvd;
1423 };
1424 
1425 struct cpl_barrier {
1426     WR_HDR;
1427     __u8 opcode;
1428     __u8 rsvd[7];
1429 };
1430 
1431 struct cpl_rdma_read_req {
1432     __u8 opcode;
1433     __u8 rsvd[15];
1434 };
1435 
1436 struct cpl_rdma_terminate {
1437 #ifdef CHELSIO_FW
1438     __u8 opcode;
1439     __u8 rsvd[2];
1440 #if defined(__LITTLE_ENDIAN_BITFIELD)
1441     __u8 rspq:3;
1442      __u8:5;
1443 #else
1444      __u8:5;
1445     __u8 rspq:3;
1446 #endif
1447     __be32 tid_len;
1448 #endif
1449     __be32 msn;
1450     __be32 mo;
1451     __u8 data[];
1452 };
1453 
1454 /* cpl_rdma_terminate.tid_len fields */
1455 #define S_FLIT_CNT    0
1456 #define M_FLIT_CNT    0xFF
1457 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1458 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1459 
1460 #define S_TERM_TID    8
1461 #define M_TERM_TID    0xFFFFF
1462 #define V_TERM_TID(x) ((x) << S_TERM_TID)
1463 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1464 
1465 /* ULP_TX opcodes */
1466 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
1467 
1468 #define S_ULPTX_CMD 28
1469 #define M_ULPTX_CMD 0xF
1470 #define V_ULPTX_CMD(x)  ((x) << S_ULPTX_CMD)
1471 
1472 #define S_ULPTX_NFLITS  0
1473 #define M_ULPTX_NFLITS  0xFF
1474 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1475 
1476 struct ulp_mem_io {
1477     WR_HDR;
1478     __be32 cmd_lock_addr;
1479     __be32 len;
1480 };
1481 
1482 /* ulp_mem_io.cmd_lock_addr fields */
1483 #define S_ULP_MEMIO_ADDR    0
1484 #define M_ULP_MEMIO_ADDR    0x7FFFFFF
1485 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1486 #define S_ULP_MEMIO_LOCK    27
1487 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1488 #define F_ULP_MEMIO_LOCK    V_ULP_MEMIO_LOCK(1U)
1489 
1490 /* ulp_mem_io.len fields */
1491 #define S_ULP_MEMIO_DATA_LEN    28
1492 #define M_ULP_MEMIO_DATA_LEN    0xF
1493 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1494 
1495 #endif              /* T3_CPL_H */
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