chelsio/cxgb3/firmware_exports.h

0001 /*
0002  * Copyright (c) 2004-2008 Chelsio, Inc. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032 #ifndef _FIRMWARE_EXPORTS_H_
0033 #define _FIRMWARE_EXPORTS_H_
0034
0035 /* WR OPCODES supported by the firmware.
0036  */
0037 #define FW_WROPCODE_FORWARD         0x01
0038 #define FW_WROPCODE_BYPASS          0x05
0039
0040 #define FW_WROPCODE_TUNNEL_TX_PKT       0x03
0041
0042 #define FW_WROPOCDE_ULPTX_DATA_SGL      0x00
0043 #define FW_WROPCODE_ULPTX_MEM_READ      0x02
0044 #define FW_WROPCODE_ULPTX_PKT           0x04
0045 #define FW_WROPCODE_ULPTX_INVALIDATE        0x06
0046
0047 #define FW_WROPCODE_TUNNEL_RX_PKT       0x07
0048
0049 #define FW_WROPCODE_OFLD_GETTCB_RPL     0x08
0050 #define FW_WROPCODE_OFLD_CLOSE_CON      0x09
0051 #define FW_WROPCODE_OFLD_TP_ABORT_CON_REQ   0x0A
0052 #define FW_WROPCODE_OFLD_HOST_ABORT_CON_RPL 0x0F
0053 #define FW_WROPCODE_OFLD_HOST_ABORT_CON_REQ 0x0B
0054 #define FW_WROPCODE_OFLD_TP_ABORT_CON_RPL   0x0C
0055 #define FW_WROPCODE_OFLD_TX_DATA        0x0D
0056 #define FW_WROPCODE_OFLD_TX_DATA_ACK        0x0E
0057
0058 #define FW_WROPCODE_RI_RDMA_INIT        0x10
0059 #define FW_WROPCODE_RI_RDMA_WRITE       0x11
0060 #define FW_WROPCODE_RI_RDMA_READ_REQ        0x12
0061 #define FW_WROPCODE_RI_RDMA_READ_RESP       0x13
0062 #define FW_WROPCODE_RI_SEND         0x14
0063 #define FW_WROPCODE_RI_TERMINATE        0x15
0064 #define FW_WROPCODE_RI_RDMA_READ        0x16
0065 #define FW_WROPCODE_RI_RECEIVE          0x17
0066 #define FW_WROPCODE_RI_BIND_MW          0x18
0067 #define FW_WROPCODE_RI_FASTREGISTER_MR      0x19
0068 #define FW_WROPCODE_RI_LOCAL_INV        0x1A
0069 #define FW_WROPCODE_RI_MODIFY_QP        0x1B
0070 #define FW_WROPCODE_RI_BYPASS           0x1C
0071
0072 #define FW_WROPOCDE_RSVD            0x1E
0073
0074 #define FW_WROPCODE_SGE_EGRESSCONTEXT_RR    0x1F
0075
0076 #define FW_WROPCODE_MNGT            0x1D
0077 #define FW_MNGTOPCODE_PKTSCHED_SET      0x00
0078
0079 /* Maximum size of a WR sent from the host, limited by the SGE.
0080  *
0081  * Note: WR coming from ULP or TP are only limited by CIM.
0082  */
0083 #define FW_WR_SIZE          128
0084
0085 /* Maximum number of outstanding WRs sent from the host. Value must be
0086  * programmed in the CTRL/TUNNEL/QP SGE Egress Context and used by
0087  * offload modules to limit the number of WRs per connection.
0088  */
0089 #define FW_T3_WR_NUM            16
0090 #define FW_N3_WR_NUM            7
0091
0092 #ifndef N3
0093 # define FW_WR_NUM          FW_T3_WR_NUM
0094 #else
0095 # define FW_WR_NUM          FW_N3_WR_NUM
0096 #endif
0097
0098 /* FW_TUNNEL_NUM corresponds to the number of supported TUNNEL Queues. These
0099  * queues must start at SGE Egress Context FW_TUNNEL_SGEEC_START and must
0100  * start at 'TID' (or 'uP Token') FW_TUNNEL_TID_START.
0101  *
0102  * Ingress Traffic (e.g. DMA completion credit)  for TUNNEL Queue[i] is sent
0103  * to RESP Queue[i].
0104  */
0105 #define FW_TUNNEL_NUM           8
0106 #define FW_TUNNEL_SGEEC_START       8
0107 #define FW_TUNNEL_TID_START     65544
0108
0109 /* FW_CTRL_NUM corresponds to the number of supported CTRL Queues. These queues
0110  * must start at SGE Egress Context FW_CTRL_SGEEC_START and must start at 'TID'
0111  * (or 'uP Token') FW_CTRL_TID_START.
0112  *
0113  * Ingress Traffic for CTRL Queue[i] is sent to RESP Queue[i].
0114  */
0115 #define FW_CTRL_NUM         8
0116 #define FW_CTRL_SGEEC_START     65528
0117 #define FW_CTRL_TID_START       65536
0118
0119 /* FW_OFLD_NUM corresponds to the number of supported OFFLOAD Queues. These
0120  * queues must start at SGE Egress Context FW_OFLD_SGEEC_START.
0121  *
0122  * Note: the 'uP Token' in the SGE Egress Context fields is irrelevant for
0123  * OFFLOAD Queues, as the host is responsible for providing the correct TID in
0124  * every WR.
0125  *
0126  * Ingress Trafffic for OFFLOAD Queue[i] is sent to RESP Queue[i].
0127  */
0128 #define FW_OFLD_NUM         8
0129 #define FW_OFLD_SGEEC_START     0
0130
0131 /*
0132  *
0133  */
0134 #define FW_RI_NUM           1
0135 #define FW_RI_SGEEC_START       65527
0136 #define FW_RI_TID_START         65552
0137
0138 /*
0139  * The RX_PKT_TID
0140  */
0141 #define FW_RX_PKT_NUM           1
0142 #define FW_RX_PKT_TID_START     65553
0143
0144 /* FW_WRC_NUM corresponds to the number of Work Request Context that supported
0145  * by the firmware.
0146  */
0147 #define FW_WRC_NUM          \
0148     (65536 + FW_TUNNEL_NUM + FW_CTRL_NUM + FW_RI_NUM + FW_RX_PKT_NUM)
0149
0150 /*
0151  * FW type and version.
0152  */
0153 #define S_FW_VERSION_TYPE       28
0154 #define M_FW_VERSION_TYPE       0xF
0155 #define V_FW_VERSION_TYPE(x)        ((x) << S_FW_VERSION_TYPE)
0156 #define G_FW_VERSION_TYPE(x)        \
0157     (((x) >> S_FW_VERSION_TYPE) & M_FW_VERSION_TYPE)
0158
0159 #define S_FW_VERSION_MAJOR      16
0160 #define M_FW_VERSION_MAJOR      0xFFF
0161 #define V_FW_VERSION_MAJOR(x)       ((x) << S_FW_VERSION_MAJOR)
0162 #define G_FW_VERSION_MAJOR(x)       \
0163     (((x) >> S_FW_VERSION_MAJOR) & M_FW_VERSION_MAJOR)
0164
0165 #define S_FW_VERSION_MINOR      8
0166 #define M_FW_VERSION_MINOR      0xFF
0167 #define V_FW_VERSION_MINOR(x)       ((x) << S_FW_VERSION_MINOR)
0168 #define G_FW_VERSION_MINOR(x)       \
0169     (((x) >> S_FW_VERSION_MINOR) & M_FW_VERSION_MINOR)
0170
0171 #define S_FW_VERSION_MICRO      0
0172 #define M_FW_VERSION_MICRO      0xFF
0173 #define V_FW_VERSION_MICRO(x)       ((x) << S_FW_VERSION_MICRO)
0174 #define G_FW_VERSION_MICRO(x)       \
0175     (((x) >> S_FW_VERSION_MICRO) & M_FW_VERSION_MICRO)
0176
0177 #endif              /* _FIRMWARE_EXPORTS_H_ */