chelsio/cxgb3/cxgb3_ioctl.h

0001 /*
0002  * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032 #ifndef __CHIOCTL_H__
0033 #define __CHIOCTL_H__
0034
0035 /*
0036  * Ioctl commands specific to this driver.
0037  */
0038 enum {
0039     CHELSIO_GETMTUTAB       = 1029,
0040     CHELSIO_SETMTUTAB       = 1030,
0041     CHELSIO_SET_PM          = 1032,
0042     CHELSIO_GET_PM          = 1033,
0043     CHELSIO_GET_MEM         = 1038,
0044     CHELSIO_LOAD_FW         = 1041,
0045     CHELSIO_SET_TRACE_FILTER    = 1044,
0046     CHELSIO_SET_QSET_PARAMS     = 1045,
0047     CHELSIO_GET_QSET_PARAMS     = 1046,
0048     CHELSIO_SET_QSET_NUM        = 1047,
0049     CHELSIO_GET_QSET_NUM        = 1048,
0050 };
0051
0052 struct ch_reg {
0053     uint32_t cmd;
0054     uint32_t addr;
0055     uint32_t val;
0056 };
0057
0058 struct ch_cntxt {
0059     uint32_t cmd;
0060     uint32_t cntxt_type;
0061     uint32_t cntxt_id;
0062     uint32_t data[4];
0063 };
0064
0065 /* context types */
0066 enum { CNTXT_TYPE_EGRESS, CNTXT_TYPE_FL, CNTXT_TYPE_RSP, CNTXT_TYPE_CQ };
0067
0068 struct ch_desc {
0069     uint32_t cmd;
0070     uint32_t queue_num;
0071     uint32_t idx;
0072     uint32_t size;
0073     uint8_t data[128];
0074 };
0075
0076 struct ch_mem_range {
0077     uint32_t cmd;
0078     uint32_t mem_id;
0079     uint32_t addr;
0080     uint32_t len;
0081     uint32_t version;
0082     uint8_t buf[];
0083 };
0084
0085 struct ch_qset_params {
0086     uint32_t cmd;
0087     uint32_t qset_idx;
0088     int32_t txq_size[3];
0089     int32_t rspq_size;
0090     int32_t fl_size[2];
0091     int32_t intr_lat;
0092     int32_t polling;
0093     int32_t lro;
0094     int32_t cong_thres;
0095     int32_t  vector;
0096     int32_t  qnum;
0097 };
0098
0099 struct ch_pktsched_params {
0100     uint32_t cmd;
0101     uint8_t sched;
0102     uint8_t idx;
0103     uint8_t min;
0104     uint8_t max;
0105     uint8_t binding;
0106 };
0107
0108 #ifndef TCB_SIZE
0109 # define TCB_SIZE   128
0110 #endif
0111
0112 /* TCB size in 32-bit words */
0113 #define TCB_WORDS (TCB_SIZE / 4)
0114
0115 enum { MEM_CM, MEM_PMRX, MEM_PMTX };    /* ch_mem_range.mem_id values */
0116
0117 struct ch_mtus {
0118     uint32_t cmd;
0119     uint32_t nmtus;
0120     uint16_t mtus[NMTUS];
0121 };
0122
0123 struct ch_pm {
0124     uint32_t cmd;
0125     uint32_t tx_pg_sz;
0126     uint32_t tx_num_pg;
0127     uint32_t rx_pg_sz;
0128     uint32_t rx_num_pg;
0129     uint32_t pm_total;
0130 };
0131
0132 struct ch_tcam {
0133     uint32_t cmd;
0134     uint32_t tcam_size;
0135     uint32_t nservers;
0136     uint32_t nroutes;
0137     uint32_t nfilters;
0138 };
0139
0140 struct ch_tcb {
0141     uint32_t cmd;
0142     uint32_t tcb_index;
0143     uint32_t tcb_data[TCB_WORDS];
0144 };
0145
0146 struct ch_tcam_word {
0147     uint32_t cmd;
0148     uint32_t addr;
0149     uint32_t buf[3];
0150 };
0151
0152 struct ch_trace {
0153     uint32_t cmd;
0154     uint32_t sip;
0155     uint32_t sip_mask;
0156     uint32_t dip;
0157     uint32_t dip_mask;
0158     uint16_t sport;
0159     uint16_t sport_mask;
0160     uint16_t dport;
0161     uint16_t dport_mask;
0162     uint32_t vlan:12;
0163     uint32_t vlan_mask:12;
0164     uint32_t intf:4;
0165     uint32_t intf_mask:4;
0166     uint8_t proto;
0167     uint8_t proto_mask;
0168     uint8_t invert_match:1;
0169     uint8_t config_tx:1;
0170     uint8_t config_rx:1;
0171     uint8_t trace_tx:1;
0172     uint8_t trace_rx:1;
0173 };
0174
0175 #define SIOCCHIOCTL SIOCDEVPRIVATE
0176
0177 #endif