![]() |
|
|||
0001 /* 0002 * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved. 0003 * 0004 * This software is available to you under a choice of one of two 0005 * licenses. You may choose to be licensed under the terms of the GNU 0006 * General Public License (GPL) Version 2, available from the file 0007 * COPYING in the main directory of this source tree, or the 0008 * OpenIB.org BSD license below: 0009 * 0010 * Redistribution and use in source and binary forms, with or 0011 * without modification, are permitted provided that the following 0012 * conditions are met: 0013 * 0014 * - Redistributions of source code must retain the above 0015 * copyright notice, this list of conditions and the following 0016 * disclaimer. 0017 * 0018 * - Redistributions in binary form must reproduce the above 0019 * copyright notice, this list of conditions and the following 0020 * disclaimer in the documentation and/or other materials 0021 * provided with the distribution. 0022 * 0023 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 0024 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 0025 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 0026 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 0027 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 0028 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 0029 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 0030 * SOFTWARE. 0031 */ 0032 #ifndef _CXGB3_OFFLOAD_CTL_DEFS_H 0033 #define _CXGB3_OFFLOAD_CTL_DEFS_H 0034 0035 enum { 0036 GET_MAX_OUTSTANDING_WR = 0, 0037 GET_TX_MAX_CHUNK = 1, 0038 GET_TID_RANGE = 2, 0039 GET_STID_RANGE = 3, 0040 GET_RTBL_RANGE = 4, 0041 GET_L2T_CAPACITY = 5, 0042 GET_MTUS = 6, 0043 GET_WR_LEN = 7, 0044 GET_IFF_FROM_MAC = 8, 0045 GET_DDP_PARAMS = 9, 0046 GET_PORTS = 10, 0047 0048 ULP_ISCSI_GET_PARAMS = 11, 0049 ULP_ISCSI_SET_PARAMS = 12, 0050 0051 RDMA_GET_PARAMS = 13, 0052 RDMA_CQ_OP = 14, 0053 RDMA_CQ_SETUP = 15, 0054 RDMA_CQ_DISABLE = 16, 0055 RDMA_CTRL_QP_SETUP = 17, 0056 RDMA_GET_MEM = 18, 0057 RDMA_GET_MIB = 19, 0058 0059 GET_RX_PAGE_INFO = 50, 0060 GET_ISCSI_IPV4ADDR = 51, 0061 0062 GET_EMBEDDED_INFO = 70, 0063 }; 0064 0065 /* 0066 * Structure used to describe a TID range. Valid TIDs are [base, base+num). 0067 */ 0068 struct tid_range { 0069 unsigned int base; /* first TID */ 0070 unsigned int num; /* number of TIDs in range */ 0071 }; 0072 0073 /* 0074 * Structure used to request the size and contents of the MTU table. 0075 */ 0076 struct mtutab { 0077 unsigned int size; /* # of entries in the MTU table */ 0078 const unsigned short *mtus; /* the MTU table values */ 0079 }; 0080 0081 struct net_device; 0082 0083 /* 0084 * Structure used to request the adapter net_device owning a given MAC address. 0085 */ 0086 struct iff_mac { 0087 struct net_device *dev; /* the net_device */ 0088 const unsigned char *mac_addr; /* MAC address to lookup */ 0089 u16 vlan_tag; 0090 }; 0091 0092 /* Structure used to request a port's iSCSI IPv4 address */ 0093 struct iscsi_ipv4addr { 0094 struct net_device *dev; /* the net_device */ 0095 __be32 ipv4addr; /* the return iSCSI IPv4 address */ 0096 }; 0097 0098 struct pci_dev; 0099 0100 /* 0101 * Structure used to request the TCP DDP parameters. 0102 */ 0103 struct ddp_params { 0104 unsigned int llimit; /* TDDP region start address */ 0105 unsigned int ulimit; /* TDDP region end address */ 0106 unsigned int tag_mask; /* TDDP tag mask */ 0107 struct pci_dev *pdev; 0108 }; 0109 0110 struct adap_ports { 0111 unsigned int nports; /* number of ports on this adapter */ 0112 struct net_device *lldevs[2]; 0113 }; 0114 0115 /* 0116 * Structure used to return information to the iscsi layer. 0117 */ 0118 struct ulp_iscsi_info { 0119 unsigned int offset; 0120 unsigned int llimit; 0121 unsigned int ulimit; 0122 unsigned int tagmask; 0123 u8 pgsz_factor[4]; 0124 unsigned int max_rxsz; 0125 unsigned int max_txsz; 0126 struct pci_dev *pdev; 0127 }; 0128 0129 /* 0130 * Structure used to return information to the RDMA layer. 0131 */ 0132 struct rdma_info { 0133 unsigned int tpt_base; /* TPT base address */ 0134 unsigned int tpt_top; /* TPT last entry address */ 0135 unsigned int pbl_base; /* PBL base address */ 0136 unsigned int pbl_top; /* PBL last entry address */ 0137 unsigned int rqt_base; /* RQT base address */ 0138 unsigned int rqt_top; /* RQT last entry address */ 0139 unsigned int udbell_len; /* user doorbell region length */ 0140 unsigned long udbell_physbase; /* user doorbell physical start addr */ 0141 void __iomem *kdb_addr; /* kernel doorbell register address */ 0142 struct pci_dev *pdev; /* associated PCI device */ 0143 }; 0144 0145 /* 0146 * Structure used to request an operation on an RDMA completion queue. 0147 */ 0148 struct rdma_cq_op { 0149 unsigned int id; 0150 unsigned int op; 0151 unsigned int credits; 0152 }; 0153 0154 /* 0155 * Structure used to setup RDMA completion queues. 0156 */ 0157 struct rdma_cq_setup { 0158 unsigned int id; 0159 unsigned long long base_addr; 0160 unsigned int size; 0161 unsigned int credits; 0162 unsigned int credit_thres; 0163 unsigned int ovfl_mode; 0164 }; 0165 0166 /* 0167 * Structure used to setup the RDMA control egress context. 0168 */ 0169 struct rdma_ctrlqp_setup { 0170 unsigned long long base_addr; 0171 unsigned int size; 0172 }; 0173 0174 /* 0175 * Offload TX/RX page information. 0176 */ 0177 struct ofld_page_info { 0178 unsigned int page_size; /* Page size, should be a power of 2 */ 0179 unsigned int num; /* Number of pages */ 0180 }; 0181 0182 /* 0183 * Structure used to get firmware and protocol engine versions. 0184 */ 0185 struct ch_embedded_info { 0186 u32 fw_vers; 0187 u32 tp_vers; 0188 }; 0189 #endif /* _CXGB3_OFFLOAD_CTL_DEFS_H */
[ Source navigation ] | [ Diff markup ] | [ Identifier search ] | [ general search ] |
This page was automatically generated by the 2.1.0 LXR engine. The LXR team |
![]() ![]() |