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0001 /*
0002  * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032 #ifndef __CHELSIO_COMMON_H
0033 #define __CHELSIO_COMMON_H
0034 
0035 #include <linux/kernel.h>
0036 #include <linux/types.h>
0037 #include <linux/ctype.h>
0038 #include <linux/delay.h>
0039 #include <linux/netdevice.h>
0040 #include <linux/ethtool.h>
0041 #include <linux/mdio.h>
0042 #include "version.h"
0043 
0044 #define CH_ERR(adap, fmt, ...)   dev_err(&adap->pdev->dev, fmt, ##__VA_ARGS__)
0045 #define CH_WARN(adap, fmt, ...)  dev_warn(&adap->pdev->dev, fmt, ##__VA_ARGS__)
0046 #define CH_ALERT(adap, fmt, ...) dev_alert(&adap->pdev->dev, fmt, ##__VA_ARGS__)
0047 
0048 /*
0049  * More powerful macro that selectively prints messages based on msg_enable.
0050  * For info and debugging messages.
0051  */
0052 #define CH_MSG(adapter, level, category, fmt, ...) do { \
0053     if ((adapter)->msg_enable & NETIF_MSG_##category) \
0054         dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \
0055                ## __VA_ARGS__); \
0056 } while (0)
0057 
0058 #ifdef DEBUG
0059 # define CH_DBG(adapter, category, fmt, ...) \
0060     CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__)
0061 #else
0062 # define CH_DBG(adapter, category, fmt, ...)
0063 #endif
0064 
0065 /* Additional NETIF_MSG_* categories */
0066 #define NETIF_MSG_MMIO 0x8000000
0067 
0068 enum {
0069     MAX_NPORTS = 2,     /* max # of ports */
0070     MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */
0071     EEPROMSIZE = 8192,  /* Serial EEPROM size */
0072     SERNUM_LEN     = 16,    /* Serial # length */
0073     RSS_TABLE_SIZE = 64,    /* size of RSS lookup and mapping tables */
0074     TCB_SIZE = 128,     /* TCB size */
0075     NMTUS = 16,     /* size of MTU table */
0076     NCCTRL_WIN = 32,    /* # of congestion control windows */
0077     PROTO_SRAM_LINES = 128, /* size of TP sram */
0078 };
0079 
0080 #define MAX_RX_COALESCING_LEN 12288U
0081 
0082 enum {
0083     PAUSE_RX = 1 << 0,
0084     PAUSE_TX = 1 << 1,
0085     PAUSE_AUTONEG = 1 << 2
0086 };
0087 
0088 enum {
0089     SUPPORTED_IRQ      = 1 << 24
0090 };
0091 
0092 enum {              /* adapter interrupt-maintained statistics */
0093     STAT_ULP_CH0_PBL_OOB,
0094     STAT_ULP_CH1_PBL_OOB,
0095     STAT_PCI_CORR_ECC,
0096 
0097     IRQ_NUM_STATS       /* keep last */
0098 };
0099 
0100 #define TP_VERSION_MAJOR    1
0101 #define TP_VERSION_MINOR    1
0102 #define TP_VERSION_MICRO    0
0103 
0104 #define S_TP_VERSION_MAJOR      16
0105 #define M_TP_VERSION_MAJOR      0xFF
0106 #define V_TP_VERSION_MAJOR(x)       ((x) << S_TP_VERSION_MAJOR)
0107 #define G_TP_VERSION_MAJOR(x)       \
0108         (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
0109 
0110 #define S_TP_VERSION_MINOR      8
0111 #define M_TP_VERSION_MINOR      0xFF
0112 #define V_TP_VERSION_MINOR(x)       ((x) << S_TP_VERSION_MINOR)
0113 #define G_TP_VERSION_MINOR(x)       \
0114         (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
0115 
0116 #define S_TP_VERSION_MICRO      0
0117 #define M_TP_VERSION_MICRO      0xFF
0118 #define V_TP_VERSION_MICRO(x)       ((x) << S_TP_VERSION_MICRO)
0119 #define G_TP_VERSION_MICRO(x)       \
0120         (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
0121 
0122 enum {
0123     SGE_QSETS = 8,      /* # of SGE Tx/Rx/RspQ sets */
0124     SGE_RXQ_PER_SET = 2,    /* # of Rx queues per set */
0125     SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
0126 };
0127 
0128 enum sge_context_type {     /* SGE egress context types */
0129     SGE_CNTXT_RDMA = 0,
0130     SGE_CNTXT_ETH = 2,
0131     SGE_CNTXT_OFLD = 4,
0132     SGE_CNTXT_CTRL = 5
0133 };
0134 
0135 enum {
0136     AN_PKT_SIZE = 32,   /* async notification packet size */
0137     IMMED_PKT_SIZE = 48 /* packet size for immediate data */
0138 };
0139 
0140 struct sg_ent {         /* SGE scatter/gather entry */
0141     __be32 len[2];
0142     __be64 addr[2];
0143 };
0144 
0145 #ifndef SGE_NUM_GENBITS
0146 /* Must be 1 or 2 */
0147 # define SGE_NUM_GENBITS 2
0148 #endif
0149 
0150 #define TX_DESC_FLITS 16U
0151 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
0152 
0153 struct cphy;
0154 struct adapter;
0155 
0156 struct mdio_ops {
0157     int (*read)(struct net_device *dev, int phy_addr, int mmd_addr,
0158             u16 reg_addr);
0159     int (*write)(struct net_device *dev, int phy_addr, int mmd_addr,
0160              u16 reg_addr, u16 val);
0161     unsigned mode_support;
0162 };
0163 
0164 struct adapter_info {
0165     unsigned char nports0;        /* # of ports on channel 0 */
0166     unsigned char nports1;        /* # of ports on channel 1 */
0167     unsigned char phy_base_addr;    /* MDIO PHY base address */
0168     unsigned int gpio_out;  /* GPIO output settings */
0169     unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */
0170     unsigned long caps; /* adapter capabilities */
0171     const struct mdio_ops *mdio_ops;    /* MDIO operations */
0172     const char *desc;   /* product description */
0173 };
0174 
0175 struct mc5_stats {
0176     unsigned long parity_err;
0177     unsigned long active_rgn_full;
0178     unsigned long nfa_srch_err;
0179     unsigned long unknown_cmd;
0180     unsigned long reqq_parity_err;
0181     unsigned long dispq_parity_err;
0182     unsigned long del_act_empty;
0183 };
0184 
0185 struct mc7_stats {
0186     unsigned long corr_err;
0187     unsigned long uncorr_err;
0188     unsigned long parity_err;
0189     unsigned long addr_err;
0190 };
0191 
0192 struct mac_stats {
0193     u64 tx_octets;      /* total # of octets in good frames */
0194     u64 tx_octets_bad;  /* total # of octets in error frames */
0195     u64 tx_frames;      /* all good frames */
0196     u64 tx_mcast_frames;    /* good multicast frames */
0197     u64 tx_bcast_frames;    /* good broadcast frames */
0198     u64 tx_pause;       /* # of transmitted pause frames */
0199     u64 tx_deferred;    /* frames with deferred transmissions */
0200     u64 tx_late_collisions; /* # of late collisions */
0201     u64 tx_total_collisions;    /* # of total collisions */
0202     u64 tx_excess_collisions;   /* frame errors from excessive collissions */
0203     u64 tx_underrun;    /* # of Tx FIFO underruns */
0204     u64 tx_len_errs;    /* # of Tx length errors */
0205     u64 tx_mac_internal_errs;   /* # of internal MAC errors on Tx */
0206     u64 tx_excess_deferral; /* # of frames with excessive deferral */
0207     u64 tx_fcs_errs;    /* # of frames with bad FCS */
0208 
0209     u64 tx_frames_64;   /* # of Tx frames in a particular range */
0210     u64 tx_frames_65_127;
0211     u64 tx_frames_128_255;
0212     u64 tx_frames_256_511;
0213     u64 tx_frames_512_1023;
0214     u64 tx_frames_1024_1518;
0215     u64 tx_frames_1519_max;
0216 
0217     u64 rx_octets;      /* total # of octets in good frames */
0218     u64 rx_octets_bad;  /* total # of octets in error frames */
0219     u64 rx_frames;      /* all good frames */
0220     u64 rx_mcast_frames;    /* good multicast frames */
0221     u64 rx_bcast_frames;    /* good broadcast frames */
0222     u64 rx_pause;       /* # of received pause frames */
0223     u64 rx_fcs_errs;    /* # of received frames with bad FCS */
0224     u64 rx_align_errs;  /* alignment errors */
0225     u64 rx_symbol_errs; /* symbol errors */
0226     u64 rx_data_errs;   /* data errors */
0227     u64 rx_sequence_errs;   /* sequence errors */
0228     u64 rx_runt;        /* # of runt frames */
0229     u64 rx_jabber;      /* # of jabber frames */
0230     u64 rx_short;       /* # of short frames */
0231     u64 rx_too_long;    /* # of oversized frames */
0232     u64 rx_mac_internal_errs;   /* # of internal MAC errors on Rx */
0233 
0234     u64 rx_frames_64;   /* # of Rx frames in a particular range */
0235     u64 rx_frames_65_127;
0236     u64 rx_frames_128_255;
0237     u64 rx_frames_256_511;
0238     u64 rx_frames_512_1023;
0239     u64 rx_frames_1024_1518;
0240     u64 rx_frames_1519_max;
0241 
0242     u64 rx_cong_drops;  /* # of Rx drops due to SGE congestion */
0243 
0244     unsigned long tx_fifo_parity_err;
0245     unsigned long rx_fifo_parity_err;
0246     unsigned long tx_fifo_urun;
0247     unsigned long rx_fifo_ovfl;
0248     unsigned long serdes_signal_loss;
0249     unsigned long xaui_pcs_ctc_err;
0250     unsigned long xaui_pcs_align_change;
0251 
0252     unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
0253     unsigned long num_resets;  /* # times reset due to stuck TX */
0254 
0255     unsigned long link_faults;  /* # detected link faults */
0256 };
0257 
0258 struct tp_mib_stats {
0259     u32 ipInReceive_hi;
0260     u32 ipInReceive_lo;
0261     u32 ipInHdrErrors_hi;
0262     u32 ipInHdrErrors_lo;
0263     u32 ipInAddrErrors_hi;
0264     u32 ipInAddrErrors_lo;
0265     u32 ipInUnknownProtos_hi;
0266     u32 ipInUnknownProtos_lo;
0267     u32 ipInDiscards_hi;
0268     u32 ipInDiscards_lo;
0269     u32 ipInDelivers_hi;
0270     u32 ipInDelivers_lo;
0271     u32 ipOutRequests_hi;
0272     u32 ipOutRequests_lo;
0273     u32 ipOutDiscards_hi;
0274     u32 ipOutDiscards_lo;
0275     u32 ipOutNoRoutes_hi;
0276     u32 ipOutNoRoutes_lo;
0277     u32 ipReasmTimeout;
0278     u32 ipReasmReqds;
0279     u32 ipReasmOKs;
0280     u32 ipReasmFails;
0281 
0282     u32 reserved[8];
0283 
0284     u32 tcpActiveOpens;
0285     u32 tcpPassiveOpens;
0286     u32 tcpAttemptFails;
0287     u32 tcpEstabResets;
0288     u32 tcpOutRsts;
0289     u32 tcpCurrEstab;
0290     u32 tcpInSegs_hi;
0291     u32 tcpInSegs_lo;
0292     u32 tcpOutSegs_hi;
0293     u32 tcpOutSegs_lo;
0294     u32 tcpRetransSeg_hi;
0295     u32 tcpRetransSeg_lo;
0296     u32 tcpInErrs_hi;
0297     u32 tcpInErrs_lo;
0298     u32 tcpRtoMin;
0299     u32 tcpRtoMax;
0300 };
0301 
0302 struct tp_params {
0303     unsigned int nchan; /* # of channels */
0304     unsigned int pmrx_size; /* total PMRX capacity */
0305     unsigned int pmtx_size; /* total PMTX capacity */
0306     unsigned int cm_size;   /* total CM capacity */
0307     unsigned int chan_rx_size;  /* per channel Rx size */
0308     unsigned int chan_tx_size;  /* per channel Tx size */
0309     unsigned int rx_pg_size;    /* Rx page size */
0310     unsigned int tx_pg_size;    /* Tx page size */
0311     unsigned int rx_num_pgs;    /* # of Rx pages */
0312     unsigned int tx_num_pgs;    /* # of Tx pages */
0313     unsigned int ntimer_qs; /* # of timer queues */
0314 };
0315 
0316 struct qset_params {        /* SGE queue set parameters */
0317     unsigned int polling;   /* polling/interrupt service for rspq */
0318     unsigned int coalesce_usecs;    /* irq coalescing timer */
0319     unsigned int rspq_size; /* # of entries in response queue */
0320     unsigned int fl_size;   /* # of entries in regular free list */
0321     unsigned int jumbo_size;    /* # of entries in jumbo free list */
0322     unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
0323     unsigned int cong_thres;    /* FL congestion threshold */
0324     unsigned int vector;        /* Interrupt (line or vector) number */
0325 };
0326 
0327 struct sge_params {
0328     unsigned int max_pkt_size;  /* max offload pkt size */
0329     struct qset_params qset[SGE_QSETS];
0330 };
0331 
0332 struct mc5_params {
0333     unsigned int mode;  /* selects MC5 width */
0334     unsigned int nservers;  /* size of server region */
0335     unsigned int nfilters;  /* size of filter region */
0336     unsigned int nroutes;   /* size of routing region */
0337 };
0338 
0339 /* Default MC5 region sizes */
0340 enum {
0341     DEFAULT_NSERVERS = 512,
0342     DEFAULT_NFILTERS = 128
0343 };
0344 
0345 /* MC5 modes, these must be non-0 */
0346 enum {
0347     MC5_MODE_144_BIT = 1,
0348     MC5_MODE_72_BIT = 2
0349 };
0350 
0351 /* MC5 min active region size */
0352 enum { MC5_MIN_TIDS = 16 };
0353 
0354 struct vpd_params {
0355     unsigned int cclk;
0356     unsigned int mclk;
0357     unsigned int uclk;
0358     unsigned int mdc;
0359     unsigned int mem_timing;
0360     u8 sn[SERNUM_LEN + 1];
0361     u8 eth_base[6];
0362     u8 port_type[MAX_NPORTS];
0363     unsigned short xauicfg[2];
0364 };
0365 
0366 struct pci_params {
0367     unsigned int vpd_cap_addr;
0368     unsigned short speed;
0369     unsigned char width;
0370     unsigned char variant;
0371 };
0372 
0373 enum {
0374     PCI_VARIANT_PCI,
0375     PCI_VARIANT_PCIX_MODE1_PARITY,
0376     PCI_VARIANT_PCIX_MODE1_ECC,
0377     PCI_VARIANT_PCIX_266_MODE2,
0378     PCI_VARIANT_PCIE
0379 };
0380 
0381 struct adapter_params {
0382     struct sge_params sge;
0383     struct mc5_params mc5;
0384     struct tp_params tp;
0385     struct vpd_params vpd;
0386     struct pci_params pci;
0387 
0388     const struct adapter_info *info;
0389 
0390     unsigned short mtus[NMTUS];
0391     unsigned short a_wnd[NCCTRL_WIN];
0392     unsigned short b_wnd[NCCTRL_WIN];
0393 
0394     unsigned int nports;    /* # of ethernet ports */
0395     unsigned int chan_map;  /* bitmap of in-use Tx channels */
0396     unsigned int stats_update_period;   /* MAC stats accumulation period */
0397     unsigned int linkpoll_period;   /* link poll period in 0.1s */
0398     unsigned int rev;   /* chip revision */
0399     unsigned int offload;
0400 };
0401 
0402 enum {                      /* chip revisions */
0403     T3_REV_A  = 0,
0404     T3_REV_B  = 2,
0405     T3_REV_B2 = 3,
0406     T3_REV_C  = 4,
0407 };
0408 
0409 struct trace_params {
0410     u32 sip;
0411     u32 sip_mask;
0412     u32 dip;
0413     u32 dip_mask;
0414     u16 sport;
0415     u16 sport_mask;
0416     u16 dport;
0417     u16 dport_mask;
0418     u32 vlan:12;
0419     u32 vlan_mask:12;
0420     u32 intf:4;
0421     u32 intf_mask:4;
0422     u8 proto;
0423     u8 proto_mask;
0424 };
0425 
0426 struct link_config {
0427     unsigned int supported; /* link capabilities */
0428     unsigned int advertising;   /* advertised capabilities */
0429     unsigned short requested_speed; /* speed user has requested */
0430     unsigned short speed;   /* actual link speed */
0431     unsigned char requested_duplex; /* duplex user has requested */
0432     unsigned char duplex;   /* actual link duplex */
0433     unsigned char requested_fc; /* flow control user has requested */
0434     unsigned char fc;   /* actual link flow control */
0435     unsigned char autoneg;  /* autonegotiating? */
0436     unsigned int link_ok;   /* link up? */
0437 };
0438 
0439 #define SPEED_INVALID   0xffff
0440 #define DUPLEX_INVALID  0xff
0441 
0442 struct mc5 {
0443     struct adapter *adapter;
0444     unsigned int tcam_size;
0445     unsigned char part_type;
0446     unsigned char parity_enabled;
0447     unsigned char mode;
0448     struct mc5_stats stats;
0449 };
0450 
0451 static inline unsigned int t3_mc5_size(const struct mc5 *p)
0452 {
0453     return p->tcam_size;
0454 }
0455 
0456 struct mc7 {
0457     struct adapter *adapter;    /* backpointer to adapter */
0458     unsigned int size;  /* memory size in bytes */
0459     unsigned int width; /* MC7 interface width */
0460     unsigned int offset;    /* register address offset for MC7 instance */
0461     const char *name;   /* name of MC7 instance */
0462     struct mc7_stats stats; /* MC7 statistics */
0463 };
0464 
0465 static inline unsigned int t3_mc7_size(const struct mc7 *p)
0466 {
0467     return p->size;
0468 }
0469 
0470 struct cmac {
0471     struct adapter *adapter;
0472     unsigned int offset;
0473     unsigned int nucast;    /* # of address filters for unicast MACs */
0474     unsigned int tx_tcnt;
0475     unsigned int tx_xcnt;
0476     u64 tx_mcnt;
0477     unsigned int rx_xcnt;
0478     unsigned int rx_ocnt;
0479     u64 rx_mcnt;
0480     unsigned int toggle_cnt;
0481     unsigned int txen;
0482     u64 rx_pause;
0483     struct mac_stats stats;
0484 };
0485 
0486 enum {
0487     MAC_DIRECTION_RX = 1,
0488     MAC_DIRECTION_TX = 2,
0489     MAC_RXFIFO_SIZE = 32768
0490 };
0491 
0492 /* PHY loopback direction */
0493 enum {
0494     PHY_LOOPBACK_TX = 1,
0495     PHY_LOOPBACK_RX = 2
0496 };
0497 
0498 /* PHY interrupt types */
0499 enum {
0500     cphy_cause_link_change = 1,
0501     cphy_cause_fifo_error = 2,
0502     cphy_cause_module_change = 4,
0503 };
0504 
0505 /* PHY module types */
0506 enum {
0507     phy_modtype_none,
0508     phy_modtype_sr,
0509     phy_modtype_lr,
0510     phy_modtype_lrm,
0511     phy_modtype_twinax,
0512     phy_modtype_twinax_long,
0513     phy_modtype_unknown
0514 };
0515 
0516 /* PHY operations */
0517 struct cphy_ops {
0518     int (*reset)(struct cphy *phy, int wait);
0519 
0520     int (*intr_enable)(struct cphy *phy);
0521     int (*intr_disable)(struct cphy *phy);
0522     int (*intr_clear)(struct cphy *phy);
0523     int (*intr_handler)(struct cphy *phy);
0524 
0525     int (*autoneg_enable)(struct cphy *phy);
0526     int (*autoneg_restart)(struct cphy *phy);
0527 
0528     int (*advertise)(struct cphy *phy, unsigned int advertise_map);
0529     int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
0530     int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
0531     int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
0532                    int *duplex, int *fc);
0533     int (*power_down)(struct cphy *phy, int enable);
0534 
0535     u32 mmds;
0536 };
0537 enum {
0538     EDC_OPT_AEL2005 = 0,
0539     EDC_OPT_AEL2005_SIZE = 1084,
0540     EDC_TWX_AEL2005 = 1,
0541     EDC_TWX_AEL2005_SIZE = 1464,
0542     EDC_TWX_AEL2020 = 2,
0543     EDC_TWX_AEL2020_SIZE = 1628,
0544     EDC_MAX_SIZE = EDC_TWX_AEL2020_SIZE, /* Max cache size */
0545 };
0546 
0547 /* A PHY instance */
0548 struct cphy {
0549     u8 modtype;         /* PHY module type */
0550     short priv;         /* scratch pad */
0551     unsigned int caps;      /* PHY capabilities */
0552     struct adapter *adapter;    /* associated adapter */
0553     const char *desc;       /* PHY description */
0554     unsigned long fifo_errors;  /* FIFO over/under-flows */
0555     const struct cphy_ops *ops; /* PHY operations */
0556     struct mdio_if_info mdio;
0557     u16 phy_cache[EDC_MAX_SIZE];    /* EDC cache */
0558 };
0559 
0560 /* Convenience MDIO read/write wrappers */
0561 static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg,
0562                    unsigned int *valp)
0563 {
0564     int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg);
0565     *valp = (rc >= 0) ? rc : -1;
0566     return (rc >= 0) ? 0 : rc;
0567 }
0568 
0569 static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg,
0570                 unsigned int val)
0571 {
0572     return phy->mdio.mdio_write(phy->mdio.dev, phy->mdio.prtad, mmd,
0573                     reg, val);
0574 }
0575 
0576 /* Convenience initializer */
0577 static inline void cphy_init(struct cphy *phy, struct adapter *adapter,
0578                  int phy_addr, const struct cphy_ops *phy_ops,
0579                  const struct mdio_ops *mdio_ops,
0580                   unsigned int caps, const char *desc)
0581 {
0582     phy->caps = caps;
0583     phy->adapter = adapter;
0584     phy->desc = desc;
0585     phy->ops = phy_ops;
0586     if (mdio_ops) {
0587         phy->mdio.prtad = phy_addr;
0588         phy->mdio.mmds = phy_ops->mmds;
0589         phy->mdio.mode_support = mdio_ops->mode_support;
0590         phy->mdio.mdio_read = mdio_ops->read;
0591         phy->mdio.mdio_write = mdio_ops->write;
0592     }
0593 }
0594 
0595 /* Accumulate MAC statistics every 180 seconds.  For 1G we multiply by 10. */
0596 #define MAC_STATS_ACCUM_SECS 180
0597 
0598 #define XGM_REG(reg_addr, idx) \
0599     ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
0600 
0601 struct addr_val_pair {
0602     unsigned int reg_addr;
0603     unsigned int val;
0604 };
0605 
0606 #include "adapter.h"
0607 
0608 #ifndef PCI_VENDOR_ID_CHELSIO
0609 # define PCI_VENDOR_ID_CHELSIO 0x1425
0610 #endif
0611 
0612 #define for_each_port(adapter, iter) \
0613     for (iter = 0; iter < (adapter)->params.nports; ++iter)
0614 
0615 #define adapter_info(adap) ((adap)->params.info)
0616 
0617 static inline int uses_xaui(const struct adapter *adap)
0618 {
0619     return adapter_info(adap)->caps & SUPPORTED_AUI;
0620 }
0621 
0622 static inline int is_10G(const struct adapter *adap)
0623 {
0624     return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
0625 }
0626 
0627 static inline int is_offload(const struct adapter *adap)
0628 {
0629     return adap->params.offload;
0630 }
0631 
0632 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
0633 {
0634     return adap->params.vpd.cclk / 1000;
0635 }
0636 
0637 static inline unsigned int is_pcie(const struct adapter *adap)
0638 {
0639     return adap->params.pci.variant == PCI_VARIANT_PCIE;
0640 }
0641 
0642 void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
0643               u32 val);
0644 void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p,
0645            int n, unsigned int offset);
0646 int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
0647             int polarity, int attempts, int delay, u32 *valp);
0648 static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask,
0649                   int polarity, int attempts, int delay)
0650 {
0651     return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
0652                    delay, NULL);
0653 }
0654 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
0655             unsigned int set);
0656 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
0657 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
0658 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
0659 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
0660 int t3_phy_lasi_intr_enable(struct cphy *phy);
0661 int t3_phy_lasi_intr_disable(struct cphy *phy);
0662 int t3_phy_lasi_intr_clear(struct cphy *phy);
0663 int t3_phy_lasi_intr_handler(struct cphy *phy);
0664 
0665 void t3_intr_enable(struct adapter *adapter);
0666 void t3_intr_disable(struct adapter *adapter);
0667 void t3_intr_clear(struct adapter *adapter);
0668 void t3_xgm_intr_enable(struct adapter *adapter, int idx);
0669 void t3_xgm_intr_disable(struct adapter *adapter, int idx);
0670 void t3_port_intr_enable(struct adapter *adapter, int idx);
0671 void t3_port_intr_disable(struct adapter *adapter, int idx);
0672 int t3_slow_intr_handler(struct adapter *adapter);
0673 int t3_phy_intr_handler(struct adapter *adapter);
0674 
0675 void t3_link_changed(struct adapter *adapter, int port_id);
0676 void t3_link_fault(struct adapter *adapter, int port_id);
0677 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
0678 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
0679 int t3_seeprom_wp(struct adapter *adapter, int enable);
0680 int t3_get_tp_version(struct adapter *adapter, u32 *vers);
0681 int t3_check_tpsram_version(struct adapter *adapter);
0682 int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram,
0683             unsigned int size);
0684 int t3_set_proto_sram(struct adapter *adap, const u8 *data);
0685 int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size);
0686 int t3_get_fw_version(struct adapter *adapter, u32 *vers);
0687 int t3_check_fw_version(struct adapter *adapter);
0688 int t3_init_hw(struct adapter *adapter, u32 fw_params);
0689 int t3_reset_adapter(struct adapter *adapter);
0690 int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
0691             int reset);
0692 int t3_replay_prep_adapter(struct adapter *adapter);
0693 void t3_led_ready(struct adapter *adapter);
0694 void t3_fatal_err(struct adapter *adapter);
0695 void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on);
0696 void t3_config_rss(struct adapter *adapter, unsigned int rss_config,
0697            const u8 * cpus, const u16 *rspq);
0698 int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr,
0699             unsigned int n, unsigned int *valp);
0700 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
0701            u64 *buf);
0702 
0703 int t3_mac_reset(struct cmac *mac);
0704 void t3b_pcs_reset(struct cmac *mac);
0705 void t3_mac_disable_exact_filters(struct cmac *mac);
0706 void t3_mac_enable_exact_filters(struct cmac *mac);
0707 int t3_mac_enable(struct cmac *mac, int which);
0708 int t3_mac_disable(struct cmac *mac, int which);
0709 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
0710 int t3_mac_set_rx_mode(struct cmac *mac, struct net_device *dev);
0711 int t3_mac_set_address(struct cmac *mac, unsigned int idx, const u8 addr[6]);
0712 int t3_mac_set_num_ucast(struct cmac *mac, int n);
0713 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
0714 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc);
0715 int t3b2_mac_watchdog_task(struct cmac *mac);
0716 
0717 void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode);
0718 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
0719         unsigned int nroutes);
0720 void t3_mc5_intr_handler(struct mc5 *mc5);
0721 
0722 void t3_tp_set_offload_mode(struct adapter *adap, int enable);
0723 void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps);
0724 void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS],
0725           unsigned short alpha[NCCTRL_WIN],
0726           unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
0727 void t3_config_trace_filter(struct adapter *adapter,
0728                 const struct trace_params *tp, int filter_index,
0729                 int invert, int enable);
0730 int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched);
0731 
0732 void t3_sge_prep(struct adapter *adap, struct sge_params *p);
0733 void t3_sge_init(struct adapter *adap, struct sge_params *p);
0734 int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable,
0735                enum sge_context_type type, int respq, u64 base_addr,
0736                unsigned int size, unsigned int token, int gen,
0737                unsigned int cidx);
0738 int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id,
0739             int gts_enable, u64 base_addr, unsigned int size,
0740             unsigned int esize, unsigned int cong_thres, int gen,
0741             unsigned int cidx);
0742 int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id,
0743              int irq_vec_idx, u64 base_addr, unsigned int size,
0744              unsigned int fl_thres, int gen, unsigned int cidx);
0745 int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr,
0746             unsigned int size, int rspq, int ovfl_mode,
0747             unsigned int credits, unsigned int credit_thres);
0748 int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable);
0749 int t3_sge_disable_fl(struct adapter *adapter, unsigned int id);
0750 int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id);
0751 int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id);
0752 int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op,
0753               unsigned int credits);
0754 
0755 int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
0756             int phy_addr, const struct mdio_ops *mdio_ops);
0757 int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter,
0758             int phy_addr, const struct mdio_ops *mdio_ops);
0759 int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter,
0760             int phy_addr, const struct mdio_ops *mdio_ops);
0761 int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter,
0762             int phy_addr, const struct mdio_ops *mdio_ops);
0763 int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter,
0764             int phy_addr, const struct mdio_ops *mdio_ops);
0765 int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr,
0766                const struct mdio_ops *mdio_ops);
0767 int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter,
0768                 int phy_addr, const struct mdio_ops *mdio_ops);
0769 int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter,
0770                 int phy_addr, const struct mdio_ops *mdio_ops);
0771 
0772 extern struct workqueue_struct *cxgb3_wq;
0773 #endif              /* __CHELSIO_COMMON_H */
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