chelsio/cxgb/vsc7326_reg.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* $Date: 2006/04/28 19:20:17 $ $RCSfile: vsc7326_reg.h,v $ $Revision: 1.5 $ */
0003 #ifndef _VSC7321_REG_H_
0004 #define _VSC7321_REG_H_
0005
0006 /* Register definitions for Vitesse VSC7321 (Meigs II) MAC
0007  *
0008  * Straight off the data sheet, VMDS-10038 Rev 2.0 and
0009  * PD0011-01-14-Meigs-II 2002-12-12
0010  */
0011
0012 /* Just 'cause it's in here doesn't mean it's used. */
0013
0014 #define CRA(blk,sub,adr) ((((blk) & 0x7) << 13) | (((sub) & 0xf) << 9) | (((adr) & 0xff) << 1))
0015
0016 /* System and CPU comm's registers */
0017 #define REG_CHIP_ID     CRA(0x7,0xf,0x00)   /* Chip ID */
0018 #define REG_BLADE_ID        CRA(0x7,0xf,0x01)   /* Blade ID */
0019 #define REG_SW_RESET        CRA(0x7,0xf,0x02)   /* Global Soft Reset */
0020 #define REG_MEM_BIST        CRA(0x7,0xf,0x04)   /* mem */
0021 #define REG_IFACE_MODE      CRA(0x7,0xf,0x07)   /* Interface mode */
0022 #define REG_MSCH        CRA(0x7,0x2,0x06)   /* CRC error count */
0023 #define REG_CRC_CNT     CRA(0x7,0x2,0x0a)   /* CRC error count */
0024 #define REG_CRC_CFG     CRA(0x7,0x2,0x0b)   /* CRC config */
0025 #define REG_SI_TRANSFER_SEL CRA(0x7,0xf,0x18)   /* SI Transfer Select */
0026 #define REG_PLL_CLK_SPEED   CRA(0x7,0xf,0x19)   /* Clock Speed Selection */
0027 #define REG_SYS_CLK_SELECT  CRA(0x7,0xf,0x1c)   /* System Clock Select */
0028 #define REG_GPIO_CTRL       CRA(0x7,0xf,0x1d)   /* GPIO Control */
0029 #define REG_GPIO_OUT        CRA(0x7,0xf,0x1e)   /* GPIO Out */
0030 #define REG_GPIO_IN     CRA(0x7,0xf,0x1f)   /* GPIO In */
0031 #define REG_CPU_TRANSFER_SEL    CRA(0x7,0xf,0x20)   /* CPU Transfer Select */
0032 #define REG_LOCAL_DATA      CRA(0x7,0xf,0xfe)   /* Local CPU Data Register */
0033 #define REG_LOCAL_STATUS    CRA(0x7,0xf,0xff)   /* Local CPU Status Register */
0034
0035 /* Aggregator registers */
0036 #define REG_AGGR_SETUP      CRA(0x7,0x1,0x00)   /* Aggregator Setup */
0037 #define REG_PMAP_TABLE      CRA(0x7,0x1,0x01)   /* Port map table */
0038 #define REG_MPLS_BIT0       CRA(0x7,0x1,0x08)   /* MPLS bit0 position */
0039 #define REG_MPLS_BIT1       CRA(0x7,0x1,0x09)   /* MPLS bit1 position */
0040 #define REG_MPLS_BIT2       CRA(0x7,0x1,0x0a)   /* MPLS bit2 position */
0041 #define REG_MPLS_BIT3       CRA(0x7,0x1,0x0b)   /* MPLS bit3 position */
0042 #define REG_MPLS_BITMASK    CRA(0x7,0x1,0x0c)   /* MPLS bit mask */
0043 #define REG_PRE_BIT0POS     CRA(0x7,0x1,0x10)   /* Preamble bit0 position */
0044 #define REG_PRE_BIT1POS     CRA(0x7,0x1,0x11)   /* Preamble bit1 position */
0045 #define REG_PRE_BIT2POS     CRA(0x7,0x1,0x12)   /* Preamble bit2 position */
0046 #define REG_PRE_BIT3POS     CRA(0x7,0x1,0x13)   /* Preamble bit3 position */
0047 #define REG_PRE_ERR_CNT     CRA(0x7,0x1,0x14)   /* Preamble parity error count */
0048
0049 /* BIST registers */
0050 /*#define REG_RAM_BIST_CMD  CRA(0x7,0x2,0x00)*/ /* RAM BIST Command Register */
0051 /*#define REG_RAM_BIST_RESULT   CRA(0x7,0x2,0x01)*/ /* RAM BIST Read Status/Result */
0052 #define REG_RAM_BIST_CMD    CRA(0x7,0x1,0x00)   /* RAM BIST Command Register */
0053 #define REG_RAM_BIST_RESULT CRA(0x7,0x1,0x01)   /* RAM BIST Read Status/Result */
0054 #define   BIST_PORT_SELECT  0x00            /* BIST port select */
0055 #define   BIST_COMMAND      0x01            /* BIST enable/disable */
0056 #define   BIST_STATUS       0x02            /* BIST operation status */
0057 #define   BIST_ERR_CNT_LSB  0x03            /* BIST error count lo 8b */
0058 #define   BIST_ERR_CNT_MSB  0x04            /* BIST error count hi 8b */
0059 #define   BIST_ERR_SEL_LSB  0x05            /* BIST error select lo 8b */
0060 #define   BIST_ERR_SEL_MSB  0x06            /* BIST error select hi 8b */
0061 #define   BIST_ERROR_STATE  0x07            /* BIST engine internal state */
0062 #define   BIST_ERR_ADR0     0x08            /* BIST error address lo 8b */
0063 #define   BIST_ERR_ADR1     0x09            /* BIST error address lomid 8b */
0064 #define   BIST_ERR_ADR2     0x0a            /* BIST error address himid 8b */
0065 #define   BIST_ERR_ADR3     0x0b            /* BIST error address hi 8b */
0066
0067 /* FIFO registers
0068  *   ie = 0 for ingress, 1 for egress
0069  *   fn = FIFO number, 0-9
0070  */
0071 #define REG_TEST(ie,fn)     CRA(0x2,ie&1,0x00+fn)   /* Mode & Test Register */
0072 #define REG_TOP_BOTTOM(ie,fn)   CRA(0x2,ie&1,0x10+fn)   /* FIFO Buffer Top & Bottom */
0073 #define REG_TAIL(ie,fn)     CRA(0x2,ie&1,0x20+fn)   /* FIFO Write Pointer */
0074 #define REG_HEAD(ie,fn)     CRA(0x2,ie&1,0x30+fn)   /* FIFO Read Pointer */
0075 #define REG_HIGH_LOW_WM(ie,fn)  CRA(0x2,ie&1,0x40+fn)   /* Flow Control Water Marks */
0076 #define REG_CT_THRHLD(ie,fn)    CRA(0x2,ie&1,0x50+fn)   /* Cut Through Threshold */
0077 #define REG_FIFO_DROP_CNT(ie,fn) CRA(0x2,ie&1,0x60+fn)  /* Drop & CRC Error Counter */
0078 #define REG_DEBUG_BUF_CNT(ie,fn) CRA(0x2,ie&1,0x70+fn)  /* Input Side Debug Counter */
0079 #define REG_BUCKI(fn) CRA(0x2,2,0x20+fn)    /* Input Side Debug Counter */
0080 #define REG_BUCKE(fn) CRA(0x2,3,0x20+fn)    /* Input Side Debug Counter */
0081
0082 /* Traffic shaper buckets
0083  *   ie = 0 for ingress, 1 for egress
0084  *   bn = bucket number 0-10 (yes, 11 buckets)
0085  */
0086 /* OK, this one's kinda ugly.  Some hardware designers are perverse. */
0087 #define REG_TRAFFIC_SHAPER_BUCKET(ie,bn) CRA(0x2,ie&1,0x0a + (bn>7) | ((bn&7)<<4))
0088 #define REG_TRAFFIC_SHAPER_CONTROL(ie)  CRA(0x2,ie&1,0x3b)
0089
0090 #define REG_SRAM_ADR(ie)    CRA(0x2,ie&1,0x0e)  /* FIFO SRAM address */
0091 #define REG_SRAM_WR_STRB(ie)    CRA(0x2,ie&1,0x1e)  /* FIFO SRAM write strobe */
0092 #define REG_SRAM_RD_STRB(ie)    CRA(0x2,ie&1,0x2e)  /* FIFO SRAM read strobe */
0093 #define REG_SRAM_DATA_0(ie) CRA(0x2,ie&1,0x3e)  /* FIFO SRAM data lo 8b */
0094 #define REG_SRAM_DATA_1(ie) CRA(0x2,ie&1,0x4e)  /* FIFO SRAM data lomid 8b */
0095 #define REG_SRAM_DATA_2(ie) CRA(0x2,ie&1,0x5e)  /* FIFO SRAM data himid 8b */
0096 #define REG_SRAM_DATA_3(ie) CRA(0x2,ie&1,0x6e)  /* FIFO SRAM data hi 8b */
0097 #define REG_SRAM_DATA_BLK_TYPE(ie) CRA(0x2,ie&1,0x7e)   /* FIFO SRAM tag */
0098 /* REG_ING_CONTROL equals REG_CONTROL with ie = 0, likewise REG_EGR_CONTROL is ie = 1 */
0099 #define REG_CONTROL(ie)     CRA(0x2,ie&1,0x0f)  /* FIFO control */
0100 #define REG_ING_CONTROL     CRA(0x2,0x0,0x0f)   /* Ingress control (alias) */
0101 #define REG_EGR_CONTROL     CRA(0x2,0x1,0x0f)   /* Egress control (alias) */
0102 #define REG_AGE_TIMER(ie)   CRA(0x2,ie&1,0x1f)  /* Aging timer */
0103 #define REG_AGE_INC(ie)     CRA(0x2,ie&1,0x2f)  /* Aging increment */
0104 #define DEBUG_OUT(ie)       CRA(0x2,ie&1,0x3f)  /* Output debug counter control */
0105 #define DEBUG_CNT(ie)       CRA(0x2,ie&1,0x4f)  /* Output debug counter */
0106
0107 /* SPI4 interface */
0108 #define REG_SPI4_MISC       CRA(0x5,0x0,0x00)   /* Misc Register */
0109 #define REG_SPI4_STATUS     CRA(0x5,0x0,0x01)   /* CML Status */
0110 #define REG_SPI4_ING_SETUP0 CRA(0x5,0x0,0x02)   /* Ingress Status Channel Setup */
0111 #define REG_SPI4_ING_SETUP1 CRA(0x5,0x0,0x03)   /* Ingress Data Training Setup */
0112 #define REG_SPI4_ING_SETUP2 CRA(0x5,0x0,0x04)   /* Ingress Data Burst Size Setup */
0113 #define REG_SPI4_EGR_SETUP0 CRA(0x5,0x0,0x05)   /* Egress Status Channel Setup */
0114 #define REG_SPI4_DBG_CNT(n) CRA(0x5,0x0,0x10+n) /* Debug counters 0-9 */
0115 #define REG_SPI4_DBG_SETUP  CRA(0x5,0x0,0x1A)   /* Debug counters setup */
0116 #define REG_SPI4_TEST       CRA(0x5,0x0,0x20)   /* Test Setup Register */
0117 #define REG_TPGEN_UP0       CRA(0x5,0x0,0x21)   /* Test Pattern generator user pattern 0 */
0118 #define REG_TPGEN_UP1       CRA(0x5,0x0,0x22)   /* Test Pattern generator user pattern 1 */
0119 #define REG_TPCHK_UP0       CRA(0x5,0x0,0x23)   /* Test Pattern checker user pattern 0 */
0120 #define REG_TPCHK_UP1       CRA(0x5,0x0,0x24)   /* Test Pattern checker user pattern 1 */
0121 #define REG_TPSAM_P0        CRA(0x5,0x0,0x25)   /* Sampled pattern 0 */
0122 #define REG_TPSAM_P1        CRA(0x5,0x0,0x26)   /* Sampled pattern 1 */
0123 #define REG_TPERR_CNT       CRA(0x5,0x0,0x27)   /* Pattern checker error counter */
0124 #define REG_SPI4_STICKY     CRA(0x5,0x0,0x30)   /* Sticky bits register */
0125 #define REG_SPI4_DBG_INH    CRA(0x5,0x0,0x31)   /* Core egress & ingress inhibit */
0126 #define REG_SPI4_DBG_STATUS CRA(0x5,0x0,0x32)   /* Sampled ingress status */
0127 #define REG_SPI4_DBG_GRANT  CRA(0x5,0x0,0x33)   /* Ingress cranted credit value */
0128
0129 #define REG_SPI4_DESKEW     CRA(0x5,0x0,0x43)   /* Ingress cranted credit value */
0130
0131 /* 10GbE MAC Block Registers */
0132 /* Note that those registers that are exactly the same for 10GbE as for
0133  * tri-speed are only defined with the version that needs a port number.
0134  * Pass 0xa in those cases.
0135  *
0136  * Also note that despite the presence of a MAC address register, this part
0137  * does no ingress MAC address filtering.  That register is used only for
0138  * pause frame detection and generation.
0139  */
0140 /* 10GbE specific, and different from tri-speed */
0141 #define REG_MISC_10G        CRA(0x1,0xa,0x00)   /* Misc 10GbE setup */
0142 #define REG_PAUSE_10G       CRA(0x1,0xa,0x01)   /* Pause register */
0143 #define REG_NORMALIZER_10G  CRA(0x1,0xa,0x05)   /* 10G normalizer */
0144 #define REG_STICKY_RX       CRA(0x1,0xa,0x06)   /* RX debug register */
0145 #define REG_DENORM_10G      CRA(0x1,0xa,0x07)   /* Denormalizer  */
0146 #define REG_STICKY_TX       CRA(0x1,0xa,0x08)   /* TX sticky bits */
0147 #define REG_MAX_RXHIGH      CRA(0x1,0xa,0x0a)   /* XGMII lane 0-3 debug */
0148 #define REG_MAX_RXLOW       CRA(0x1,0xa,0x0b)   /* XGMII lane 4-7 debug */
0149 #define REG_MAC_TX_STICKY   CRA(0x1,0xa,0x0c)   /* MAC Tx state sticky debug */
0150 #define REG_MAC_TX_RUNNING  CRA(0x1,0xa,0x0d)   /* MAC Tx state running debug */
0151 #define REG_TX_ABORT_AGE    CRA(0x1,0xa,0x14)   /* Aged Tx frames discarded */
0152 #define REG_TX_ABORT_SHORT  CRA(0x1,0xa,0x15)   /* Short Tx frames discarded */
0153 #define REG_TX_ABORT_TAXI   CRA(0x1,0xa,0x16)   /* Taxi error frames discarded */
0154 #define REG_TX_ABORT_UNDERRUN   CRA(0x1,0xa,0x17)   /* Tx Underrun abort counter */
0155 #define REG_TX_DENORM_DISCARD   CRA(0x1,0xa,0x18)   /* Tx denormalizer discards */
0156 #define REG_XAUI_STAT_A     CRA(0x1,0xa,0x20)   /* XAUI status A */
0157 #define REG_XAUI_STAT_B     CRA(0x1,0xa,0x21)   /* XAUI status B */
0158 #define REG_XAUI_STAT_C     CRA(0x1,0xa,0x22)   /* XAUI status C */
0159 #define REG_XAUI_CONF_A     CRA(0x1,0xa,0x23)   /* XAUI configuration A */
0160 #define REG_XAUI_CONF_B     CRA(0x1,0xa,0x24)   /* XAUI configuration B */
0161 #define REG_XAUI_CODE_GRP_CNT   CRA(0x1,0xa,0x25)   /* XAUI code group error count */
0162 #define REG_XAUI_CONF_TEST_A    CRA(0x1,0xa,0x26)   /* XAUI test register A */
0163 #define REG_PDERRCNT        CRA(0x1,0xa,0x27)   /* XAUI test register B */
0164
0165 /* pn = port number 0-9 for tri-speed, 10 for 10GbE */
0166 /* Both tri-speed and 10GbE */
0167 #define REG_MAX_LEN(pn)     CRA(0x1,pn,0x02)    /* Max length */
0168 #define REG_MAC_HIGH_ADDR(pn)   CRA(0x1,pn,0x03)    /* Upper 24 bits of MAC addr */
0169 #define REG_MAC_LOW_ADDR(pn)    CRA(0x1,pn,0x04)    /* Lower 24 bits of MAC addr */
0170
0171 /* tri-speed only
0172  * pn = port number, 0-9
0173  */
0174 #define REG_MODE_CFG(pn)    CRA(0x1,pn,0x00)    /* Mode configuration */
0175 #define REG_PAUSE_CFG(pn)   CRA(0x1,pn,0x01)    /* Pause configuration */
0176 #define REG_NORMALIZER(pn)  CRA(0x1,pn,0x05)    /* Normalizer */
0177 #define REG_TBI_STATUS(pn)  CRA(0x1,pn,0x06)    /* TBI status */
0178 #define REG_PCS_STATUS_DBG(pn)  CRA(0x1,pn,0x07)    /* PCS status debug */
0179 #define REG_PCS_CTRL(pn)    CRA(0x1,pn,0x08)    /* PCS control */
0180 #define REG_TBI_CONFIG(pn)  CRA(0x1,pn,0x09)    /* TBI configuration */
0181 #define REG_STICK_BIT(pn)   CRA(0x1,pn,0x0a)    /* Sticky bits */
0182 #define REG_DEV_SETUP(pn)   CRA(0x1,pn,0x0b)    /* MAC clock/reset setup */
0183 #define REG_DROP_CNT(pn)    CRA(0x1,pn,0x0c)    /* Drop counter */
0184 #define REG_PORT_POS(pn)    CRA(0x1,pn,0x0d)    /* Preamble port position */
0185 #define REG_PORT_FAIL(pn)   CRA(0x1,pn,0x0e)    /* Preamble port position */
0186 #define REG_SERDES_CONF(pn) CRA(0x1,pn,0x0f)    /* SerDes configuration */
0187 #define REG_SERDES_TEST(pn) CRA(0x1,pn,0x10)    /* SerDes test */
0188 #define REG_SERDES_STAT(pn) CRA(0x1,pn,0x11)    /* SerDes status */
0189 #define REG_SERDES_COM_CNT(pn)  CRA(0x1,pn,0x12)    /* SerDes comma counter */
0190 #define REG_DENORM(pn)      CRA(0x1,pn,0x15)    /* Frame denormalization */
0191 #define REG_DBG(pn)     CRA(0x1,pn,0x16)    /* Device 1G debug */
0192 #define REG_TX_IFG(pn)      CRA(0x1,pn,0x18)    /* Tx IFG config */
0193 #define REG_HDX(pn)     CRA(0x1,pn,0x19)    /* Half-duplex config */
0194
0195 /* Statistics */
0196 /* CRA(0x4,pn,reg) */
0197 /* reg below */
0198 /* pn = port number, 0-a, a = 10GbE */
0199
0200 enum {
0201     RxInBytes       = 0x00, // # Rx in octets
0202     RxSymbolCarrier     = 0x01, // Frames w/ symbol errors
0203     RxPause         = 0x02, // # pause frames received
0204     RxUnsupOpcode       = 0x03, // # control frames with unsupported opcode
0205     RxOkBytes       = 0x04, // # octets in good frames
0206     RxBadBytes      = 0x05, // # octets in bad frames
0207     RxUnicast       = 0x06, // # good unicast frames
0208     RxMulticast     = 0x07, // # good multicast frames
0209     RxBroadcast     = 0x08, // # good broadcast frames
0210     Crc         = 0x09, // # frames w/ bad CRC only
0211     RxAlignment     = 0x0a, // # frames w/ alignment err
0212     RxUndersize     = 0x0b, // # frames undersize
0213     RxFragments     = 0x0c, // # frames undersize w/ crc err
0214     RxInRangeLengthError    = 0x0d, // # frames with length error
0215     RxOutOfRangeError   = 0x0e, // # frames with illegal length field
0216     RxOversize      = 0x0f, // # frames oversize
0217     RxJabbers       = 0x10, // # frames oversize w/ crc err
0218     RxSize64        = 0x11, // # frames 64 octets long
0219     RxSize65To127       = 0x12, // # frames 65-127 octets
0220     RxSize128To255      = 0x13, // # frames 128-255
0221     RxSize256To511      = 0x14, // # frames 256-511
0222     RxSize512To1023     = 0x15, // # frames 512-1023
0223     RxSize1024To1518    = 0x16, // # frames 1024-1518
0224     RxSize1519ToMax     = 0x17, // # frames 1519-max
0225
0226     TxOutBytes      = 0x18, // # octets tx
0227     TxPause         = 0x19, // # pause frames sent
0228     TxOkBytes       = 0x1a, // # octets tx OK
0229     TxUnicast       = 0x1b, // # frames unicast
0230     TxMulticast     = 0x1c, // # frames multicast
0231     TxBroadcast     = 0x1d, // # frames broadcast
0232     TxMultipleColl      = 0x1e, // # frames tx after multiple collisions
0233     TxLateColl      = 0x1f, // # late collisions detected
0234     TxXcoll         = 0x20, // # frames lost, excessive collisions
0235     TxDefer         = 0x21, // # frames deferred on first tx attempt
0236     TxXdefer        = 0x22, // # frames excessively deferred
0237     TxCsense        = 0x23, // carrier sense errors at frame end
0238     TxSize64        = 0x24, // # frames 64 octets long
0239     TxSize65To127       = 0x25, // # frames 65-127 octets
0240     TxSize128To255      = 0x26, // # frames 128-255
0241     TxSize256To511      = 0x27, // # frames 256-511
0242     TxSize512To1023     = 0x28, // # frames 512-1023
0243     TxSize1024To1518    = 0x29, // # frames 1024-1518
0244     TxSize1519ToMax     = 0x2a, // # frames 1519-max
0245     TxSingleColl        = 0x2b, // # frames tx after single collision
0246     TxBackoff2      = 0x2c, // # frames tx ok after 2 backoffs/collisions
0247     TxBackoff3      = 0x2d, //   after 3 backoffs/collisions
0248     TxBackoff4      = 0x2e, //   after 4
0249     TxBackoff5      = 0x2f, //   after 5
0250     TxBackoff6      = 0x30, //   after 6
0251     TxBackoff7      = 0x31, //   after 7
0252     TxBackoff8      = 0x32, //   after 8
0253     TxBackoff9      = 0x33, //   after 9
0254     TxBackoff10     = 0x34, //   after 10
0255     TxBackoff11     = 0x35, //   after 11
0256     TxBackoff12     = 0x36, //   after 12
0257     TxBackoff13     = 0x37, //   after 13
0258     TxBackoff14     = 0x38, //   after 14
0259     TxBackoff15     = 0x39, //   after 15
0260     TxUnderrun      = 0x3a, // # frames dropped from underrun
0261     // Hole. See REG_RX_XGMII_PROT_ERR below.
0262     RxIpgShrink     = 0x3c, // # of IPG shrinks detected
0263     // Duplicate. See REG_STAT_STICKY10G below.
0264     StatSticky1G        = 0x3e, // tri-speed sticky bits
0265     StatInit        = 0x3f  // Clear all statistics
0266 };
0267
0268 #define REG_RX_XGMII_PROT_ERR   CRA(0x4,0xa,0x3b)       /* # protocol errors detected on XGMII interface */
0269 #define REG_STAT_STICKY10G  CRA(0x4,0xa,StatSticky1G)   /* 10GbE sticky bits */
0270
0271 #define REG_RX_OK_BYTES(pn) CRA(0x4,pn,RxOkBytes)
0272 #define REG_RX_BAD_BYTES(pn)    CRA(0x4,pn,RxBadBytes)
0273 #define REG_TX_OK_BYTES(pn) CRA(0x4,pn,TxOkBytes)
0274
0275 /* MII-Management Block registers */
0276 /* These are for MII-M interface 0, which is the bidirectional LVTTL one.  If
0277  * we hooked up to the one with separate directions, the middle 0x0 needs to
0278  * change to 0x1.  And the current errata states that MII-M 1 doesn't work.
0279  */
0280
0281 #define REG_MIIM_STATUS     CRA(0x3,0x0,0x00)   /* MII-M Status */
0282 #define REG_MIIM_CMD        CRA(0x3,0x0,0x01)   /* MII-M Command */
0283 #define REG_MIIM_DATA       CRA(0x3,0x0,0x02)   /* MII-M Data */
0284 #define REG_MIIM_PRESCALE   CRA(0x3,0x0,0x03)   /* MII-M MDC Prescale */
0285
0286 #define REG_ING_FFILT_UM_EN CRA(0x2, 0, 0xd)
0287 #define REG_ING_FFILT_BE_EN CRA(0x2, 0, 0x1d)
0288 #define REG_ING_FFILT_VAL0  CRA(0x2, 0, 0x2d)
0289 #define REG_ING_FFILT_VAL1  CRA(0x2, 0, 0x3d)
0290 #define REG_ING_FFILT_MASK0 CRA(0x2, 0, 0x4d)
0291 #define REG_ING_FFILT_MASK1 CRA(0x2, 0, 0x5d)
0292 #define REG_ING_FFILT_MASK2 CRA(0x2, 0, 0x6d)
0293 #define REG_ING_FFILT_ETYPE CRA(0x2, 0, 0x7d)
0294
0295
0296 /* Whew. */
0297
0298 #endif