chelsio/cxgb/tp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* $Date: 2006/02/07 04:21:54 $ $RCSfile: tp.c,v $ $Revision: 1.73 $ */
0003 #include "common.h"
0004 #include "regs.h"
0005 #include "tp.h"
0006 #ifdef CONFIG_CHELSIO_T1_1G
0007 #include "fpga_defs.h"
0008 #endif
0009
0010 struct petp {
0011     adapter_t *adapter;
0012 };
0013
0014 /* Pause deadlock avoidance parameters */
0015 #define DROP_MSEC 16
0016 #define DROP_PKTS_CNT  1
0017
0018 static void tp_init(adapter_t * ap, const struct tp_params *p,
0019             unsigned int tp_clk)
0020 {
0021     u32 val;
0022
0023     if (!t1_is_asic(ap))
0024         return;
0025
0026     val = F_TP_IN_CSPI_CPL | F_TP_IN_CSPI_CHECK_IP_CSUM |
0027         F_TP_IN_CSPI_CHECK_TCP_CSUM | F_TP_IN_ESPI_ETHERNET;
0028     if (!p->pm_size)
0029         val |= F_OFFLOAD_DISABLE;
0030     else
0031         val |= F_TP_IN_ESPI_CHECK_IP_CSUM | F_TP_IN_ESPI_CHECK_TCP_CSUM;
0032     writel(val, ap->regs + A_TP_IN_CONFIG);
0033     writel(F_TP_OUT_CSPI_CPL |
0034            F_TP_OUT_ESPI_ETHERNET |
0035            F_TP_OUT_ESPI_GENERATE_IP_CSUM |
0036            F_TP_OUT_ESPI_GENERATE_TCP_CSUM, ap->regs + A_TP_OUT_CONFIG);
0037     writel(V_IP_TTL(64) |
0038            F_PATH_MTU /* IP DF bit */  |
0039            V_5TUPLE_LOOKUP(p->use_5tuple_mode) |
0040            V_SYN_COOKIE_PARAMETER(29), ap->regs + A_TP_GLOBAL_CONFIG);
0041     /*
0042      * Enable pause frame deadlock prevention.
0043      */
0044     if (is_T2(ap) && ap->params.nports > 1) {
0045         u32 drop_ticks = DROP_MSEC * (tp_clk / 1000);
0046
0047         writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR |
0048                V_DROP_TICKS_CNT(drop_ticks) |
0049                V_NUM_PKTS_DROPPED(DROP_PKTS_CNT),
0050                ap->regs + A_TP_TX_DROP_CONFIG);
0051     }
0052 }
0053
0054 void t1_tp_destroy(struct petp *tp)
0055 {
0056     kfree(tp);
0057 }
0058
0059 struct petp *t1_tp_create(adapter_t *adapter, struct tp_params *p)
0060 {
0061     struct petp *tp = kzalloc(sizeof(*tp), GFP_KERNEL);
0062
0063     if (!tp)
0064         return NULL;
0065
0066     tp->adapter = adapter;
0067
0068     return tp;
0069 }
0070
0071 void t1_tp_intr_enable(struct petp *tp)
0072 {
0073     u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
0074
0075 #ifdef CONFIG_CHELSIO_T1_1G
0076     if (!t1_is_asic(tp->adapter)) {
0077         /* FPGA */
0078         writel(0xffffffff,
0079                tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
0080         writel(tp_intr | FPGA_PCIX_INTERRUPT_TP,
0081                tp->adapter->regs + A_PL_ENABLE);
0082     } else
0083 #endif
0084     {
0085         /* We don't use any TP interrupts */
0086         writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
0087         writel(tp_intr | F_PL_INTR_TP,
0088                tp->adapter->regs + A_PL_ENABLE);
0089     }
0090 }
0091
0092 void t1_tp_intr_disable(struct petp *tp)
0093 {
0094     u32 tp_intr = readl(tp->adapter->regs + A_PL_ENABLE);
0095
0096 #ifdef CONFIG_CHELSIO_T1_1G
0097     if (!t1_is_asic(tp->adapter)) {
0098         /* FPGA */
0099         writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE);
0100         writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP,
0101                tp->adapter->regs + A_PL_ENABLE);
0102     } else
0103 #endif
0104     {
0105         writel(0, tp->adapter->regs + A_TP_INT_ENABLE);
0106         writel(tp_intr & ~F_PL_INTR_TP,
0107                tp->adapter->regs + A_PL_ENABLE);
0108     }
0109 }
0110
0111 void t1_tp_intr_clear(struct petp *tp)
0112 {
0113 #ifdef CONFIG_CHELSIO_T1_1G
0114     if (!t1_is_asic(tp->adapter)) {
0115         writel(0xffffffff,
0116                tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
0117         writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE);
0118         return;
0119     }
0120 #endif
0121     writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE);
0122     writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE);
0123 }
0124
0125 int t1_tp_intr_handler(struct petp *tp)
0126 {
0127     u32 cause;
0128
0129 #ifdef CONFIG_CHELSIO_T1_1G
0130     /* FPGA doesn't support TP interrupts. */
0131     if (!t1_is_asic(tp->adapter))
0132         return 1;
0133 #endif
0134
0135     cause = readl(tp->adapter->regs + A_TP_INT_CAUSE);
0136     writel(cause, tp->adapter->regs + A_TP_INT_CAUSE);
0137     return 0;
0138 }
0139
0140 static void set_csum_offload(struct petp *tp, u32 csum_bit, int enable)
0141 {
0142     u32 val = readl(tp->adapter->regs + A_TP_GLOBAL_CONFIG);
0143
0144     if (enable)
0145         val |= csum_bit;
0146     else
0147         val &= ~csum_bit;
0148     writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG);
0149 }
0150
0151 void t1_tp_set_ip_checksum_offload(struct petp *tp, int enable)
0152 {
0153     set_csum_offload(tp, F_IP_CSUM, enable);
0154 }
0155
0156 void t1_tp_set_tcp_checksum_offload(struct petp *tp, int enable)
0157 {
0158     set_csum_offload(tp, F_TCP_CSUM, enable);
0159 }
0160
0161 /*
0162  * Initialize TP state.  tp_params contains initial settings for some TP
0163  * parameters, particularly the one-time PM and CM settings.
0164  */
0165 int t1_tp_reset(struct petp *tp, struct tp_params *p, unsigned int tp_clk)
0166 {
0167     adapter_t *adapter = tp->adapter;
0168
0169     tp_init(adapter, p, tp_clk);
0170     writel(F_TP_RESET, adapter->regs +  A_TP_RESET);
0171     return 0;
0172 }