chelsio/cxgb/mv88e1xxx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* $Date: 2005/03/07 23:59:05 $ $RCSfile: mv88e1xxx.h,v $ $Revision: 1.13 $ */
0003 #ifndef CHELSIO_MV8E1XXX_H
0004 #define CHELSIO_MV8E1XXX_H
0005
0006 #ifndef BMCR_SPEED1000
0007 # define BMCR_SPEED1000 0x40
0008 #endif
0009
0010 #ifndef ADVERTISE_PAUSE
0011 # define ADVERTISE_PAUSE 0x400
0012 #endif
0013 #ifndef ADVERTISE_PAUSE_ASYM
0014 # define ADVERTISE_PAUSE_ASYM 0x800
0015 #endif
0016
0017 /* Gigabit MII registers */
0018 #define MII_GBCR 9       /* 1000Base-T control register */
0019 #define MII_GBSR 10      /* 1000Base-T status register */
0020
0021 /* 1000Base-T control register fields */
0022 #define GBCR_ADV_1000HALF         0x100
0023 #define GBCR_ADV_1000FULL         0x200
0024 #define GBCR_PREFER_MASTER        0x400
0025 #define GBCR_MANUAL_AS_MASTER     0x800
0026 #define GBCR_MANUAL_CONFIG_ENABLE 0x1000
0027
0028 /* 1000Base-T status register fields */
0029 #define GBSR_LP_1000HALF  0x400
0030 #define GBSR_LP_1000FULL  0x800
0031 #define GBSR_REMOTE_OK    0x1000
0032 #define GBSR_LOCAL_OK     0x2000
0033 #define GBSR_LOCAL_MASTER 0x4000
0034 #define GBSR_MASTER_FAULT 0x8000
0035
0036 /* Marvell PHY interrupt status bits. */
0037 #define MV88E1XXX_INTR_JABBER          0x0001
0038 #define MV88E1XXX_INTR_POLARITY_CHNG   0x0002
0039 #define MV88E1XXX_INTR_ENG_DETECT_CHNG 0x0010
0040 #define MV88E1XXX_INTR_DOWNSHIFT       0x0020
0041 #define MV88E1XXX_INTR_MDI_XOVER_CHNG  0x0040
0042 #define MV88E1XXX_INTR_FIFO_OVER_UNDER 0x0080
0043 #define MV88E1XXX_INTR_FALSE_CARRIER   0x0100
0044 #define MV88E1XXX_INTR_SYMBOL_ERROR    0x0200
0045 #define MV88E1XXX_INTR_LINK_CHNG       0x0400
0046 #define MV88E1XXX_INTR_AUTONEG_DONE    0x0800
0047 #define MV88E1XXX_INTR_PAGE_RECV       0x1000
0048 #define MV88E1XXX_INTR_DUPLEX_CHNG     0x2000
0049 #define MV88E1XXX_INTR_SPEED_CHNG      0x4000
0050 #define MV88E1XXX_INTR_AUTONEG_ERR     0x8000
0051
0052 /* Marvell PHY specific registers. */
0053 #define MV88E1XXX_SPECIFIC_CNTRL_REGISTER               16
0054 #define MV88E1XXX_SPECIFIC_STATUS_REGISTER              17
0055 #define MV88E1XXX_INTERRUPT_ENABLE_REGISTER             18
0056 #define MV88E1XXX_INTERRUPT_STATUS_REGISTER             19
0057 #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER       20
0058 #define MV88E1XXX_RECV_ERR_CNTR_REGISTER                21
0059 #define MV88E1XXX_RES_REGISTER                          22
0060 #define MV88E1XXX_GLOBAL_STATUS_REGISTER                23
0061 #define MV88E1XXX_LED_CONTROL_REGISTER                  24
0062 #define MV88E1XXX_MANUAL_LED_OVERRIDE_REGISTER          25
0063 #define MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_2_REGISTER     26
0064 #define MV88E1XXX_EXT_PHY_SPECIFIC_STATUS_REGISTER      27
0065 #define MV88E1XXX_VIRTUAL_CABLE_TESTER_REGISTER         28
0066 #define MV88E1XXX_EXTENDED_ADDR_REGISTER                29
0067 #define MV88E1XXX_EXTENDED_REGISTER                     30
0068
0069 /* PHY specific control register fields */
0070 #define S_PSCR_MDI_XOVER_MODE    5
0071 #define M_PSCR_MDI_XOVER_MODE    0x3
0072 #define V_PSCR_MDI_XOVER_MODE(x) ((x) << S_PSCR_MDI_XOVER_MODE)
0073 #define G_PSCR_MDI_XOVER_MODE(x) (((x) >> S_PSCR_MDI_XOVER_MODE) & M_PSCR_MDI_XOVER_MODE)
0074
0075 /* Extended PHY specific control register fields */
0076 #define S_DOWNSHIFT_ENABLE 8
0077 #define V_DOWNSHIFT_ENABLE (1 << S_DOWNSHIFT_ENABLE)
0078
0079 #define S_DOWNSHIFT_CNT    9
0080 #define M_DOWNSHIFT_CNT    0x7
0081 #define V_DOWNSHIFT_CNT(x) ((x) << S_DOWNSHIFT_CNT)
0082 #define G_DOWNSHIFT_CNT(x) (((x) >> S_DOWNSHIFT_CNT) & M_DOWNSHIFT_CNT)
0083
0084 /* PHY specific status register fields */
0085 #define S_PSSR_JABBER 0
0086 #define V_PSSR_JABBER (1 << S_PSSR_JABBER)
0087
0088 #define S_PSSR_POLARITY 1
0089 #define V_PSSR_POLARITY (1 << S_PSSR_POLARITY)
0090
0091 #define S_PSSR_RX_PAUSE 2
0092 #define V_PSSR_RX_PAUSE (1 << S_PSSR_RX_PAUSE)
0093
0094 #define S_PSSR_TX_PAUSE 3
0095 #define V_PSSR_TX_PAUSE (1 << S_PSSR_TX_PAUSE)
0096
0097 #define S_PSSR_ENERGY_DETECT 4
0098 #define V_PSSR_ENERGY_DETECT (1 << S_PSSR_ENERGY_DETECT)
0099
0100 #define S_PSSR_DOWNSHIFT_STATUS 5
0101 #define V_PSSR_DOWNSHIFT_STATUS (1 << S_PSSR_DOWNSHIFT_STATUS)
0102
0103 #define S_PSSR_MDI 6
0104 #define V_PSSR_MDI (1 << S_PSSR_MDI)
0105
0106 #define S_PSSR_CABLE_LEN    7
0107 #define M_PSSR_CABLE_LEN    0x7
0108 #define V_PSSR_CABLE_LEN(x) ((x) << S_PSSR_CABLE_LEN)
0109 #define G_PSSR_CABLE_LEN(x) (((x) >> S_PSSR_CABLE_LEN) & M_PSSR_CABLE_LEN)
0110
0111 #define S_PSSR_LINK 10
0112 #define V_PSSR_LINK (1 << S_PSSR_LINK)
0113
0114 #define S_PSSR_STATUS_RESOLVED 11
0115 #define V_PSSR_STATUS_RESOLVED (1 << S_PSSR_STATUS_RESOLVED)
0116
0117 #define S_PSSR_PAGE_RECEIVED 12
0118 #define V_PSSR_PAGE_RECEIVED (1 << S_PSSR_PAGE_RECEIVED)
0119
0120 #define S_PSSR_DUPLEX 13
0121 #define V_PSSR_DUPLEX (1 << S_PSSR_DUPLEX)
0122
0123 #define S_PSSR_SPEED    14
0124 #define M_PSSR_SPEED    0x3
0125 #define V_PSSR_SPEED(x) ((x) << S_PSSR_SPEED)
0126 #define G_PSSR_SPEED(x) (((x) >> S_PSSR_SPEED) & M_PSSR_SPEED)
0127
0128 #endif