chelsio/cxgb/mv88e1xxx.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* $Date: 2005/10/24 23:18:13 $ $RCSfile: mv88e1xxx.c,v $ $Revision: 1.49 $ */
0003 #include "common.h"
0004 #include "mv88e1xxx.h"
0005 #include "cphy.h"
0006 #include "elmer0.h"
0007
0008 /* MV88E1XXX MDI crossover register values */
0009 #define CROSSOVER_MDI   0
0010 #define CROSSOVER_MDIX  1
0011 #define CROSSOVER_AUTO  3
0012
0013 #define INTR_ENABLE_MASK 0x6CA0
0014
0015 /*
0016  * Set the bits given by 'bitval' in PHY register 'reg'.
0017  */
0018 static void mdio_set_bit(struct cphy *cphy, int reg, u32 bitval)
0019 {
0020     u32 val;
0021
0022     (void) simple_mdio_read(cphy, reg, &val);
0023     (void) simple_mdio_write(cphy, reg, val | bitval);
0024 }
0025
0026 /*
0027  * Clear the bits given by 'bitval' in PHY register 'reg'.
0028  */
0029 static void mdio_clear_bit(struct cphy *cphy, int reg, u32 bitval)
0030 {
0031     u32 val;
0032
0033     (void) simple_mdio_read(cphy, reg, &val);
0034     (void) simple_mdio_write(cphy, reg, val & ~bitval);
0035 }
0036
0037 /*
0038  * NAME:   phy_reset
0039  *
0040  * DESC:   Reset the given PHY's port. NOTE: This is not a global
0041  *         chip reset.
0042  *
0043  * PARAMS: cphy     - Pointer to PHY instance data.
0044  *
0045  * RETURN:  0 - Successful reset.
0046  *         -1 - Timeout.
0047  */
0048 static int mv88e1xxx_reset(struct cphy *cphy, int wait)
0049 {
0050     u32 ctl;
0051     int time_out = 1000;
0052
0053     mdio_set_bit(cphy, MII_BMCR, BMCR_RESET);
0054
0055     do {
0056         (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
0057         ctl &= BMCR_RESET;
0058         if (ctl)
0059             udelay(1);
0060     } while (ctl && --time_out);
0061
0062     return ctl ? -1 : 0;
0063 }
0064
0065 static int mv88e1xxx_interrupt_enable(struct cphy *cphy)
0066 {
0067     /* Enable PHY interrupts. */
0068     (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER,
0069            INTR_ENABLE_MASK);
0070
0071     /* Enable Marvell interrupts through Elmer0. */
0072     if (t1_is_asic(cphy->adapter)) {
0073         u32 elmer;
0074
0075         t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
0076         elmer |= ELMER0_GP_BIT1;
0077         if (is_T2(cphy->adapter))
0078             elmer |= ELMER0_GP_BIT2 | ELMER0_GP_BIT3 | ELMER0_GP_BIT4;
0079         t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
0080     }
0081     return 0;
0082 }
0083
0084 static int mv88e1xxx_interrupt_disable(struct cphy *cphy)
0085 {
0086     /* Disable all phy interrupts. */
0087     (void) simple_mdio_write(cphy, MV88E1XXX_INTERRUPT_ENABLE_REGISTER, 0);
0088
0089     /* Disable Marvell interrupts through Elmer0. */
0090     if (t1_is_asic(cphy->adapter)) {
0091         u32 elmer;
0092
0093         t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
0094         elmer &= ~ELMER0_GP_BIT1;
0095         if (is_T2(cphy->adapter))
0096             elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4);
0097         t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
0098     }
0099     return 0;
0100 }
0101
0102 static int mv88e1xxx_interrupt_clear(struct cphy *cphy)
0103 {
0104     u32 elmer;
0105
0106     /* Clear PHY interrupts by reading the register. */
0107     (void) simple_mdio_read(cphy,
0108             MV88E1XXX_INTERRUPT_STATUS_REGISTER, &elmer);
0109
0110     /* Clear Marvell interrupts through Elmer0. */
0111     if (t1_is_asic(cphy->adapter)) {
0112         t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
0113         elmer |= ELMER0_GP_BIT1;
0114         if (is_T2(cphy->adapter))
0115             elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
0116         t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
0117     }
0118     return 0;
0119 }
0120
0121 /*
0122  * Set the PHY speed and duplex.  This also disables auto-negotiation, except
0123  * for 1Gb/s, where auto-negotiation is mandatory.
0124  */
0125 static int mv88e1xxx_set_speed_duplex(struct cphy *phy, int speed, int duplex)
0126 {
0127     u32 ctl;
0128
0129     (void) simple_mdio_read(phy, MII_BMCR, &ctl);
0130     if (speed >= 0) {
0131         ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
0132         if (speed == SPEED_100)
0133             ctl |= BMCR_SPEED100;
0134         else if (speed == SPEED_1000)
0135             ctl |= BMCR_SPEED1000;
0136     }
0137     if (duplex >= 0) {
0138         ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
0139         if (duplex == DUPLEX_FULL)
0140             ctl |= BMCR_FULLDPLX;
0141     }
0142     if (ctl & BMCR_SPEED1000)  /* auto-negotiation required for 1Gb/s */
0143         ctl |= BMCR_ANENABLE;
0144     (void) simple_mdio_write(phy, MII_BMCR, ctl);
0145     return 0;
0146 }
0147
0148 static int mv88e1xxx_crossover_set(struct cphy *cphy, int crossover)
0149 {
0150     u32 data32;
0151
0152     (void) simple_mdio_read(cphy,
0153             MV88E1XXX_SPECIFIC_CNTRL_REGISTER, &data32);
0154     data32 &= ~V_PSCR_MDI_XOVER_MODE(M_PSCR_MDI_XOVER_MODE);
0155     data32 |= V_PSCR_MDI_XOVER_MODE(crossover);
0156     (void) simple_mdio_write(cphy,
0157             MV88E1XXX_SPECIFIC_CNTRL_REGISTER, data32);
0158     return 0;
0159 }
0160
0161 static int mv88e1xxx_autoneg_enable(struct cphy *cphy)
0162 {
0163     u32 ctl;
0164
0165     (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_AUTO);
0166
0167     (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
0168     /* restart autoneg for change to take effect */
0169     ctl |= BMCR_ANENABLE | BMCR_ANRESTART;
0170     (void) simple_mdio_write(cphy, MII_BMCR, ctl);
0171     return 0;
0172 }
0173
0174 static int mv88e1xxx_autoneg_disable(struct cphy *cphy)
0175 {
0176     u32 ctl;
0177
0178     /*
0179      * Crossover *must* be set to manual in order to disable auto-neg.
0180      * The Alaska FAQs document highlights this point.
0181      */
0182     (void) mv88e1xxx_crossover_set(cphy, CROSSOVER_MDI);
0183
0184     /*
0185      * Must include autoneg reset when disabling auto-neg. This
0186      * is described in the Alaska FAQ document.
0187      */
0188     (void) simple_mdio_read(cphy, MII_BMCR, &ctl);
0189     ctl &= ~BMCR_ANENABLE;
0190     (void) simple_mdio_write(cphy, MII_BMCR, ctl | BMCR_ANRESTART);
0191     return 0;
0192 }
0193
0194 static int mv88e1xxx_autoneg_restart(struct cphy *cphy)
0195 {
0196     mdio_set_bit(cphy, MII_BMCR, BMCR_ANRESTART);
0197     return 0;
0198 }
0199
0200 static int mv88e1xxx_advertise(struct cphy *phy, unsigned int advertise_map)
0201 {
0202     u32 val = 0;
0203
0204     if (advertise_map &
0205         (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
0206         (void) simple_mdio_read(phy, MII_GBCR, &val);
0207         val &= ~(GBCR_ADV_1000HALF | GBCR_ADV_1000FULL);
0208         if (advertise_map & ADVERTISED_1000baseT_Half)
0209             val |= GBCR_ADV_1000HALF;
0210         if (advertise_map & ADVERTISED_1000baseT_Full)
0211             val |= GBCR_ADV_1000FULL;
0212     }
0213     (void) simple_mdio_write(phy, MII_GBCR, val);
0214
0215     val = 1;
0216     if (advertise_map & ADVERTISED_10baseT_Half)
0217         val |= ADVERTISE_10HALF;
0218     if (advertise_map & ADVERTISED_10baseT_Full)
0219         val |= ADVERTISE_10FULL;
0220     if (advertise_map & ADVERTISED_100baseT_Half)
0221         val |= ADVERTISE_100HALF;
0222     if (advertise_map & ADVERTISED_100baseT_Full)
0223         val |= ADVERTISE_100FULL;
0224     if (advertise_map & ADVERTISED_PAUSE)
0225         val |= ADVERTISE_PAUSE;
0226     if (advertise_map & ADVERTISED_ASYM_PAUSE)
0227         val |= ADVERTISE_PAUSE_ASYM;
0228     (void) simple_mdio_write(phy, MII_ADVERTISE, val);
0229     return 0;
0230 }
0231
0232 static int mv88e1xxx_set_loopback(struct cphy *cphy, int on)
0233 {
0234     if (on)
0235         mdio_set_bit(cphy, MII_BMCR, BMCR_LOOPBACK);
0236     else
0237         mdio_clear_bit(cphy, MII_BMCR, BMCR_LOOPBACK);
0238     return 0;
0239 }
0240
0241 static int mv88e1xxx_get_link_status(struct cphy *cphy, int *link_ok,
0242                      int *speed, int *duplex, int *fc)
0243 {
0244     u32 status;
0245     int sp = -1, dplx = -1, pause = 0;
0246
0247     (void) simple_mdio_read(cphy,
0248             MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status);
0249     if ((status & V_PSSR_STATUS_RESOLVED) != 0) {
0250         if (status & V_PSSR_RX_PAUSE)
0251             pause |= PAUSE_RX;
0252         if (status & V_PSSR_TX_PAUSE)
0253             pause |= PAUSE_TX;
0254         dplx = (status & V_PSSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
0255         sp = G_PSSR_SPEED(status);
0256         if (sp == 0)
0257             sp = SPEED_10;
0258         else if (sp == 1)
0259             sp = SPEED_100;
0260         else
0261             sp = SPEED_1000;
0262     }
0263     if (link_ok)
0264         *link_ok = (status & V_PSSR_LINK) != 0;
0265     if (speed)
0266         *speed = sp;
0267     if (duplex)
0268         *duplex = dplx;
0269     if (fc)
0270         *fc = pause;
0271     return 0;
0272 }
0273
0274 static int mv88e1xxx_downshift_set(struct cphy *cphy, int downshift_enable)
0275 {
0276     u32 val;
0277
0278     (void) simple_mdio_read(cphy,
0279         MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, &val);
0280
0281     /*
0282      * Set the downshift counter to 2 so we try to establish Gb link
0283      * twice before downshifting.
0284      */
0285     val &= ~(V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(M_DOWNSHIFT_CNT));
0286
0287     if (downshift_enable)
0288         val |= V_DOWNSHIFT_ENABLE | V_DOWNSHIFT_CNT(2);
0289     (void) simple_mdio_write(cphy,
0290             MV88E1XXX_EXT_PHY_SPECIFIC_CNTRL_REGISTER, val);
0291     return 0;
0292 }
0293
0294 static int mv88e1xxx_interrupt_handler(struct cphy *cphy)
0295 {
0296     int cphy_cause = 0;
0297     u32 status;
0298
0299     /*
0300      * Loop until cause reads zero. Need to handle bouncing interrupts.
0301      */
0302     while (1) {
0303         u32 cause;
0304
0305         (void) simple_mdio_read(cphy,
0306                 MV88E1XXX_INTERRUPT_STATUS_REGISTER,
0307                 &cause);
0308         cause &= INTR_ENABLE_MASK;
0309         if (!cause)
0310             break;
0311
0312         if (cause & MV88E1XXX_INTR_LINK_CHNG) {
0313             (void) simple_mdio_read(cphy,
0314                 MV88E1XXX_SPECIFIC_STATUS_REGISTER, &status);
0315
0316             if (status & MV88E1XXX_INTR_LINK_CHNG)
0317                 cphy->state |= PHY_LINK_UP;
0318             else {
0319                 cphy->state &= ~PHY_LINK_UP;
0320                 if (cphy->state & PHY_AUTONEG_EN)
0321                     cphy->state &= ~PHY_AUTONEG_RDY;
0322                 cphy_cause |= cphy_cause_link_change;
0323             }
0324         }
0325
0326         if (cause & MV88E1XXX_INTR_AUTONEG_DONE)
0327             cphy->state |= PHY_AUTONEG_RDY;
0328
0329         if ((cphy->state & (PHY_LINK_UP | PHY_AUTONEG_RDY)) ==
0330             (PHY_LINK_UP | PHY_AUTONEG_RDY))
0331                 cphy_cause |= cphy_cause_link_change;
0332     }
0333     return cphy_cause;
0334 }
0335
0336 static void mv88e1xxx_destroy(struct cphy *cphy)
0337 {
0338     kfree(cphy);
0339 }
0340
0341 static const struct cphy_ops mv88e1xxx_ops = {
0342     .destroy              = mv88e1xxx_destroy,
0343     .reset                = mv88e1xxx_reset,
0344     .interrupt_enable     = mv88e1xxx_interrupt_enable,
0345     .interrupt_disable    = mv88e1xxx_interrupt_disable,
0346     .interrupt_clear      = mv88e1xxx_interrupt_clear,
0347     .interrupt_handler    = mv88e1xxx_interrupt_handler,
0348     .autoneg_enable       = mv88e1xxx_autoneg_enable,
0349     .autoneg_disable      = mv88e1xxx_autoneg_disable,
0350     .autoneg_restart      = mv88e1xxx_autoneg_restart,
0351     .advertise            = mv88e1xxx_advertise,
0352     .set_loopback         = mv88e1xxx_set_loopback,
0353     .set_speed_duplex     = mv88e1xxx_set_speed_duplex,
0354     .get_link_status      = mv88e1xxx_get_link_status,
0355 };
0356
0357 static struct cphy *mv88e1xxx_phy_create(struct net_device *dev, int phy_addr,
0358                      const struct mdio_ops *mdio_ops)
0359 {
0360     struct adapter *adapter = netdev_priv(dev);
0361     struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL);
0362
0363     if (!cphy)
0364         return NULL;
0365
0366     cphy_init(cphy, dev, phy_addr, &mv88e1xxx_ops, mdio_ops);
0367
0368     /* Configure particular PHY's to run in a different mode. */
0369     if ((board_info(adapter)->caps & SUPPORTED_TP) &&
0370         board_info(adapter)->chip_phy == CHBT_PHY_88E1111) {
0371         /*
0372          * Configure the PHY transmitter as class A to reduce EMI.
0373          */
0374         (void) simple_mdio_write(cphy,
0375                 MV88E1XXX_EXTENDED_ADDR_REGISTER, 0xB);
0376         (void) simple_mdio_write(cphy,
0377                 MV88E1XXX_EXTENDED_REGISTER, 0x8004);
0378     }
0379     (void) mv88e1xxx_downshift_set(cphy, 1);   /* Enable downshift */
0380
0381     /* LED */
0382     if (is_T2(adapter)) {
0383         (void) simple_mdio_write(cphy,
0384                 MV88E1XXX_LED_CONTROL_REGISTER, 0x1);
0385     }
0386
0387     return cphy;
0388 }
0389
0390 static int mv88e1xxx_phy_reset(adapter_t* adapter)
0391 {
0392     return 0;
0393 }
0394
0395 const struct gphy t1_mv88e1xxx_ops = {
0396     .create = mv88e1xxx_phy_create,
0397     .reset =  mv88e1xxx_phy_reset
0398 };