Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*****************************************************************************
0003  *                                                                           *
0004  * File: espi.c                                                              *
0005  * $Revision: 1.14 $                                                         *
0006  * $Date: 2005/05/14 00:59:32 $                                              *
0007  * Description:                                                              *
0008  *  Ethernet SPI functionality.                                              *
0009  *  part of the Chelsio 10Gb Ethernet Driver.                                *
0010  *                                                                           *
0011  *                                                                           *
0012  * http://www.chelsio.com                                                    *
0013  *                                                                           *
0014  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
0015  * All rights reserved.                                                      *
0016  *                                                                           *
0017  * Maintainers: maintainers@chelsio.com                                      *
0018  *                                                                           *
0019  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
0020  *          Tina Yang               <tainay@chelsio.com>                     *
0021  *          Felix Marti             <felix@chelsio.com>                      *
0022  *          Scott Bardone           <sbardone@chelsio.com>                   *
0023  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
0024  *          Frank DiMambro          <frank@chelsio.com>                      *
0025  *                                                                           *
0026  * History:                                                                  *
0027  *                                                                           *
0028  ****************************************************************************/
0029 
0030 #include "common.h"
0031 #include "regs.h"
0032 #include "espi.h"
0033 
0034 struct peespi {
0035     adapter_t *adapter;
0036     struct espi_intr_counts intr_cnt;
0037     u32 misc_ctrl;
0038     spinlock_t lock;
0039 };
0040 
0041 #define ESPI_INTR_MASK (F_DIP4ERR | F_RXDROP | F_TXDROP | F_RXOVERFLOW | \
0042             F_RAMPARITYERR | F_DIP2PARITYERR)
0043 #define MON_MASK  (V_MONITORED_PORT_NUM(3) | F_MONITORED_DIRECTION \
0044            | F_MONITORED_INTERFACE)
0045 
0046 #define TRICN_CNFG 14
0047 #define TRICN_CMD_READ  0x11
0048 #define TRICN_CMD_WRITE 0x21
0049 #define TRICN_CMD_ATTEMPTS 10
0050 
0051 static int tricn_write(adapter_t *adapter, int bundle_addr, int module_addr,
0052                int ch_addr, int reg_offset, u32 wr_data)
0053 {
0054     int busy, attempts = TRICN_CMD_ATTEMPTS;
0055 
0056     writel(V_WRITE_DATA(wr_data) |
0057            V_REGISTER_OFFSET(reg_offset) |
0058            V_CHANNEL_ADDR(ch_addr) | V_MODULE_ADDR(module_addr) |
0059            V_BUNDLE_ADDR(bundle_addr) |
0060            V_SPI4_COMMAND(TRICN_CMD_WRITE),
0061            adapter->regs + A_ESPI_CMD_ADDR);
0062     writel(0, adapter->regs + A_ESPI_GOSTAT);
0063 
0064     do {
0065         busy = readl(adapter->regs + A_ESPI_GOSTAT) & F_ESPI_CMD_BUSY;
0066     } while (busy && --attempts);
0067 
0068     if (busy)
0069         pr_err("%s: TRICN write timed out\n", adapter->name);
0070 
0071     return busy;
0072 }
0073 
0074 static int tricn_init(adapter_t *adapter)
0075 {
0076     int i, sme = 1;
0077 
0078     if (!(readl(adapter->regs + A_ESPI_RX_RESET)  & F_RX_CLK_STATUS)) {
0079         pr_err("%s: ESPI clock not ready\n", adapter->name);
0080         return -1;
0081     }
0082 
0083     writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET);
0084 
0085     if (sme) {
0086         tricn_write(adapter, 0, 0, 0, TRICN_CNFG, 0x81);
0087         tricn_write(adapter, 0, 1, 0, TRICN_CNFG, 0x81);
0088         tricn_write(adapter, 0, 2, 0, TRICN_CNFG, 0x81);
0089     }
0090     for (i = 1; i <= 8; i++)
0091         tricn_write(adapter, 0, 0, i, TRICN_CNFG, 0xf1);
0092     for (i = 1; i <= 2; i++)
0093         tricn_write(adapter, 0, 1, i, TRICN_CNFG, 0xf1);
0094     for (i = 1; i <= 3; i++)
0095         tricn_write(adapter, 0, 2, i, TRICN_CNFG, 0xe1);
0096     tricn_write(adapter, 0, 2, 4, TRICN_CNFG, 0xf1);
0097     tricn_write(adapter, 0, 2, 5, TRICN_CNFG, 0xe1);
0098     tricn_write(adapter, 0, 2, 6, TRICN_CNFG, 0xf1);
0099     tricn_write(adapter, 0, 2, 7, TRICN_CNFG, 0x80);
0100     tricn_write(adapter, 0, 2, 8, TRICN_CNFG, 0xf1);
0101 
0102     writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST,
0103            adapter->regs + A_ESPI_RX_RESET);
0104 
0105     return 0;
0106 }
0107 
0108 void t1_espi_intr_enable(struct peespi *espi)
0109 {
0110     u32 enable, pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
0111 
0112     /*
0113      * Cannot enable ESPI interrupts on T1B because HW asserts the
0114      * interrupt incorrectly, namely the driver gets ESPI interrupts
0115      * but no data is actually dropped (can verify this reading the ESPI
0116      * drop registers).  Also, once the ESPI interrupt is asserted it
0117      * cannot be cleared (HW bug).
0118      */
0119     enable = t1_is_T1B(espi->adapter) ? 0 : ESPI_INTR_MASK;
0120     writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE);
0121     writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
0122 }
0123 
0124 void t1_espi_intr_clear(struct peespi *espi)
0125 {
0126     readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
0127     writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS);
0128     writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE);
0129 }
0130 
0131 void t1_espi_intr_disable(struct peespi *espi)
0132 {
0133     u32 pl_intr = readl(espi->adapter->regs + A_PL_ENABLE);
0134 
0135     writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE);
0136     writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE);
0137 }
0138 
0139 int t1_espi_intr_handler(struct peespi *espi)
0140 {
0141     u32 status = readl(espi->adapter->regs + A_ESPI_INTR_STATUS);
0142 
0143     if (status & F_DIP4ERR)
0144         espi->intr_cnt.DIP4_err++;
0145     if (status & F_RXDROP)
0146         espi->intr_cnt.rx_drops++;
0147     if (status & F_TXDROP)
0148         espi->intr_cnt.tx_drops++;
0149     if (status & F_RXOVERFLOW)
0150         espi->intr_cnt.rx_ovflw++;
0151     if (status & F_RAMPARITYERR)
0152         espi->intr_cnt.parity_err++;
0153     if (status & F_DIP2PARITYERR) {
0154         espi->intr_cnt.DIP2_parity_err++;
0155 
0156         /*
0157          * Must read the error count to clear the interrupt
0158          * that it causes.
0159          */
0160         readl(espi->adapter->regs + A_ESPI_DIP2_ERR_COUNT);
0161     }
0162 
0163     /*
0164      * For T1B we need to write 1 to clear ESPI interrupts.  For T2+ we
0165      * write the status as is.
0166      */
0167     if (status && t1_is_T1B(espi->adapter))
0168         status = 1;
0169     writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS);
0170     return 0;
0171 }
0172 
0173 const struct espi_intr_counts *t1_espi_get_intr_counts(struct peespi *espi)
0174 {
0175     return &espi->intr_cnt;
0176 }
0177 
0178 static void espi_setup_for_pm3393(adapter_t *adapter)
0179 {
0180     u32 wmark = t1_is_T1B(adapter) ? 0x4000 : 0x3200;
0181 
0182     writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
0183     writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1);
0184     writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
0185     writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3);
0186     writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
0187     writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
0188     writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH);
0189     writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
0190     writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG);
0191 }
0192 
0193 static void espi_setup_for_vsc7321(adapter_t *adapter)
0194 {
0195     writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0);
0196     writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1);
0197     writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2);
0198     writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
0199     writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
0200     writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
0201     writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG);
0202 
0203     writel(0x08000008, adapter->regs + A_ESPI_TRAIN);
0204 }
0205 
0206 /*
0207  * Note that T1B requires at least 2 ports for IXF1010 due to a HW bug.
0208  */
0209 static void espi_setup_for_ixf1010(adapter_t *adapter, int nports)
0210 {
0211     writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH);
0212     if (nports == 4) {
0213         if (is_T2(adapter)) {
0214             writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
0215             writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
0216         } else {
0217             writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
0218             writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
0219         }
0220     } else {
0221         writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK);
0222         writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK);
0223     }
0224     writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG);
0225 
0226 }
0227 
0228 int t1_espi_init(struct peespi *espi, int mac_type, int nports)
0229 {
0230     u32 status_enable_extra = 0;
0231     adapter_t *adapter = espi->adapter;
0232 
0233     /* Disable ESPI training.  MACs that can handle it enable it below. */
0234     writel(0, adapter->regs + A_ESPI_TRAIN);
0235 
0236     if (is_T2(adapter)) {
0237         writel(V_OUT_OF_SYNC_COUNT(4) |
0238                V_DIP2_PARITY_ERR_THRES(3) |
0239                V_DIP4_THRES(1), adapter->regs + A_ESPI_MISC_CONTROL);
0240         writel(nports == 4 ? 0x200040 : 0x1000080,
0241                adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
0242     } else
0243         writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2);
0244 
0245     if (mac_type == CHBT_MAC_PM3393)
0246         espi_setup_for_pm3393(adapter);
0247     else if (mac_type == CHBT_MAC_VSC7321)
0248         espi_setup_for_vsc7321(adapter);
0249     else if (mac_type == CHBT_MAC_IXF1010) {
0250         status_enable_extra = F_INTEL1010MODE;
0251         espi_setup_for_ixf1010(adapter, nports);
0252     } else
0253         return -1;
0254 
0255     writel(status_enable_extra | F_RXSTATUSENABLE,
0256            adapter->regs + A_ESPI_FIFO_STATUS_ENABLE);
0257 
0258     if (is_T2(adapter)) {
0259         tricn_init(adapter);
0260         /*
0261          * Always position the control at the 1st port egress IN
0262          * (sop,eop) counter to reduce PIOs for T/N210 workaround.
0263          */
0264         espi->misc_ctrl = readl(adapter->regs + A_ESPI_MISC_CONTROL);
0265         espi->misc_ctrl &= ~MON_MASK;
0266         espi->misc_ctrl |= F_MONITORED_DIRECTION;
0267         if (adapter->params.nports == 1)
0268             espi->misc_ctrl |= F_MONITORED_INTERFACE;
0269         writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
0270         spin_lock_init(&espi->lock);
0271     }
0272 
0273     return 0;
0274 }
0275 
0276 void t1_espi_destroy(struct peespi *espi)
0277 {
0278     kfree(espi);
0279 }
0280 
0281 struct peespi *t1_espi_create(adapter_t *adapter)
0282 {
0283     struct peespi *espi = kzalloc(sizeof(*espi), GFP_KERNEL);
0284 
0285     if (espi)
0286         espi->adapter = adapter;
0287     return espi;
0288 }
0289 
0290 #if 0
0291 void t1_espi_set_misc_ctrl(adapter_t *adapter, u32 val)
0292 {
0293     struct peespi *espi = adapter->espi;
0294 
0295     if (!is_T2(adapter))
0296         return;
0297     spin_lock(&espi->lock);
0298     espi->misc_ctrl = (val & ~MON_MASK) |
0299               (espi->misc_ctrl & MON_MASK);
0300     writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
0301     spin_unlock(&espi->lock);
0302 }
0303 #endif  /*  0  */
0304 
0305 u32 t1_espi_get_mon(adapter_t *adapter, u32 addr, u8 wait)
0306 {
0307     struct peespi *espi = adapter->espi;
0308     u32 sel;
0309 
0310     if (!is_T2(adapter))
0311         return 0;
0312 
0313     sel = V_MONITORED_PORT_NUM((addr & 0x3c) >> 2);
0314     if (!wait) {
0315         if (!spin_trylock(&espi->lock))
0316             return 0;
0317     } else
0318         spin_lock(&espi->lock);
0319 
0320     if ((sel != (espi->misc_ctrl & MON_MASK))) {
0321         writel(((espi->misc_ctrl & ~MON_MASK) | sel),
0322                adapter->regs + A_ESPI_MISC_CONTROL);
0323         sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
0324         writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
0325     } else
0326         sel = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
0327     spin_unlock(&espi->lock);
0328     return sel;
0329 }
0330 
0331 /*
0332  * This function is for T204 only.
0333  * compare with t1_espi_get_mon(), it reads espiInTxSop[0 ~ 3] in
0334  * one shot, since there is no per port counter on the out side.
0335  */
0336 int t1_espi_get_mon_t204(adapter_t *adapter, u32 *valp, u8 wait)
0337 {
0338     struct peespi *espi = adapter->espi;
0339     u8 i, nport = (u8)adapter->params.nports;
0340 
0341     if (!wait) {
0342         if (!spin_trylock(&espi->lock))
0343             return -1;
0344     } else
0345         spin_lock(&espi->lock);
0346 
0347     if ((espi->misc_ctrl & MON_MASK) != F_MONITORED_DIRECTION) {
0348         espi->misc_ctrl = (espi->misc_ctrl & ~MON_MASK) |
0349                     F_MONITORED_DIRECTION;
0350         writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
0351     }
0352     for (i = 0 ; i < nport; i++, valp++) {
0353         if (i) {
0354             writel(espi->misc_ctrl | V_MONITORED_PORT_NUM(i),
0355                    adapter->regs + A_ESPI_MISC_CONTROL);
0356         }
0357         *valp = readl(adapter->regs + A_ESPI_SCH_TOKEN3);
0358     }
0359 
0360     writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
0361     spin_unlock(&espi->lock);
0362     return 0;
0363 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!