chelsio/cxgb/cpl5_cmd.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*****************************************************************************
0003  *                                                                           *
0004  * File: cpl5_cmd.h                                                          *
0005  * $Revision: 1.6 $                                                          *
0006  * $Date: 2005/06/21 18:29:47 $                                              *
0007  * Description:                                                              *
0008  *  part of the Chelsio 10Gb Ethernet Driver.                                *
0009  *                                                                           *
0010  *                                                                           *
0011  * http://www.chelsio.com                                                    *
0012  *                                                                           *
0013  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
0014  * All rights reserved.                                                      *
0015  *                                                                           *
0016  * Maintainers: maintainers@chelsio.com                                      *
0017  *                                                                           *
0018  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
0019  *          Tina Yang               <tainay@chelsio.com>                     *
0020  *          Felix Marti             <felix@chelsio.com>                      *
0021  *          Scott Bardone           <sbardone@chelsio.com>                   *
0022  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
0023  *          Frank DiMambro          <frank@chelsio.com>                      *
0024  *                                                                           *
0025  * History:                                                                  *
0026  *                                                                           *
0027  ****************************************************************************/
0028
0029 #ifndef _CXGB_CPL5_CMD_H_
0030 #define _CXGB_CPL5_CMD_H_
0031
0032 #include <asm/byteorder.h>
0033
0034 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
0035 #error "Adjust your <asm/byteorder.h> defines"
0036 #endif
0037
0038 enum CPL_opcode {
0039     CPL_PASS_OPEN_REQ     = 0x1,
0040     CPL_PASS_OPEN_RPL     = 0x2,
0041     CPL_PASS_ESTABLISH    = 0x3,
0042     CPL_PASS_ACCEPT_REQ   = 0xE,
0043     CPL_PASS_ACCEPT_RPL   = 0x4,
0044     CPL_ACT_OPEN_REQ      = 0x5,
0045     CPL_ACT_OPEN_RPL      = 0x6,
0046     CPL_CLOSE_CON_REQ     = 0x7,
0047     CPL_CLOSE_CON_RPL     = 0x8,
0048     CPL_CLOSE_LISTSRV_REQ = 0x9,
0049     CPL_CLOSE_LISTSRV_RPL = 0xA,
0050     CPL_ABORT_REQ         = 0xB,
0051     CPL_ABORT_RPL         = 0xC,
0052     CPL_PEER_CLOSE        = 0xD,
0053     CPL_ACT_ESTABLISH     = 0x17,
0054
0055     CPL_GET_TCB           = 0x24,
0056     CPL_GET_TCB_RPL       = 0x25,
0057     CPL_SET_TCB           = 0x26,
0058     CPL_SET_TCB_FIELD     = 0x27,
0059     CPL_SET_TCB_RPL       = 0x28,
0060     CPL_PCMD              = 0x29,
0061
0062     CPL_PCMD_READ         = 0x31,
0063     CPL_PCMD_READ_RPL     = 0x32,
0064
0065
0066     CPL_RX_DATA           = 0xA0,
0067     CPL_RX_DATA_DDP       = 0xA1,
0068     CPL_RX_DATA_ACK       = 0xA3,
0069     CPL_RX_PKT            = 0xAD,
0070     CPL_RX_ISCSI_HDR      = 0xAF,
0071     CPL_TX_DATA_ACK       = 0xB0,
0072     CPL_TX_DATA           = 0xB1,
0073     CPL_TX_PKT            = 0xB2,
0074     CPL_TX_PKT_LSO        = 0xB6,
0075
0076     CPL_RTE_DELETE_REQ    = 0xC0,
0077     CPL_RTE_DELETE_RPL    = 0xC1,
0078     CPL_RTE_WRITE_REQ     = 0xC2,
0079     CPL_RTE_WRITE_RPL     = 0xD3,
0080     CPL_RTE_READ_REQ      = 0xC3,
0081     CPL_RTE_READ_RPL      = 0xC4,
0082     CPL_L2T_WRITE_REQ     = 0xC5,
0083     CPL_L2T_WRITE_RPL     = 0xD4,
0084     CPL_L2T_READ_REQ      = 0xC6,
0085     CPL_L2T_READ_RPL      = 0xC7,
0086     CPL_SMT_WRITE_REQ     = 0xC8,
0087     CPL_SMT_WRITE_RPL     = 0xD5,
0088     CPL_SMT_READ_REQ      = 0xC9,
0089     CPL_SMT_READ_RPL      = 0xCA,
0090     CPL_ARP_MISS_REQ      = 0xCD,
0091     CPL_ARP_MISS_RPL      = 0xCE,
0092     CPL_MIGRATE_C2T_REQ   = 0xDC,
0093     CPL_MIGRATE_C2T_RPL   = 0xDD,
0094     CPL_ERROR             = 0xD7,
0095
0096     /* internal: driver -> TOM */
0097     CPL_MSS_CHANGE        = 0xE1
0098 };
0099
0100 #define NUM_CPL_CMDS 256
0101
0102 enum CPL_error {
0103     CPL_ERR_NONE               = 0,
0104     CPL_ERR_TCAM_PARITY        = 1,
0105     CPL_ERR_TCAM_FULL          = 3,
0106     CPL_ERR_CONN_RESET         = 20,
0107     CPL_ERR_CONN_EXIST         = 22,
0108     CPL_ERR_ARP_MISS           = 23,
0109     CPL_ERR_BAD_SYN            = 24,
0110     CPL_ERR_CONN_TIMEDOUT      = 30,
0111     CPL_ERR_XMIT_TIMEDOUT      = 31,
0112     CPL_ERR_PERSIST_TIMEDOUT   = 32,
0113     CPL_ERR_FINWAIT2_TIMEDOUT  = 33,
0114     CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
0115     CPL_ERR_ABORT_FAILED       = 42,
0116     CPL_ERR_GENERAL            = 99
0117 };
0118
0119 enum {
0120     CPL_CONN_POLICY_AUTO = 0,
0121     CPL_CONN_POLICY_ASK  = 1,
0122     CPL_CONN_POLICY_DENY = 3
0123 };
0124
0125 enum {
0126     ULP_MODE_NONE   = 0,
0127     ULP_MODE_TCPDDP = 1,
0128     ULP_MODE_ISCSI  = 2,
0129     ULP_MODE_IWARP  = 3,
0130     ULP_MODE_SSL    = 4
0131 };
0132
0133 enum {
0134     CPL_PASS_OPEN_ACCEPT,
0135     CPL_PASS_OPEN_REJECT
0136 };
0137
0138 enum {
0139     CPL_ABORT_SEND_RST = 0,
0140     CPL_ABORT_NO_RST,
0141     CPL_ABORT_POST_CLOSE_REQ = 2
0142 };
0143
0144 enum {                // TX_PKT_LSO ethernet types
0145     CPL_ETH_II,
0146     CPL_ETH_II_VLAN,
0147     CPL_ETH_802_3,
0148     CPL_ETH_802_3_VLAN
0149 };
0150
0151 union opcode_tid {
0152     u32 opcode_tid;
0153     u8 opcode;
0154 };
0155
0156 #define S_OPCODE 24
0157 #define V_OPCODE(x) ((x) << S_OPCODE)
0158 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
0159 #define G_TID(x)    ((x) & 0xFFFFFF)
0160
0161 /* tid is assumed to be 24-bits */
0162 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
0163
0164 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
0165
0166 /* extract the TID from a CPL command */
0167 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
0168
0169 struct tcp_options {
0170     u16 mss;
0171     u8 wsf;
0172 #if defined(__LITTLE_ENDIAN_BITFIELD)
0173     u8 rsvd:4;
0174     u8 ecn:1;
0175     u8 sack:1;
0176     u8 tstamp:1;
0177 #else
0178     u8 tstamp:1;
0179     u8 sack:1;
0180     u8 ecn:1;
0181     u8 rsvd:4;
0182 #endif
0183 };
0184
0185 struct cpl_pass_open_req {
0186     union opcode_tid ot;
0187     u16 local_port;
0188     u16 peer_port;
0189     u32 local_ip;
0190     u32 peer_ip;
0191     u32 opt0h;
0192     u32 opt0l;
0193     u32 peer_netmask;
0194     u32 opt1;
0195 };
0196
0197 struct cpl_pass_open_rpl {
0198     union opcode_tid ot;
0199     u16 local_port;
0200     u16 peer_port;
0201     u32 local_ip;
0202     u32 peer_ip;
0203     u8 resvd[7];
0204     u8 status;
0205 };
0206
0207 struct cpl_pass_establish {
0208     union opcode_tid ot;
0209     u16 local_port;
0210     u16 peer_port;
0211     u32 local_ip;
0212     u32 peer_ip;
0213     u32 tos_tid;
0214     u8  l2t_idx;
0215     u8  rsvd[3];
0216     u32 snd_isn;
0217     u32 rcv_isn;
0218 };
0219
0220 struct cpl_pass_accept_req {
0221     union opcode_tid ot;
0222     u16 local_port;
0223     u16 peer_port;
0224     u32 local_ip;
0225     u32 peer_ip;
0226     u32 tos_tid;
0227     struct tcp_options tcp_options;
0228     u8  dst_mac[6];
0229     u16 vlan_tag;
0230     u8  src_mac[6];
0231     u8  rsvd[2];
0232     u32 rcv_isn;
0233     u32 unknown_tcp_options;
0234 };
0235
0236 struct cpl_pass_accept_rpl {
0237     union opcode_tid ot;
0238     u32 rsvd0;
0239     u32 rsvd1;
0240     u32 peer_ip;
0241     u32 opt0h;
0242     union {
0243         u32 opt0l;
0244         struct {
0245             u8 rsvd[3];
0246             u8 status;
0247         };
0248     };
0249 };
0250
0251 struct cpl_act_open_req {
0252     union opcode_tid ot;
0253     u16 local_port;
0254     u16 peer_port;
0255     u32 local_ip;
0256     u32 peer_ip;
0257     u32 opt0h;
0258     u32 opt0l;
0259     u32 iff_vlantag;
0260     u32 rsvd;
0261 };
0262
0263 struct cpl_act_open_rpl {
0264     union opcode_tid ot;
0265     u16 local_port;
0266     u16 peer_port;
0267     u32 local_ip;
0268     u32 peer_ip;
0269     u32 new_tid;
0270     u8  rsvd[3];
0271     u8  status;
0272 };
0273
0274 struct cpl_act_establish {
0275     union opcode_tid ot;
0276     u16 local_port;
0277     u16 peer_port;
0278     u32 local_ip;
0279     u32 peer_ip;
0280     u32 tos_tid;
0281     u32 rsvd;
0282     u32 snd_isn;
0283     u32 rcv_isn;
0284 };
0285
0286 struct cpl_get_tcb {
0287     union opcode_tid ot;
0288     u32 rsvd;
0289 };
0290
0291 struct cpl_get_tcb_rpl {
0292     union opcode_tid ot;
0293     u16 len;
0294     u8 rsvd;
0295     u8 status;
0296 };
0297
0298 struct cpl_set_tcb {
0299     union opcode_tid ot;
0300     u16 len;
0301     u16 rsvd;
0302 };
0303
0304 struct cpl_set_tcb_field {
0305     union opcode_tid ot;
0306     u8 rsvd[3];
0307     u8 offset;
0308     u32 mask;
0309     u32 val;
0310 };
0311
0312 struct cpl_set_tcb_rpl {
0313     union opcode_tid ot;
0314     u8 rsvd[3];
0315     u8 status;
0316 };
0317
0318 struct cpl_pcmd {
0319     union opcode_tid ot;
0320     u16 dlen_in;
0321     u16 dlen_out;
0322     u32 pcmd_parm[2];
0323 };
0324
0325 struct cpl_pcmd_read {
0326     union opcode_tid ot;
0327     u32 rsvd1;
0328     u16 rsvd2;
0329     u32 addr;
0330     u16 len;
0331 };
0332
0333 struct cpl_pcmd_read_rpl {
0334     union opcode_tid ot;
0335     u16 len;
0336 };
0337
0338 struct cpl_close_con_req {
0339     union opcode_tid ot;
0340     u32 rsvd;
0341 };
0342
0343 struct cpl_close_con_rpl {
0344     union opcode_tid ot;
0345     u8 rsvd[3];
0346     u8 status;
0347     u32 snd_nxt;
0348     u32 rcv_nxt;
0349 };
0350
0351 struct cpl_close_listserv_req {
0352     union opcode_tid ot;
0353     u32 rsvd;
0354 };
0355
0356 struct cpl_close_listserv_rpl {
0357     union opcode_tid ot;
0358     u8 rsvd[3];
0359     u8 status;
0360 };
0361
0362 struct cpl_abort_req {
0363     union opcode_tid ot;
0364     u32 rsvd0;
0365     u8  rsvd1;
0366     u8  cmd;
0367     u8  rsvd2[6];
0368 };
0369
0370 struct cpl_abort_rpl {
0371     union opcode_tid ot;
0372     u32 rsvd0;
0373     u8  rsvd1;
0374     u8  status;
0375     u8  rsvd2[6];
0376 };
0377
0378 struct cpl_peer_close {
0379     union opcode_tid ot;
0380     u32 rsvd;
0381 };
0382
0383 struct cpl_tx_data {
0384     union opcode_tid ot;
0385     u32 len;
0386     u32 rsvd0;
0387     u16 urg;
0388     u16 flags;
0389 };
0390
0391 struct cpl_tx_data_ack {
0392     union opcode_tid ot;
0393     u32 ack_seq;
0394 };
0395
0396 struct cpl_rx_data {
0397     union opcode_tid ot;
0398     u32 len;
0399     u32 seq;
0400     u16 urg;
0401     u8  rsvd;
0402     u8  status;
0403 };
0404
0405 struct cpl_rx_data_ack {
0406     union opcode_tid ot;
0407     u32 credit;
0408 };
0409
0410 struct cpl_rx_data_ddp {
0411     union opcode_tid ot;
0412     u32 len;
0413     u32 seq;
0414     u32 nxt_seq;
0415     u32 ulp_crc;
0416     u16 ddp_status;
0417     u8  rsvd;
0418     u8  status;
0419 };
0420
0421 /*
0422  * We want this header's alignment to be no more stringent than 2-byte aligned.
0423  * All fields are u8 or u16 except for the length.  However that field is not
0424  * used so we break it into 2 16-bit parts to easily meet our alignment needs.
0425  */
0426 struct cpl_tx_pkt {
0427     u8 opcode;
0428 #if defined(__LITTLE_ENDIAN_BITFIELD)
0429     u8 iff:4;
0430     u8 ip_csum_dis:1;
0431     u8 l4_csum_dis:1;
0432     u8 vlan_valid:1;
0433     u8 rsvd:1;
0434 #else
0435     u8 rsvd:1;
0436     u8 vlan_valid:1;
0437     u8 l4_csum_dis:1;
0438     u8 ip_csum_dis:1;
0439     u8 iff:4;
0440 #endif
0441     u16 vlan;
0442     u16 len_hi;
0443     u16 len_lo;
0444 };
0445
0446 struct cpl_tx_pkt_lso {
0447     u8 opcode;
0448 #if defined(__LITTLE_ENDIAN_BITFIELD)
0449     u8 iff:4;
0450     u8 ip_csum_dis:1;
0451     u8 l4_csum_dis:1;
0452     u8 vlan_valid:1;
0453     u8 :1;
0454 #else
0455     u8 :1;
0456     u8 vlan_valid:1;
0457     u8 l4_csum_dis:1;
0458     u8 ip_csum_dis:1;
0459     u8 iff:4;
0460 #endif
0461     u16 vlan;
0462     __be32 len;
0463
0464     u8 rsvd[5];
0465 #if defined(__LITTLE_ENDIAN_BITFIELD)
0466     u8 tcp_hdr_words:4;
0467     u8 ip_hdr_words:4;
0468 #else
0469     u8 ip_hdr_words:4;
0470     u8 tcp_hdr_words:4;
0471 #endif
0472     __be16 eth_type_mss;
0473 };
0474
0475 struct cpl_rx_pkt {
0476     u8 opcode;
0477 #if defined(__LITTLE_ENDIAN_BITFIELD)
0478     u8 iff:4;
0479     u8 csum_valid:1;
0480     u8 bad_pkt:1;
0481     u8 vlan_valid:1;
0482     u8 rsvd:1;
0483 #else
0484     u8 rsvd:1;
0485     u8 vlan_valid:1;
0486     u8 bad_pkt:1;
0487     u8 csum_valid:1;
0488     u8 iff:4;
0489 #endif
0490     u16 csum;
0491     u16 vlan;
0492     u16 len;
0493 };
0494
0495 struct cpl_l2t_write_req {
0496     union opcode_tid ot;
0497     u32 params;
0498     u8 rsvd1[2];
0499     u8 dst_mac[6];
0500 };
0501
0502 struct cpl_l2t_write_rpl {
0503     union opcode_tid ot;
0504     u8 status;
0505     u8 rsvd[3];
0506 };
0507
0508 struct cpl_l2t_read_req {
0509     union opcode_tid ot;
0510     u8 rsvd[3];
0511     u8 l2t_idx;
0512 };
0513
0514 struct cpl_l2t_read_rpl {
0515     union opcode_tid ot;
0516     u32 params;
0517     u8 rsvd1[2];
0518     u8 dst_mac[6];
0519 };
0520
0521 struct cpl_smt_write_req {
0522     union opcode_tid ot;
0523     u8 rsvd0;
0524 #if defined(__LITTLE_ENDIAN_BITFIELD)
0525     u8 rsvd1:1;
0526     u8 mtu_idx:3;
0527     u8 iff:4;
0528 #else
0529     u8 iff:4;
0530     u8 mtu_idx:3;
0531     u8 rsvd1:1;
0532 #endif
0533     u16 rsvd2;
0534     u16 rsvd3;
0535     u8  src_mac1[6];
0536     u16 rsvd4;
0537     u8  src_mac0[6];
0538 };
0539
0540 struct cpl_smt_write_rpl {
0541     union opcode_tid ot;
0542     u8 status;
0543     u8 rsvd[3];
0544 };
0545
0546 struct cpl_smt_read_req {
0547     union opcode_tid ot;
0548     u8 rsvd0;
0549 #if defined(__LITTLE_ENDIAN_BITFIELD)
0550     u8 rsvd1:4;
0551     u8 iff:4;
0552 #else
0553     u8 iff:4;
0554     u8 rsvd1:4;
0555 #endif
0556     u16 rsvd2;
0557 };
0558
0559 struct cpl_smt_read_rpl {
0560     union opcode_tid ot;
0561     u8 status;
0562 #if defined(__LITTLE_ENDIAN_BITFIELD)
0563     u8 rsvd1:1;
0564     u8 mtu_idx:3;
0565     u8 rsvd0:4;
0566 #else
0567     u8 rsvd0:4;
0568     u8 mtu_idx:3;
0569     u8 rsvd1:1;
0570 #endif
0571     u16 rsvd2;
0572     u16 rsvd3;
0573     u8  src_mac1[6];
0574     u16 rsvd4;
0575     u8  src_mac0[6];
0576 };
0577
0578 struct cpl_rte_delete_req {
0579     union opcode_tid ot;
0580     u32 params;
0581 };
0582
0583 struct cpl_rte_delete_rpl {
0584     union opcode_tid ot;
0585     u8 status;
0586     u8 rsvd[3];
0587 };
0588
0589 struct cpl_rte_write_req {
0590     union opcode_tid ot;
0591     u32 params;
0592     u32 netmask;
0593     u32 faddr;
0594 };
0595
0596 struct cpl_rte_write_rpl {
0597     union opcode_tid ot;
0598     u8 status;
0599     u8 rsvd[3];
0600 };
0601
0602 struct cpl_rte_read_req {
0603     union opcode_tid ot;
0604     u32 params;
0605 };
0606
0607 struct cpl_rte_read_rpl {
0608     union opcode_tid ot;
0609     u8 status;
0610     u8 rsvd0[2];
0611     u8 l2t_idx;
0612 #if defined(__LITTLE_ENDIAN_BITFIELD)
0613     u8 rsvd1:7;
0614     u8 select:1;
0615 #else
0616     u8 select:1;
0617     u8 rsvd1:7;
0618 #endif
0619     u8 rsvd2[3];
0620     u32 addr;
0621 };
0622
0623 struct cpl_mss_change {
0624     union opcode_tid ot;
0625     u32 mss;
0626 };
0627
0628 #endif /* _CXGB_CPL5_CMD_H_ */