chelsio/cxgb/common.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*****************************************************************************
0003  *                                                                           *
0004  * File: common.h                                                            *
0005  * $Revision: 1.21 $                                                         *
0006  * $Date: 2005/06/22 00:43:25 $                                              *
0007  * Description:                                                              *
0008  *  part of the Chelsio 10Gb Ethernet Driver.                                *
0009  *                                                                           *
0010  *                                                                           *
0011  * http://www.chelsio.com                                                    *
0012  *                                                                           *
0013  * Copyright (c) 2003 - 2005 Chelsio Communications, Inc.                    *
0014  * All rights reserved.                                                      *
0015  *                                                                           *
0016  * Maintainers: maintainers@chelsio.com                                      *
0017  *                                                                           *
0018  * Authors: Dimitrios Michailidis   <dm@chelsio.com>                         *
0019  *          Tina Yang               <tainay@chelsio.com>                     *
0020  *          Felix Marti             <felix@chelsio.com>                      *
0021  *          Scott Bardone           <sbardone@chelsio.com>                   *
0022  *          Kurt Ottaway            <kottaway@chelsio.com>                   *
0023  *          Frank DiMambro          <frank@chelsio.com>                      *
0024  *                                                                           *
0025  * History:                                                                  *
0026  *                                                                           *
0027  ****************************************************************************/
0028
0029 #define pr_fmt(fmt) "cxgb: " fmt
0030
0031 #ifndef _CXGB_COMMON_H_
0032 #define _CXGB_COMMON_H_
0033
0034 #include <linux/module.h>
0035 #include <linux/netdevice.h>
0036 #include <linux/types.h>
0037 #include <linux/delay.h>
0038 #include <linux/pci.h>
0039 #include <linux/ethtool.h>
0040 #include <linux/if_vlan.h>
0041 #include <linux/mdio.h>
0042 #include <linux/crc32.h>
0043 #include <linux/slab.h>
0044 #include <asm/io.h>
0045 #include <linux/pci_ids.h>
0046
0047 #define DRV_DESCRIPTION "Chelsio 10Gb Ethernet Driver"
0048 #define DRV_NAME "cxgb"
0049
0050 #define CH_DEVICE(devid, ssid, idx) \
0051     { PCI_VENDOR_ID_CHELSIO, devid, PCI_ANY_ID, ssid, 0, 0, idx }
0052
0053 #define SUPPORTED_PAUSE       (1 << 13)
0054 #define SUPPORTED_LOOPBACK    (1 << 15)
0055
0056 #define ADVERTISED_PAUSE      (1 << 13)
0057 #define ADVERTISED_ASYM_PAUSE (1 << 14)
0058
0059 typedef struct adapter adapter_t;
0060
0061 struct t1_rx_mode {
0062        struct net_device *dev;
0063 };
0064
0065 #define t1_rx_mode_promisc(rm)  (rm->dev->flags & IFF_PROMISC)
0066 #define t1_rx_mode_allmulti(rm) (rm->dev->flags & IFF_ALLMULTI)
0067 #define t1_rx_mode_mc_cnt(rm)   (netdev_mc_count(rm->dev))
0068 #define t1_get_netdev(rm)   (rm->dev)
0069
0070 #define MAX_NPORTS 4
0071 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
0072 #define NMTUS      8
0073 #define TCB_SIZE   128
0074
0075 #define SPEED_INVALID 0xffff
0076 #define DUPLEX_INVALID 0xff
0077
0078 /* Max frame size PM3393 can handle. Includes Ethernet header and CRC. */
0079 #define PM3393_MAX_FRAME_SIZE 9600
0080
0081 #define VSC7326_MAX_MTU 9600
0082
0083 enum {
0084     CHBT_BOARD_N110,
0085     CHBT_BOARD_N210,
0086     CHBT_BOARD_7500,
0087     CHBT_BOARD_8000,
0088     CHBT_BOARD_CHT101,
0089     CHBT_BOARD_CHT110,
0090     CHBT_BOARD_CHT210,
0091     CHBT_BOARD_CHT204,
0092     CHBT_BOARD_CHT204V,
0093     CHBT_BOARD_CHT204E,
0094     CHBT_BOARD_CHN204,
0095     CHBT_BOARD_COUGAR,
0096     CHBT_BOARD_6800,
0097     CHBT_BOARD_SIMUL,
0098 };
0099
0100 enum {
0101     CHBT_TERM_FPGA,
0102     CHBT_TERM_T1,
0103     CHBT_TERM_T2,
0104     CHBT_TERM_T3
0105 };
0106
0107 enum {
0108     CHBT_MAC_CHELSIO_A,
0109     CHBT_MAC_IXF1010,
0110     CHBT_MAC_PM3393,
0111     CHBT_MAC_VSC7321,
0112     CHBT_MAC_DUMMY
0113 };
0114
0115 enum {
0116     CHBT_PHY_88E1041,
0117     CHBT_PHY_88E1111,
0118     CHBT_PHY_88X2010,
0119     CHBT_PHY_XPAK,
0120     CHBT_PHY_MY3126,
0121     CHBT_PHY_8244,
0122     CHBT_PHY_DUMMY
0123 };
0124
0125 enum {
0126     PAUSE_RX      = 1 << 0,
0127     PAUSE_TX      = 1 << 1,
0128     PAUSE_AUTONEG = 1 << 2
0129 };
0130
0131 /* Revisions of T1 chip */
0132 enum {
0133     TERM_T1A   = 0,
0134     TERM_T1B   = 1,
0135     TERM_T2    = 3
0136 };
0137
0138 struct sge_params {
0139     unsigned int cmdQ_size[2];
0140     unsigned int freelQ_size[2];
0141     unsigned int large_buf_capacity;
0142     unsigned int rx_coalesce_usecs;
0143     unsigned int last_rx_coalesce_raw;
0144     unsigned int default_rx_coalesce_usecs;
0145     unsigned int sample_interval_usecs;
0146     unsigned int coalesce_enable;
0147     unsigned int polling;
0148 };
0149
0150 struct chelsio_pci_params {
0151     unsigned short speed;
0152     unsigned char  width;
0153     unsigned char  is_pcix;
0154 };
0155
0156 struct tp_params {
0157     unsigned int pm_size;
0158     unsigned int cm_size;
0159     unsigned int pm_rx_base;
0160     unsigned int pm_tx_base;
0161     unsigned int pm_rx_pg_size;
0162     unsigned int pm_tx_pg_size;
0163     unsigned int pm_rx_num_pgs;
0164     unsigned int pm_tx_num_pgs;
0165     unsigned int rx_coalescing_size;
0166     unsigned int use_5tuple_mode;
0167 };
0168
0169 struct mc5_params {
0170     unsigned int mode;       /* selects MC5 width */
0171     unsigned int nservers;   /* size of server region */
0172     unsigned int nroutes;    /* size of routing region */
0173 };
0174
0175 /* Default MC5 region sizes */
0176 #define DEFAULT_SERVER_REGION_LEN 256
0177 #define DEFAULT_RT_REGION_LEN 1024
0178
0179 struct adapter_params {
0180     struct sge_params sge;
0181     struct mc5_params mc5;
0182     struct tp_params  tp;
0183     struct chelsio_pci_params pci;
0184
0185     const struct board_info *brd_info;
0186
0187     unsigned short mtus[NMTUS];
0188     unsigned int   nports;          /* # of ethernet ports */
0189     unsigned int   stats_update_period;
0190     unsigned short chip_revision;
0191     unsigned char  chip_version;
0192     unsigned char  is_asic;
0193     unsigned char  has_msi;
0194 };
0195
0196 struct link_config {
0197     unsigned int   supported;        /* link capabilities */
0198     unsigned int   advertising;      /* advertised capabilities */
0199     unsigned short requested_speed;  /* speed user has requested */
0200     unsigned short speed;            /* actual link speed */
0201     unsigned char  requested_duplex; /* duplex user has requested */
0202     unsigned char  duplex;           /* actual link duplex */
0203     unsigned char  requested_fc;     /* flow control user has requested */
0204     unsigned char  fc;               /* actual link flow control */
0205     unsigned char  autoneg;          /* autonegotiating? */
0206 };
0207
0208 struct cmac;
0209 struct cphy;
0210
0211 struct port_info {
0212     struct net_device *dev;
0213     struct cmac *mac;
0214     struct cphy *phy;
0215     struct link_config link_config;
0216 };
0217
0218 struct sge;
0219 struct peespi;
0220
0221 struct adapter {
0222     u8 __iomem *regs;
0223     struct pci_dev *pdev;
0224     unsigned long registered_device_map;
0225     unsigned long open_device_map;
0226     unsigned long flags;
0227
0228     const char *name;
0229     int msg_enable;
0230     u32 mmio_len;
0231
0232     struct adapter_params params;
0233
0234     /* Terminator modules. */
0235     struct sge    *sge;
0236     struct peespi *espi;
0237     struct petp   *tp;
0238
0239     struct napi_struct napi;
0240     struct port_info port[MAX_NPORTS];
0241     struct delayed_work stats_update_task;
0242     struct timer_list stats_update_timer;
0243
0244     spinlock_t tpi_lock;
0245     spinlock_t work_lock;
0246     spinlock_t mac_lock;
0247
0248     /* guards async operations */
0249     spinlock_t async_lock ____cacheline_aligned;
0250     u32 pending_thread_intr;
0251     u32 slow_intr_mask;
0252     int t1powersave;
0253 };
0254
0255 enum {                                           /* adapter flags */
0256     FULL_INIT_DONE        = 1 << 0,
0257 };
0258
0259 struct mdio_ops;
0260 struct gmac;
0261 struct gphy;
0262
0263 struct board_info {
0264     unsigned char           board;
0265     unsigned char           port_number;
0266     unsigned long           caps;
0267     unsigned char           chip_term;
0268     unsigned char           chip_mac;
0269     unsigned char           chip_phy;
0270     unsigned int            clock_core;
0271     unsigned int            clock_mc3;
0272     unsigned int            clock_mc4;
0273     unsigned int            espi_nports;
0274     unsigned int            clock_elmer0;
0275     unsigned char           mdio_mdien;
0276     unsigned char           mdio_mdiinv;
0277     unsigned char           mdio_mdc;
0278     unsigned char           mdio_phybaseaddr;
0279     const struct gmac      *gmac;
0280     const struct gphy      *gphy;
0281     const struct mdio_ops  *mdio_ops;
0282     const char             *desc;
0283 };
0284
0285 static inline int t1_is_asic(const adapter_t *adapter)
0286 {
0287     return adapter->params.is_asic;
0288 }
0289
0290 extern const struct pci_device_id t1_pci_tbl[];
0291
0292 static inline int adapter_matches_type(const adapter_t *adapter,
0293                        int version, int revision)
0294 {
0295     return adapter->params.chip_version == version &&
0296            adapter->params.chip_revision == revision;
0297 }
0298
0299 #define t1_is_T1B(adap) adapter_matches_type(adap, CHBT_TERM_T1, TERM_T1B)
0300 #define is_T2(adap)     adapter_matches_type(adap, CHBT_TERM_T2, TERM_T2)
0301
0302 /* Returns true if an adapter supports VLAN acceleration and TSO */
0303 static inline int vlan_tso_capable(const adapter_t *adapter)
0304 {
0305     return !t1_is_T1B(adapter);
0306 }
0307
0308 #define for_each_port(adapter, iter) \
0309     for (iter = 0; iter < (adapter)->params.nports; ++iter)
0310
0311 #define board_info(adapter) ((adapter)->params.brd_info)
0312 #define is_10G(adapter) (board_info(adapter)->caps & SUPPORTED_10000baseT_Full)
0313
0314 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
0315 {
0316     return board_info(adap)->clock_core / 1000000;
0317 }
0318
0319 int __t1_tpi_read(adapter_t *adapter, u32 addr, u32 *valp);
0320 int __t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
0321 int t1_tpi_write(adapter_t *adapter, u32 addr, u32 value);
0322 int t1_tpi_read(adapter_t *adapter, u32 addr, u32 *value);
0323
0324 void t1_interrupts_enable(adapter_t *adapter);
0325 void t1_interrupts_disable(adapter_t *adapter);
0326 void t1_interrupts_clear(adapter_t *adapter);
0327 int t1_elmer0_ext_intr_handler(adapter_t *adapter);
0328 irqreturn_t t1_slow_intr_handler(adapter_t *adapter);
0329
0330 int t1_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
0331 const struct board_info *t1_get_board_info(unsigned int board_id);
0332 const struct board_info *t1_get_board_info_from_ids(unsigned int devid,
0333                             unsigned short ssid);
0334 int t1_seeprom_read(adapter_t *adapter, u32 addr, __le32 *data);
0335 int t1_get_board_rev(adapter_t *adapter, const struct board_info *bi,
0336              struct adapter_params *p);
0337 int t1_init_hw_modules(adapter_t *adapter);
0338 int t1_init_sw_modules(adapter_t *adapter, const struct board_info *bi);
0339 void t1_free_sw_modules(adapter_t *adapter);
0340 void t1_link_changed(adapter_t *adapter, int port_id);
0341 void t1_link_negotiated(adapter_t *adapter, int port_id, int link_stat,
0342                 int speed, int duplex, int pause);
0343 #endif /* _CXGB_COMMON_H_ */