cavium/thunder/thunder_xcv.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2016 Cavium, Inc.
0004  */
0005
0006 #include <linux/acpi.h>
0007 #include <linux/module.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/pci.h>
0010 #include <linux/netdevice.h>
0011 #include <linux/etherdevice.h>
0012 #include <linux/phy.h>
0013 #include <linux/of.h>
0014 #include <linux/of_mdio.h>
0015 #include <linux/of_net.h>
0016
0017 #include "nic.h"
0018 #include "thunder_bgx.h"
0019
0020 #define DRV_NAME    "thunder_xcv"
0021 #define DRV_VERSION "1.0"
0022
0023 /* Register offsets */
0024 #define XCV_RESET       0x00
0025 #define   PORT_EN       BIT_ULL(63)
0026 #define   CLK_RESET     BIT_ULL(15)
0027 #define   DLL_RESET     BIT_ULL(11)
0028 #define   COMP_EN       BIT_ULL(7)
0029 #define   TX_PKT_RESET      BIT_ULL(3)
0030 #define   TX_DATA_RESET     BIT_ULL(2)
0031 #define   RX_PKT_RESET      BIT_ULL(1)
0032 #define   RX_DATA_RESET     BIT_ULL(0)
0033 #define XCV_DLL_CTL     0x10
0034 #define   CLKRX_BYP     BIT_ULL(23)
0035 #define   CLKTX_BYP     BIT_ULL(15)
0036 #define XCV_COMP_CTL        0x20
0037 #define   DRV_BYP       BIT_ULL(63)
0038 #define XCV_CTL         0x30
0039 #define XCV_INT         0x40
0040 #define XCV_INT_W1S     0x48
0041 #define XCV_INT_ENA_W1C     0x50
0042 #define XCV_INT_ENA_W1S     0x58
0043 #define XCV_INBND_STATUS    0x80
0044 #define XCV_BATCH_CRD_RET   0x100
0045
0046 struct xcv {
0047     void __iomem        *reg_base;
0048     struct pci_dev      *pdev;
0049 };
0050
0051 static struct xcv *xcv;
0052
0053 /* Supported devices */
0054 static const struct pci_device_id xcv_id_table[] = {
0055     { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, 0xA056) },
0056     { 0, }  /* end of table */
0057 };
0058
0059 MODULE_AUTHOR("Cavium Inc");
0060 MODULE_DESCRIPTION("Cavium Thunder RGX/XCV Driver");
0061 MODULE_LICENSE("GPL v2");
0062 MODULE_VERSION(DRV_VERSION);
0063 MODULE_DEVICE_TABLE(pci, xcv_id_table);
0064
0065 void xcv_init_hw(void)
0066 {
0067     u64  cfg;
0068
0069     /* Take DLL out of reset */
0070     cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
0071     cfg &= ~DLL_RESET;
0072     writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
0073
0074     /* Take clock tree out of reset */
0075     cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
0076     cfg &= ~CLK_RESET;
0077     writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
0078     /* Wait for DLL to lock */
0079     msleep(1);
0080
0081     /* Configure DLL - enable or bypass
0082      * TX no bypass, RX bypass
0083      */
0084     cfg = readq_relaxed(xcv->reg_base + XCV_DLL_CTL);
0085     cfg &= ~0xFF03;
0086     cfg |= CLKRX_BYP;
0087     writeq_relaxed(cfg, xcv->reg_base + XCV_DLL_CTL);
0088
0089     /* Enable compensation controller and force the
0090      * write to be visible to HW by readig back.
0091      */
0092     cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
0093     cfg |= COMP_EN;
0094     writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
0095     readq_relaxed(xcv->reg_base + XCV_RESET);
0096     /* Wait for compensation state machine to lock */
0097     msleep(10);
0098
0099     /* enable the XCV block */
0100     cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
0101     cfg |= PORT_EN;
0102     writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
0103
0104     cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
0105     cfg |= CLK_RESET;
0106     writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
0107 }
0108 EXPORT_SYMBOL(xcv_init_hw);
0109
0110 void xcv_setup_link(bool link_up, int link_speed)
0111 {
0112     u64  cfg;
0113     int speed = 2;
0114
0115     if (!xcv) {
0116         pr_err("XCV init not done, probe may have failed\n");
0117         return;
0118     }
0119
0120     if (link_speed == 100)
0121         speed = 1;
0122     else if (link_speed == 10)
0123         speed = 0;
0124
0125     if (link_up) {
0126         /* set operating speed */
0127         cfg = readq_relaxed(xcv->reg_base + XCV_CTL);
0128         cfg &= ~0x03;
0129         cfg |= speed;
0130         writeq_relaxed(cfg, xcv->reg_base + XCV_CTL);
0131
0132         /* Reset datapaths */
0133         cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
0134         cfg |= TX_DATA_RESET | RX_DATA_RESET;
0135         writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
0136
0137         /* Enable the packet flow */
0138         cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
0139         cfg |= TX_PKT_RESET | RX_PKT_RESET;
0140         writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
0141
0142         /* Return credits to RGX */
0143         writeq_relaxed(0x01, xcv->reg_base + XCV_BATCH_CRD_RET);
0144     } else {
0145         /* Disable packet flow */
0146         cfg = readq_relaxed(xcv->reg_base + XCV_RESET);
0147         cfg &= ~(TX_PKT_RESET | RX_PKT_RESET);
0148         writeq_relaxed(cfg, xcv->reg_base + XCV_RESET);
0149         readq_relaxed(xcv->reg_base + XCV_RESET);
0150     }
0151 }
0152 EXPORT_SYMBOL(xcv_setup_link);
0153
0154 static int xcv_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
0155 {
0156     int err;
0157     struct device *dev = &pdev->dev;
0158
0159     xcv = devm_kzalloc(dev, sizeof(struct xcv), GFP_KERNEL);
0160     if (!xcv)
0161         return -ENOMEM;
0162     xcv->pdev = pdev;
0163
0164     pci_set_drvdata(pdev, xcv);
0165
0166     err = pci_enable_device(pdev);
0167     if (err) {
0168         dev_err(dev, "Failed to enable PCI device\n");
0169         goto err_kfree;
0170     }
0171
0172     err = pci_request_regions(pdev, DRV_NAME);
0173     if (err) {
0174         dev_err(dev, "PCI request regions failed 0x%x\n", err);
0175         goto err_disable_device;
0176     }
0177
0178     /* MAP configuration registers */
0179     xcv->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
0180     if (!xcv->reg_base) {
0181         dev_err(dev, "XCV: Cannot map CSR memory space, aborting\n");
0182         err = -ENOMEM;
0183         goto err_release_regions;
0184     }
0185
0186     return 0;
0187
0188 err_release_regions:
0189     pci_release_regions(pdev);
0190 err_disable_device:
0191     pci_disable_device(pdev);
0192 err_kfree:
0193     devm_kfree(dev, xcv);
0194     xcv = NULL;
0195     return err;
0196 }
0197
0198 static void xcv_remove(struct pci_dev *pdev)
0199 {
0200     struct device *dev = &pdev->dev;
0201
0202     if (xcv) {
0203         devm_kfree(dev, xcv);
0204         xcv = NULL;
0205     }
0206
0207     pci_release_regions(pdev);
0208     pci_disable_device(pdev);
0209 }
0210
0211 static struct pci_driver xcv_driver = {
0212     .name = DRV_NAME,
0213     .id_table = xcv_id_table,
0214     .probe = xcv_probe,
0215     .remove = xcv_remove,
0216 };
0217
0218 static int __init xcv_init_module(void)
0219 {
0220     pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
0221
0222     return pci_register_driver(&xcv_driver);
0223 }
0224
0225 static void __exit xcv_cleanup_module(void)
0226 {
0227     pci_unregister_driver(&xcv_driver);
0228 }
0229
0230 module_init(xcv_init_module);
0231 module_exit(xcv_cleanup_module);