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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2015 Cavium, Inc.
0004  */
0005 
0006 #ifndef NIC_REG_H
0007 #define NIC_REG_H
0008 
0009 #define   NIC_PF_REG_COUNT          29573
0010 #define   NIC_VF_REG_COUNT          249
0011 
0012 /* Physical function register offsets */
0013 #define   NIC_PF_CFG                (0x0000)
0014 #define   NIC_PF_STATUS             (0x0010)
0015 #define   NIC_PF_INTR_TIMER_CFG         (0x0030)
0016 #define   NIC_PF_BIST_STATUS            (0x0040)
0017 #define   NIC_PF_SOFT_RESET         (0x0050)
0018 #define   NIC_PF_TCP_TIMER          (0x0060)
0019 #define   NIC_PF_BP_CFG             (0x0080)
0020 #define   NIC_PF_RRM_CFG            (0x0088)
0021 #define   NIC_PF_CQM_CFG            (0x00A0)
0022 #define   NIC_PF_CNM_CF             (0x00A8)
0023 #define   NIC_PF_CNM_STATUS         (0x00B0)
0024 #define   NIC_PF_CQ_AVG_CFG         (0x00C0)
0025 #define   NIC_PF_RRM_AVG_CFG            (0x00C8)
0026 #define   NIC_PF_INTF_0_1_SEND_CFG      (0x0200)
0027 #define   NIC_PF_INTF_0_1_BP_CFG        (0x0208)
0028 #define   NIC_PF_INTF_0_1_BP_DIS_0_1        (0x0210)
0029 #define   NIC_PF_INTF_0_1_BP_SW_0_1     (0x0220)
0030 #define   NIC_PF_RBDR_BP_STATE_0_3      (0x0240)
0031 #define   NIC_PF_MAILBOX_INT            (0x0410)
0032 #define   NIC_PF_MAILBOX_INT_W1S        (0x0430)
0033 #define   NIC_PF_MAILBOX_ENA_W1C        (0x0450)
0034 #define   NIC_PF_MAILBOX_ENA_W1S        (0x0470)
0035 #define   NIC_PF_RX_ETYPE_0_7           (0x0500)
0036 #define   NIC_PF_RX_GENEVE_DEF          (0x0580)
0037 #define    UDP_GENEVE_PORT_NUM              0x17C1ULL
0038 #define   NIC_PF_RX_GENEVE_PROT_DEF     (0x0588)
0039 #define    IPV6_PROT                    0x86DDULL
0040 #define    IPV4_PROT                    0x800ULL
0041 #define    ET_PROT                  0x6558ULL
0042 #define   NIC_PF_RX_NVGRE_PROT_DEF      (0x0598)
0043 #define   NIC_PF_RX_VXLAN_DEF_0_1       (0x05A0)
0044 #define    UDP_VXLAN_PORT_NUM               0x12B5
0045 #define   NIC_PF_RX_VXLAN_PROT_DEF      (0x05B0)
0046 #define    IPV6_PROT_DEF                0x2ULL
0047 #define    IPV4_PROT_DEF                0x1ULL
0048 #define    ET_PROT_DEF                  0x3ULL
0049 #define   NIC_PF_RX_CFG             (0x05D0)
0050 #define   NIC_PF_PKIND_0_15_CFG         (0x0600)
0051 #define   NIC_PF_ECC0_FLIP0         (0x1000)
0052 #define   NIC_PF_ECC1_FLIP0         (0x1008)
0053 #define   NIC_PF_ECC2_FLIP0         (0x1010)
0054 #define   NIC_PF_ECC3_FLIP0         (0x1018)
0055 #define   NIC_PF_ECC0_FLIP1         (0x1080)
0056 #define   NIC_PF_ECC1_FLIP1         (0x1088)
0057 #define   NIC_PF_ECC2_FLIP1         (0x1090)
0058 #define   NIC_PF_ECC3_FLIP1         (0x1098)
0059 #define   NIC_PF_ECC0_CDIS          (0x1100)
0060 #define   NIC_PF_ECC1_CDIS          (0x1108)
0061 #define   NIC_PF_ECC2_CDIS          (0x1110)
0062 #define   NIC_PF_ECC3_CDIS          (0x1118)
0063 #define   NIC_PF_BIST0_STATUS           (0x1280)
0064 #define   NIC_PF_BIST1_STATUS           (0x1288)
0065 #define   NIC_PF_BIST2_STATUS           (0x1290)
0066 #define   NIC_PF_BIST3_STATUS           (0x1298)
0067 #define   NIC_PF_ECC0_SBE_INT           (0x2000)
0068 #define   NIC_PF_ECC0_SBE_INT_W1S       (0x2008)
0069 #define   NIC_PF_ECC0_SBE_ENA_W1C       (0x2010)
0070 #define   NIC_PF_ECC0_SBE_ENA_W1S       (0x2018)
0071 #define   NIC_PF_ECC0_DBE_INT           (0x2100)
0072 #define   NIC_PF_ECC0_DBE_INT_W1S       (0x2108)
0073 #define   NIC_PF_ECC0_DBE_ENA_W1C       (0x2110)
0074 #define   NIC_PF_ECC0_DBE_ENA_W1S       (0x2118)
0075 #define   NIC_PF_ECC1_SBE_INT           (0x2200)
0076 #define   NIC_PF_ECC1_SBE_INT_W1S       (0x2208)
0077 #define   NIC_PF_ECC1_SBE_ENA_W1C       (0x2210)
0078 #define   NIC_PF_ECC1_SBE_ENA_W1S       (0x2218)
0079 #define   NIC_PF_ECC1_DBE_INT           (0x2300)
0080 #define   NIC_PF_ECC1_DBE_INT_W1S       (0x2308)
0081 #define   NIC_PF_ECC1_DBE_ENA_W1C       (0x2310)
0082 #define   NIC_PF_ECC1_DBE_ENA_W1S       (0x2318)
0083 #define   NIC_PF_ECC2_SBE_INT           (0x2400)
0084 #define   NIC_PF_ECC2_SBE_INT_W1S       (0x2408)
0085 #define   NIC_PF_ECC2_SBE_ENA_W1C       (0x2410)
0086 #define   NIC_PF_ECC2_SBE_ENA_W1S       (0x2418)
0087 #define   NIC_PF_ECC2_DBE_INT           (0x2500)
0088 #define   NIC_PF_ECC2_DBE_INT_W1S       (0x2508)
0089 #define   NIC_PF_ECC2_DBE_ENA_W1C       (0x2510)
0090 #define   NIC_PF_ECC2_DBE_ENA_W1S       (0x2518)
0091 #define   NIC_PF_ECC3_SBE_INT           (0x2600)
0092 #define   NIC_PF_ECC3_SBE_INT_W1S       (0x2608)
0093 #define   NIC_PF_ECC3_SBE_ENA_W1C       (0x2610)
0094 #define   NIC_PF_ECC3_SBE_ENA_W1S       (0x2618)
0095 #define   NIC_PF_ECC3_DBE_INT           (0x2700)
0096 #define   NIC_PF_ECC3_DBE_INT_W1S       (0x2708)
0097 #define   NIC_PF_ECC3_DBE_ENA_W1C       (0x2710)
0098 #define   NIC_PF_ECC3_DBE_ENA_W1S       (0x2718)
0099 #define   NIC_PF_INTFX_SEND_CFG         (0x4000)
0100 #define   NIC_PF_MCAM_0_191_ENA         (0x100000)
0101 #define   NIC_PF_MCAM_0_191_M_0_5_DATA      (0x110000)
0102 #define   NIC_PF_MCAM_CTRL          (0x120000)
0103 #define   NIC_PF_CPI_0_2047_CFG         (0x200000)
0104 #define   NIC_PF_MPI_0_2047_CFG         (0x210000)
0105 #define   NIC_PF_RSSI_0_4097_RQ         (0x220000)
0106 #define   NIC_PF_LMAC_0_7_CFG           (0x240000)
0107 #define   NIC_PF_LMAC_0_7_CFG2          (0x240100)
0108 #define   NIC_PF_LMAC_0_7_SW_XOFF       (0x242000)
0109 #define   NIC_PF_LMAC_0_7_CREDIT        (0x244000)
0110 #define   NIC_PF_CHAN_0_255_TX_CFG      (0x400000)
0111 #define   NIC_PF_CHAN_0_255_RX_CFG      (0x420000)
0112 #define   NIC_PF_CHAN_0_255_SW_XOFF     (0x440000)
0113 #define   NIC_PF_CHAN_0_255_CREDIT      (0x460000)
0114 #define   NIC_PF_CHAN_0_255_RX_BP_CFG       (0x480000)
0115 #define   NIC_PF_SW_SYNC_RX         (0x490000)
0116 #define   NIC_PF_SW_SYNC_RX_DONE        (0x490008)
0117 #define   NIC_PF_TL2_0_63_CFG           (0x500000)
0118 #define   NIC_PF_TL2_0_63_PRI           (0x520000)
0119 #define   NIC_PF_TL2_LMAC           (0x540000)
0120 #define   NIC_PF_TL2_0_63_SH_STATUS     (0x580000)
0121 #define   NIC_PF_TL3A_0_63_CFG          (0x5F0000)
0122 #define   NIC_PF_TL3_0_255_CFG          (0x600000)
0123 #define   NIC_PF_TL3_0_255_CHAN         (0x620000)
0124 #define   NIC_PF_TL3_0_255_PIR          (0x640000)
0125 #define   NIC_PF_TL3_0_255_SW_XOFF      (0x660000)
0126 #define   NIC_PF_TL3_0_255_CNM_RATE     (0x680000)
0127 #define   NIC_PF_TL3_0_255_SH_STATUS        (0x6A0000)
0128 #define   NIC_PF_TL4A_0_255_CFG         (0x6F0000)
0129 #define   NIC_PF_TL4_0_1023_CFG         (0x800000)
0130 #define   NIC_PF_TL4_0_1023_SW_XOFF     (0x820000)
0131 #define   NIC_PF_TL4_0_1023_SH_STATUS       (0x840000)
0132 #define   NIC_PF_TL4A_0_1023_CNM_RATE       (0x880000)
0133 #define   NIC_PF_TL4A_0_1023_CNM_STATUS     (0x8A0000)
0134 #define   NIC_PF_VF_0_127_MAILBOX_0_1       (0x20002030)
0135 #define   NIC_PF_VNIC_0_127_TX_STAT_0_4     (0x20004000)
0136 #define   NIC_PF_VNIC_0_127_RX_STAT_0_13    (0x20004100)
0137 #define   NIC_PF_QSET_0_127_LOCK_0_15       (0x20006000)
0138 #define   NIC_PF_QSET_0_127_CFG         (0x20010000)
0139 #define   NIC_PF_QSET_0_127_RQ_0_7_CFG      (0x20010400)
0140 #define   NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG (0x20010420)
0141 #define   NIC_PF_QSET_0_127_RQ_0_7_BP_CFG   (0x20010500)
0142 #define   NIC_PF_QSET_0_127_RQ_0_7_STAT_0_1 (0x20010600)
0143 #define   NIC_PF_QSET_0_127_SQ_0_7_CFG      (0x20010C00)
0144 #define   NIC_PF_QSET_0_127_SQ_0_7_CFG2     (0x20010C08)
0145 #define   NIC_PF_QSET_0_127_SQ_0_7_STAT_0_1 (0x20010D00)
0146 
0147 #define   NIC_PF_MSIX_VEC_0_18_ADDR     (0x000000)
0148 #define   NIC_PF_MSIX_VEC_0_CTL         (0x000008)
0149 #define   NIC_PF_MSIX_PBA_0         (0x0F0000)
0150 
0151 /* Virtual function register offsets */
0152 #define   NIC_VNIC_CFG              (0x000020)
0153 #define   NIC_VF_PF_MAILBOX_0_1         (0x000130)
0154 #define   NIC_VF_INT                (0x000200)
0155 #define   NIC_VF_INT_W1S            (0x000220)
0156 #define   NIC_VF_ENA_W1C            (0x000240)
0157 #define   NIC_VF_ENA_W1S            (0x000260)
0158 
0159 #define   NIC_VNIC_RSS_CFG          (0x0020E0)
0160 #define   NIC_VNIC_RSS_KEY_0_4          (0x002200)
0161 #define   NIC_VNIC_TX_STAT_0_4          (0x004000)
0162 #define   NIC_VNIC_RX_STAT_0_13         (0x004100)
0163 #define   NIC_QSET_RQ_GEN_CFG           (0x010010)
0164 
0165 #define   NIC_QSET_CQ_0_7_CFG           (0x010400)
0166 #define   NIC_QSET_CQ_0_7_CFG2          (0x010408)
0167 #define   NIC_QSET_CQ_0_7_THRESH        (0x010410)
0168 #define   NIC_QSET_CQ_0_7_BASE          (0x010420)
0169 #define   NIC_QSET_CQ_0_7_HEAD          (0x010428)
0170 #define   NIC_QSET_CQ_0_7_TAIL          (0x010430)
0171 #define   NIC_QSET_CQ_0_7_DOOR          (0x010438)
0172 #define   NIC_QSET_CQ_0_7_STATUS        (0x010440)
0173 #define   NIC_QSET_CQ_0_7_STATUS2       (0x010448)
0174 #define   NIC_QSET_CQ_0_7_DEBUG         (0x010450)
0175 
0176 #define   NIC_QSET_RQ_0_7_CFG           (0x010600)
0177 #define   NIC_QSET_RQ_0_7_STAT_0_1      (0x010700)
0178 
0179 #define   NIC_QSET_SQ_0_7_CFG           (0x010800)
0180 #define   NIC_QSET_SQ_0_7_THRESH        (0x010810)
0181 #define   NIC_QSET_SQ_0_7_BASE          (0x010820)
0182 #define   NIC_QSET_SQ_0_7_HEAD          (0x010828)
0183 #define   NIC_QSET_SQ_0_7_TAIL          (0x010830)
0184 #define   NIC_QSET_SQ_0_7_DOOR          (0x010838)
0185 #define   NIC_QSET_SQ_0_7_STATUS        (0x010840)
0186 #define   NIC_QSET_SQ_0_7_DEBUG         (0x010848)
0187 #define   NIC_QSET_SQ_0_7_STAT_0_1      (0x010900)
0188 
0189 #define   NIC_QSET_RBDR_0_1_CFG         (0x010C00)
0190 #define   NIC_QSET_RBDR_0_1_THRESH      (0x010C10)
0191 #define   NIC_QSET_RBDR_0_1_BASE        (0x010C20)
0192 #define   NIC_QSET_RBDR_0_1_HEAD        (0x010C28)
0193 #define   NIC_QSET_RBDR_0_1_TAIL        (0x010C30)
0194 #define   NIC_QSET_RBDR_0_1_DOOR        (0x010C38)
0195 #define   NIC_QSET_RBDR_0_1_STATUS0     (0x010C40)
0196 #define   NIC_QSET_RBDR_0_1_STATUS1     (0x010C48)
0197 #define   NIC_QSET_RBDR_0_1_PREFETCH_STATUS (0x010C50)
0198 
0199 #define   NIC_VF_MSIX_VECTOR_0_19_ADDR      (0x000000)
0200 #define   NIC_VF_MSIX_VECTOR_0_19_CTL       (0x000008)
0201 #define   NIC_VF_MSIX_PBA           (0x0F0000)
0202 
0203 /* Offsets within registers */
0204 #define   NIC_MSIX_VEC_SHIFT            4
0205 #define   NIC_Q_NUM_SHIFT           18
0206 #define   NIC_QS_ID_SHIFT           21
0207 #define   NIC_VF_NUM_SHIFT          21
0208 
0209 /* Port kind configuration register */
0210 struct pkind_cfg {
0211 #if defined(__BIG_ENDIAN_BITFIELD)
0212     u64 reserved_42_63:22;
0213     u64 hdr_sl:5;   /* Header skip length */
0214     u64 rx_hdr:3;   /* TNS Receive header present */
0215     u64 lenerr_en:1;/* L2 length error check enable */
0216     u64 reserved_32_32:1;
0217     u64 maxlen:16;  /* Max frame size */
0218     u64 minlen:16;  /* Min frame size */
0219 #elif defined(__LITTLE_ENDIAN_BITFIELD)
0220     u64 minlen:16;
0221     u64 maxlen:16;
0222     u64 reserved_32_32:1;
0223     u64 lenerr_en:1;
0224     u64 rx_hdr:3;
0225     u64 hdr_sl:5;
0226     u64 reserved_42_63:22;
0227 #endif
0228 };
0229 
0230 #endif /* NIC_REG_H */
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