cavium/liquidio/octeon_mem_ops.h

0001 /**********************************************************************
0002  * Author: Cavium, Inc.
0003  *
0004  * Contact: support@cavium.com
0005  *          Please include "LiquidIO" in the subject.
0006  *
0007  * Copyright (c) 2003-2016 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  **********************************************************************/
0019
0020 /*!  \file octeon_mem_ops.h
0021  *   \brief Host Driver: Routines used to read/write Octeon memory.
0022  */
0023
0024 #ifndef __OCTEON_MEM_OPS_H__
0025 #define __OCTEON_MEM_OPS_H__
0026
0027 /**  Read a 64-bit value from a BAR1 mapped core memory address.
0028  *   @param  oct        -  pointer to the octeon device.
0029  *   @param  core_addr  -  the address to read from.
0030  *
0031  *   The range_idx gives the BAR1 index register for the range of address
0032  *   in which core_addr is mapped.
0033  *
0034  *   @return  64-bit value read from Core memory
0035  */
0036 u64 octeon_read_device_mem64(struct octeon_device *oct, u64 core_addr);
0037
0038 /**  Read a 32-bit value from a BAR1 mapped core memory address.
0039  *   @param  oct        -  pointer to the octeon device.
0040  *   @param  core_addr  -  the address to read from.
0041  *
0042  *   @return  32-bit value read from Core memory
0043  */
0044 u32 octeon_read_device_mem32(struct octeon_device *oct, u64 core_addr);
0045
0046 /**  Write a 32-bit value to a BAR1 mapped core memory address.
0047  *   @param  oct        -  pointer to the octeon device.
0048  *   @param  core_addr  -  the address to write to.
0049  *   @param  val        -  32-bit value to write.
0050  */
0051 void
0052 octeon_write_device_mem32(struct octeon_device *oct,
0053               u64 core_addr,
0054               u32 val);
0055
0056 /** Read multiple bytes from Octeon memory.
0057  */
0058 void
0059 octeon_pci_read_core_mem(struct octeon_device *oct,
0060              u64 coreaddr,
0061              u8 *buf,
0062              u32 len);
0063
0064 /** Write multiple bytes into Octeon memory.
0065  */
0066 void
0067 octeon_pci_write_core_mem(struct octeon_device *oct,
0068               u64 coreaddr,
0069               const u8 *buf,
0070               u32 len);
0071
0072 #endif