cavium/liquidio/octeon_mem_ops.c

0001 /**********************************************************************
0002  * Author: Cavium, Inc.
0003  *
0004  * Contact: support@cavium.com
0005  *          Please include "LiquidIO" in the subject.
0006  *
0007  * Copyright (c) 2003-2016 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more
0017  * details.
0018  **********************************************************************/
0019 #include <linux/netdevice.h>
0020 #include "liquidio_common.h"
0021 #include "octeon_droq.h"
0022 #include "octeon_iq.h"
0023 #include "response_manager.h"
0024 #include "octeon_device.h"
0025 #include "octeon_mem_ops.h"
0026
0027 #define MEMOPS_IDX   BAR1_INDEX_DYNAMIC_MAP
0028
0029 #ifdef __BIG_ENDIAN_BITFIELD
0030 static inline void
0031 octeon_toggle_bar1_swapmode(struct octeon_device *oct, u32 idx)
0032 {
0033     u32 mask;
0034
0035     mask = oct->fn_list.bar1_idx_read(oct, idx);
0036     mask = (mask & 0x2) ? (mask & ~2) : (mask | 2);
0037     oct->fn_list.bar1_idx_write(oct, idx, mask);
0038 }
0039 #else
0040 #define octeon_toggle_bar1_swapmode(oct, idx)
0041 #endif
0042
0043 static void
0044 octeon_pci_fastwrite(struct octeon_device *oct, u8 __iomem *mapped_addr,
0045              u8 *hostbuf, u32 len)
0046 {
0047     while ((len) && ((unsigned long)mapped_addr) & 7) {
0048         writeb(*(hostbuf++), mapped_addr++);
0049         len--;
0050     }
0051
0052     octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
0053
0054     while (len >= 8) {
0055         writeq(*((u64 *)hostbuf), mapped_addr);
0056         mapped_addr += 8;
0057         hostbuf += 8;
0058         len -= 8;
0059     }
0060
0061     octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
0062
0063     while (len--)
0064         writeb(*(hostbuf++), mapped_addr++);
0065 }
0066
0067 static void
0068 octeon_pci_fastread(struct octeon_device *oct, u8 __iomem *mapped_addr,
0069             u8 *hostbuf, u32 len)
0070 {
0071     while ((len) && ((unsigned long)mapped_addr) & 7) {
0072         *(hostbuf++) = readb(mapped_addr++);
0073         len--;
0074     }
0075
0076     octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
0077
0078     while (len >= 8) {
0079         *((u64 *)hostbuf) = readq(mapped_addr);
0080         mapped_addr += 8;
0081         hostbuf += 8;
0082         len -= 8;
0083     }
0084
0085     octeon_toggle_bar1_swapmode(oct, MEMOPS_IDX);
0086
0087     while (len--)
0088         *(hostbuf++) = readb(mapped_addr++);
0089 }
0090
0091 /* Core mem read/write with temporary bar1 settings. */
0092 /* op = 1 to read, op = 0 to write. */
0093 static void
0094 __octeon_pci_rw_core_mem(struct octeon_device *oct, u64 addr,
0095              u8 *hostbuf, u32 len, u32 op)
0096 {
0097     u32 copy_len = 0, index_reg_val = 0;
0098     unsigned long flags;
0099     u8 __iomem *mapped_addr;
0100     u64 static_mapping_base;
0101
0102     static_mapping_base = oct->console_nb_info.dram_region_base;
0103
0104     if (static_mapping_base &&
0105         static_mapping_base == (addr & ~(OCTEON_BAR1_ENTRY_SIZE - 1ULL))) {
0106         int bar1_index = oct->console_nb_info.bar1_index;
0107
0108         mapped_addr = oct->mmio[1].hw_addr
0109             + (bar1_index << ilog2(OCTEON_BAR1_ENTRY_SIZE))
0110             + (addr & (OCTEON_BAR1_ENTRY_SIZE - 1ULL));
0111
0112         if (op)
0113             octeon_pci_fastread(oct, mapped_addr, hostbuf, len);
0114         else
0115             octeon_pci_fastwrite(oct, mapped_addr, hostbuf, len);
0116
0117         return;
0118     }
0119
0120     spin_lock_irqsave(&oct->mem_access_lock, flags);
0121
0122     /* Save the original index reg value. */
0123     index_reg_val = oct->fn_list.bar1_idx_read(oct, MEMOPS_IDX);
0124     do {
0125         oct->fn_list.bar1_idx_setup(oct, addr, MEMOPS_IDX, 1);
0126         mapped_addr = oct->mmio[1].hw_addr
0127             + (MEMOPS_IDX << 22) + (addr & 0x3fffff);
0128
0129         /* If operation crosses a 4MB boundary, split the transfer
0130          * at the 4MB
0131          * boundary.
0132          */
0133         if (((addr + len - 1) & ~(0x3fffff)) != (addr & ~(0x3fffff))) {
0134             copy_len = (u32)(((addr & ~(0x3fffff)) +
0135                    (MEMOPS_IDX << 22)) - addr);
0136         } else {
0137             copy_len = len;
0138         }
0139
0140         if (op) {   /* read from core */
0141             octeon_pci_fastread(oct, mapped_addr, hostbuf,
0142                         copy_len);
0143         } else {
0144             octeon_pci_fastwrite(oct, mapped_addr, hostbuf,
0145                          copy_len);
0146         }
0147
0148         len -= copy_len;
0149         addr += copy_len;
0150         hostbuf += copy_len;
0151
0152     } while (len);
0153
0154     oct->fn_list.bar1_idx_write(oct, MEMOPS_IDX, index_reg_val);
0155
0156     spin_unlock_irqrestore(&oct->mem_access_lock, flags);
0157 }
0158
0159 void
0160 octeon_pci_read_core_mem(struct octeon_device *oct,
0161              u64 coreaddr,
0162              u8 *buf,
0163              u32 len)
0164 {
0165     __octeon_pci_rw_core_mem(oct, coreaddr, buf, len, 1);
0166 }
0167
0168 void
0169 octeon_pci_write_core_mem(struct octeon_device *oct,
0170               u64 coreaddr,
0171               const u8 *buf,
0172               u32 len)
0173 {
0174     __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)buf, len, 0);
0175 }
0176
0177 u64 octeon_read_device_mem64(struct octeon_device *oct, u64 coreaddr)
0178 {
0179     __be64 ret;
0180
0181     __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&ret, 8, 1);
0182
0183     return be64_to_cpu(ret);
0184 }
0185
0186 u32 octeon_read_device_mem32(struct octeon_device *oct, u64 coreaddr)
0187 {
0188     __be32 ret;
0189
0190     __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&ret, 4, 1);
0191
0192     return be32_to_cpu(ret);
0193 }
0194
0195 void octeon_write_device_mem32(struct octeon_device *oct, u64 coreaddr,
0196                    u32 val)
0197 {
0198     __be32 t = cpu_to_be32(val);
0199
0200     __octeon_pci_rw_core_mem(oct, coreaddr, (u8 *)&t, 4, 0);
0201 }