cavium/liquidio/octeon_iq.h

0001 /**********************************************************************
0002  * Author: Cavium, Inc.
0003  *
0004  * Contact: support@cavium.com
0005  *          Please include "LiquidIO" in the subject.
0006  *
0007  * Copyright (c) 2003-2016 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more details.
0017  ***********************************************************************/
0018 /*!  \file  octeon_iq.h
0019  *   \brief Host Driver: Implementation of Octeon input queues. "Input" is
0020  *   with respect to the Octeon device on the NIC. From this driver's
0021  *   point of view they are egress queues.
0022  */
0023
0024 #ifndef __OCTEON_IQ_H__
0025 #define  __OCTEON_IQ_H__
0026
0027 #define IQ_STATUS_RUNNING   1
0028
0029 #define IQ_SEND_OK          0
0030 #define IQ_SEND_STOP        1
0031 #define IQ_SEND_FAILED     -1
0032
0033 /*-------------------------  INSTRUCTION QUEUE --------------------------*/
0034
0035 /* \cond */
0036
0037 #define REQTYPE_NONE                 0
0038 #define REQTYPE_NORESP_NET           1
0039 #define REQTYPE_NORESP_NET_SG        2
0040 #define REQTYPE_RESP_NET             3
0041 #define REQTYPE_RESP_NET_SG          4
0042 #define REQTYPE_SOFT_COMMAND         5
0043 #define REQTYPE_LAST                 5
0044
0045 struct octeon_request_list {
0046     u32 reqtype;
0047     void *buf;
0048 };
0049
0050 /* \endcond */
0051
0052 /** Input Queue statistics. Each input queue has four stats fields. */
0053 struct oct_iq_stats {
0054     u64 instr_posted; /**< Instructions posted to this queue. */
0055     u64 instr_processed; /**< Instructions processed in this queue. */
0056     u64 instr_dropped; /**< Instructions that could not be processed */
0057     u64 bytes_sent;  /**< Bytes sent through this queue. */
0058     u64 sgentry_sent;/**< Gather entries sent through this queue. */
0059     u64 tx_done;/**< Num of packets sent to network. */
0060     u64 tx_iq_busy;/**< Numof times this iq was found to be full. */
0061     u64 tx_dropped;/**< Numof pkts dropped dueto xmitpath errors. */
0062     u64 tx_tot_bytes;/**< Total count of bytes sento to network. */
0063     u64 tx_gso;  /* count of tso */
0064     u64 tx_vxlan; /* tunnel */
0065     u64 tx_dmamap_fail; /* Number of times dma mapping failed */
0066     u64 tx_restart; /* Number of times this queue restarted */
0067 };
0068
0069 #define OCT_IQ_STATS_SIZE   (sizeof(struct oct_iq_stats))
0070
0071 /** The instruction (input) queue.
0072  *  The input queue is used to post raw (instruction) mode data or packet
0073  *  data to Octeon device from the host. Each input queue (upto 4) for
0074  *  a Octeon device has one such structure to represent it.
0075  */
0076 struct octeon_instr_queue {
0077     struct octeon_device *oct_dev;
0078
0079     /** A spinlock to protect access to the input ring.  */
0080     spinlock_t lock;
0081
0082     /** A spinlock to protect while posting on the ring.  */
0083     spinlock_t post_lock;
0084
0085     /** This flag indicates if the queue can be used for soft commands.
0086      *  If this flag is set, post_lock must be acquired before posting
0087      *  a command to the queue.
0088      *  If this flag is clear, post_lock is invalid for the queue.
0089      *  All control commands (soft commands) will go through only Queue 0
0090      *  (control and data queue). So only queue-0 needs post_lock,
0091      *  other queues are only data queues and does not need post_lock
0092      */
0093     bool allow_soft_cmds;
0094
0095     u32 pkt_in_done;
0096
0097     u32 pkts_processed;
0098
0099     /** A spinlock to protect access to the input ring.*/
0100     spinlock_t iq_flush_running_lock;
0101
0102     /** Flag that indicates if the queue uses 64 byte commands. */
0103     u32 iqcmd_64B:1;
0104
0105     /** Queue info. */
0106     union oct_txpciq txpciq;
0107
0108     u32 rsvd:17;
0109
0110     /* Controls whether extra flushing of IQ is done on Tx */
0111     u32 do_auto_flush:1;
0112
0113     u32 status:8;
0114
0115     /** Maximum no. of instructions in this queue. */
0116     u32 max_count;
0117
0118     /** Index in input ring where the driver should write the next packet */
0119     u32 host_write_index;
0120
0121     /** Index in input ring where Octeon is expected to read the next
0122      * packet.
0123      */
0124     u32 octeon_read_index;
0125
0126     /** This index aids in finding the window in the queue where Octeon
0127      *  has read the commands.
0128      */
0129     u32 flush_index;
0130
0131     /** This field keeps track of the instructions pending in this queue. */
0132     atomic_t instr_pending;
0133
0134     u32 reset_instr_cnt;
0135
0136     /** Pointer to the Virtual Base addr of the input ring. */
0137     u8 *base_addr;
0138
0139     struct octeon_request_list *request_list;
0140
0141     /** Octeon doorbell register for the ring. */
0142     void __iomem *doorbell_reg;
0143
0144     /** Octeon instruction count register for this ring. */
0145     void __iomem *inst_cnt_reg;
0146
0147     /** Number of instructions pending to be posted to Octeon. */
0148     u32 fill_cnt;
0149
0150     /** The max. number of instructions that can be held pending by the
0151      * driver.
0152      */
0153     u32 fill_threshold;
0154
0155     /** The last time that the doorbell was rung. */
0156     u64 last_db_time;
0157
0158     /** The doorbell timeout. If the doorbell was not rung for this time and
0159      * fill_cnt is non-zero, ring the doorbell again.
0160      */
0161     u32 db_timeout;
0162
0163     /** Statistics for this input queue. */
0164     struct oct_iq_stats stats;
0165
0166     /** DMA mapped base address of the input descriptor ring. */
0167     dma_addr_t base_addr_dma;
0168
0169     /** Application context */
0170     void *app_ctx;
0171
0172     /* network stack queue index */
0173     int q_index;
0174
0175     /*os ifidx associated with this queue */
0176     int ifidx;
0177
0178 };
0179
0180 /*----------------------  INSTRUCTION FORMAT ----------------------------*/
0181
0182 /** 32-byte instruction format.
0183  *  Format of instruction for a 32-byte mode input queue.
0184  */
0185 struct octeon_instr_32B {
0186     /** Pointer where the input data is available. */
0187     u64 dptr;
0188
0189     /** Instruction Header.  */
0190     u64 ih;
0191
0192     /** Pointer where the response for a RAW mode packet will be written
0193      * by Octeon.
0194      */
0195     u64 rptr;
0196
0197     /** Input Request Header. Additional info about the input. */
0198     u64 irh;
0199
0200 };
0201
0202 #define OCT_32B_INSTR_SIZE     (sizeof(struct octeon_instr_32B))
0203
0204 /** 64-byte instruction format.
0205  *  Format of instruction for a 64-byte mode input queue.
0206  */
0207 struct octeon_instr2_64B {
0208     /** Pointer where the input data is available. */
0209     u64 dptr;
0210
0211     /** Instruction Header. */
0212     u64 ih2;
0213
0214     /** Input Request Header. */
0215     u64 irh;
0216
0217     /** opcode/subcode specific parameters */
0218     u64 ossp[2];
0219
0220     /** Return Data Parameters */
0221     u64 rdp;
0222
0223     /** Pointer where the response for a RAW mode packet will be written
0224      * by Octeon.
0225      */
0226     u64 rptr;
0227
0228     u64 reserved;
0229 };
0230
0231 struct octeon_instr3_64B {
0232     /** Pointer where the input data is available. */
0233     u64 dptr;
0234
0235     /** Instruction Header. */
0236     u64 ih3;
0237
0238     /** Instruction Header. */
0239     u64 pki_ih3;
0240
0241     /** Input Request Header. */
0242     u64 irh;
0243
0244     /** opcode/subcode specific parameters */
0245     u64 ossp[2];
0246
0247     /** Return Data Parameters */
0248     u64 rdp;
0249
0250     /** Pointer where the response for a RAW mode packet will be written
0251      * by Octeon.
0252      */
0253     u64 rptr;
0254
0255 };
0256
0257 union octeon_instr_64B {
0258     struct octeon_instr2_64B cmd2;
0259     struct octeon_instr3_64B cmd3;
0260 };
0261
0262 #define OCT_64B_INSTR_SIZE     (sizeof(union octeon_instr_64B))
0263
0264 /** The size of each buffer in soft command buffer pool
0265  */
0266 #define  SOFT_COMMAND_BUFFER_SIZE   2048
0267
0268 struct octeon_soft_command {
0269     /** Soft command buffer info. */
0270     struct list_head node;
0271     u64 dma_addr;
0272     u32 size;
0273
0274     /** Command and return status */
0275     union octeon_instr_64B cmd;
0276
0277 #define COMPLETION_WORD_INIT    0xffffffffffffffffULL
0278     u64 *status_word;
0279
0280     /** Data buffer info */
0281     void *virtdptr;
0282     u64 dmadptr;
0283     u32 datasize;
0284
0285     /** Return buffer info */
0286     void *virtrptr;
0287     u64 dmarptr;
0288     u32 rdatasize;
0289
0290     /** Context buffer info */
0291     void *ctxptr;
0292     u32  ctxsize;
0293
0294     /** Time out and callback */
0295     size_t expiry_time;
0296     u32 iq_no;
0297     void (*callback)(struct octeon_device *, u32, void *);
0298     void *callback_arg;
0299
0300     int caller_is_done;
0301     u32 sc_status;
0302     struct completion complete;
0303 };
0304
0305 /* max timeout (in milli sec) for soft request */
0306 #define LIO_SC_MAX_TMO_MS       60000
0307
0308 /** Maximum number of buffers to allocate into soft command buffer pool
0309  */
0310 #define  MAX_SOFT_COMMAND_BUFFERS   256
0311
0312 /** Head of a soft command buffer pool.
0313  */
0314 struct octeon_sc_buffer_pool {
0315     /** List structure to add delete pending entries to */
0316     struct list_head head;
0317
0318     /** A lock for this response list */
0319     spinlock_t lock;
0320
0321     atomic_t alloc_buf_count;
0322 };
0323
0324 #define INCR_INSTRQUEUE_PKT_COUNT(octeon_dev_ptr, iq_no, field, count)  \
0325         (((octeon_dev_ptr)->instr_queue[iq_no]->stats.field) += count)
0326
0327 int octeon_setup_sc_buffer_pool(struct octeon_device *oct);
0328 int octeon_free_sc_done_list(struct octeon_device *oct);
0329 int octeon_free_sc_zombie_list(struct octeon_device *oct);
0330 int octeon_free_sc_buffer_pool(struct octeon_device *oct);
0331 struct octeon_soft_command *
0332     octeon_alloc_soft_command(struct octeon_device *oct,
0333                   u32 datasize, u32 rdatasize,
0334                   u32 ctxsize);
0335 void octeon_free_soft_command(struct octeon_device *oct,
0336                   struct octeon_soft_command *sc);
0337
0338 /**
0339  *  octeon_init_instr_queue()
0340  *  @param octeon_dev      - pointer to the octeon device structure.
0341  *  @param txpciq          - queue to be initialized (0 <= q_no <= 3).
0342  *
0343  *  Called at driver init time for each input queue. iq_conf has the
0344  *  configuration parameters for the queue.
0345  *
0346  *  @return  Success: 0   Failure: 1
0347  */
0348 int octeon_init_instr_queue(struct octeon_device *octeon_dev,
0349                 union oct_txpciq txpciq,
0350                 u32 num_descs);
0351
0352 /**
0353  *  octeon_delete_instr_queue()
0354  *  @param octeon_dev      - pointer to the octeon device structure.
0355  *  @param iq_no           - queue to be deleted (0 <= q_no <= 3).
0356  *
0357  *  Called at driver unload time for each input queue. Deletes all
0358  *  allocated resources for the input queue.
0359  *
0360  *  @return  Success: 0   Failure: 1
0361  */
0362 int octeon_delete_instr_queue(struct octeon_device *octeon_dev, u32 iq_no);
0363
0364 int lio_wait_for_instr_fetch(struct octeon_device *oct);
0365
0366 void
0367 octeon_ring_doorbell_locked(struct octeon_device *oct, u32 iq_no);
0368
0369 int
0370 octeon_register_reqtype_free_fn(struct octeon_device *oct, int reqtype,
0371                 void (*fn)(void *));
0372
0373 int
0374 lio_process_iq_request_list(struct octeon_device *oct,
0375                 struct octeon_instr_queue *iq, u32 napi_budget);
0376
0377 int octeon_send_command(struct octeon_device *oct, u32 iq_no,
0378             u32 force_db, void *cmd, void *buf,
0379             u32 datasize, u32 reqtype);
0380
0381 void octeon_dump_soft_command(struct octeon_device *oct,
0382                   struct octeon_soft_command *sc);
0383
0384 void octeon_prepare_soft_command(struct octeon_device *oct,
0385                  struct octeon_soft_command *sc,
0386                  u8 opcode, u8 subcode,
0387                  u32 irh_ossp, u64 ossp0,
0388                  u64 ossp1);
0389
0390 int octeon_send_soft_command(struct octeon_device *oct,
0391                  struct octeon_soft_command *sc);
0392
0393 int octeon_setup_iq(struct octeon_device *oct, int ifidx,
0394             int q_index, union oct_txpciq iq_no, u32 num_descs,
0395             void *app_ctx);
0396 int
0397 octeon_flush_iq(struct octeon_device *oct, struct octeon_instr_queue *iq,
0398         u32 napi_budget);
0399 #endif              /* __OCTEON_IQ_H__ */