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0001 /**********************************************************************
0002  * Author: Cavium, Inc.
0003  *
0004  * Contact: support@cavium.com
0005  *          Please include "LiquidIO" in the subject.
0006  *
0007  * Copyright (c) 2003-2016 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more details.
0017  ***********************************************************************/
0018 /*
0019  * @file octeon_console.c
0020  */
0021 #include <linux/moduleparam.h>
0022 #include <linux/pci.h>
0023 #include <linux/netdevice.h>
0024 #include <linux/crc32.h>
0025 #include "liquidio_common.h"
0026 #include "octeon_droq.h"
0027 #include "octeon_iq.h"
0028 #include "response_manager.h"
0029 #include "octeon_device.h"
0030 #include "liquidio_image.h"
0031 #include "octeon_mem_ops.h"
0032 
0033 static void octeon_remote_lock(void);
0034 static void octeon_remote_unlock(void);
0035 static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct,
0036                          const char *name,
0037                          u32 flags);
0038 static int octeon_console_read(struct octeon_device *oct, u32 console_num,
0039                    char *buffer, u32 buf_size);
0040 
0041 #define BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR    0x0006c008
0042 #define BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR     0x0006c004
0043 #define BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR   0x0006c000
0044 #define BOOTLOADER_PCI_READ_DESC_ADDR           0x0006c100
0045 #define BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN     248
0046 
0047 #define OCTEON_PCI_IO_BUF_OWNER_OCTEON    0x00000001
0048 #define OCTEON_PCI_IO_BUF_OWNER_HOST      0x00000002
0049 
0050 /** Can change without breaking ABI */
0051 #define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
0052 
0053 /** minimum alignment of bootmem alloced blocks */
0054 #define CVMX_BOOTMEM_ALIGNMENT_SIZE     (16ull)
0055 
0056 /** CVMX bootmem descriptor major version */
0057 #define CVMX_BOOTMEM_DESC_MAJ_VER   3
0058 /* CVMX bootmem descriptor minor version */
0059 #define CVMX_BOOTMEM_DESC_MIN_VER   0
0060 
0061 /* Current versions */
0062 #define OCTEON_PCI_CONSOLE_MAJOR_VERSION    1
0063 #define OCTEON_PCI_CONSOLE_MINOR_VERSION    0
0064 #define OCTEON_PCI_CONSOLE_BLOCK_NAME   "__pci_console"
0065 #define OCTEON_CONSOLE_POLL_INTERVAL_MS  100    /* 10 times per second */
0066 
0067 /* First three members of cvmx_bootmem_desc are left in original
0068  * positions for backwards compatibility.
0069  * Assumes big endian target
0070  */
0071 struct cvmx_bootmem_desc {
0072     /** spinlock to control access to list */
0073     u32 lock;
0074 
0075     /** flags for indicating various conditions */
0076     u32 flags;
0077 
0078     u64 head_addr;
0079 
0080     /** incremented changed when incompatible changes made */
0081     u32 major_version;
0082 
0083     /** incremented changed when compatible changes made,
0084      *  reset to zero when major incremented
0085      */
0086     u32 minor_version;
0087 
0088     u64 app_data_addr;
0089     u64 app_data_size;
0090 
0091     /** number of elements in named blocks array */
0092     u32 nb_num_blocks;
0093 
0094     /** length of name array in bootmem blocks */
0095     u32 named_block_name_len;
0096 
0097     /** address of named memory block descriptors */
0098     u64 named_block_array_addr;
0099 };
0100 
0101 /* Structure that defines a single console.
0102  *
0103  * Note: when read_index == write_index, the buffer is empty.
0104  * The actual usable size of each console is console_buf_size -1;
0105  */
0106 struct octeon_pci_console {
0107     u64 input_base_addr;
0108     u32 input_read_index;
0109     u32 input_write_index;
0110     u64 output_base_addr;
0111     u32 output_read_index;
0112     u32 output_write_index;
0113     u32 lock;
0114     u32 buf_size;
0115 };
0116 
0117 /* This is the main container structure that contains all the information
0118  * about all PCI consoles.  The address of this structure is passed to various
0119  * routines that operation on PCI consoles.
0120  */
0121 struct octeon_pci_console_desc {
0122     u32 major_version;
0123     u32 minor_version;
0124     u32 lock;
0125     u32 flags;
0126     u32 num_consoles;
0127     u32 pad;
0128     /* must be 64 bit aligned here... */
0129     /* Array of addresses of octeon_pci_console structures */
0130     u64 console_addr_array[];
0131     /* Implicit storage for console_addr_array */
0132 };
0133 
0134 /*
0135  * This function is the implementation of the get macros defined
0136  * for individual structure members. The argument are generated
0137  * by the macros inorder to read only the needed memory.
0138  *
0139  * @param oct    Pointer to current octeon device
0140  * @param base   64bit physical address of the complete structure
0141  * @param offset Offset from the beginning of the structure to the member being
0142  *               accessed.
0143  * @param size   Size of the structure member.
0144  *
0145  * @return Value of the structure member promoted into a u64.
0146  */
0147 static inline u64 __cvmx_bootmem_desc_get(struct octeon_device *oct,
0148                       u64 base,
0149                       u32 offset,
0150                       u32 size)
0151 {
0152     base = (1ull << 63) | (base + offset);
0153     switch (size) {
0154     case 4:
0155         return octeon_read_device_mem32(oct, base);
0156     case 8:
0157         return octeon_read_device_mem64(oct, base);
0158     default:
0159         return 0;
0160     }
0161 }
0162 
0163 /*
0164  * This function retrieves the string name of a named block. It is
0165  * more complicated than a simple memcpy() since the named block
0166  * descriptor may not be directly accessible.
0167  *
0168  * @param addr   Physical address of the named block descriptor
0169  * @param str    String to receive the named block string name
0170  * @param len    Length of the string buffer, which must match the length
0171  *               stored in the bootmem descriptor.
0172  */
0173 static void CVMX_BOOTMEM_NAMED_GET_NAME(struct octeon_device *oct,
0174                     u64 addr,
0175                     char *str,
0176                     u32 len)
0177 {
0178     addr += offsetof(struct cvmx_bootmem_named_block_desc, name);
0179     octeon_pci_read_core_mem(oct, addr, (u8 *)str, len);
0180     str[len] = 0;
0181 }
0182 
0183 /* See header file for descriptions of functions */
0184 
0185 /*
0186  * Check the version information on the bootmem descriptor
0187  *
0188  * @param exact_match
0189  *               Exact major version to check against. A zero means
0190  *               check that the version supports named blocks.
0191  *
0192  * @return Zero if the version is correct. Negative if the version is
0193  *         incorrect. Failures also cause a message to be displayed.
0194  */
0195 static int __cvmx_bootmem_check_version(struct octeon_device *oct,
0196                     u32 exact_match)
0197 {
0198     u32 major_version;
0199     u32 minor_version;
0200 
0201     if (!oct->bootmem_desc_addr)
0202         oct->bootmem_desc_addr =
0203             octeon_read_device_mem64(oct,
0204                          BOOTLOADER_PCI_READ_DESC_ADDR);
0205     major_version = (u32)__cvmx_bootmem_desc_get(
0206             oct, oct->bootmem_desc_addr,
0207             offsetof(struct cvmx_bootmem_desc, major_version),
0208             sizeof_field(struct cvmx_bootmem_desc, major_version));
0209     minor_version = (u32)__cvmx_bootmem_desc_get(
0210             oct, oct->bootmem_desc_addr,
0211             offsetof(struct cvmx_bootmem_desc, minor_version),
0212             sizeof_field(struct cvmx_bootmem_desc, minor_version));
0213 
0214     dev_dbg(&oct->pci_dev->dev, "%s: major_version=%d\n", __func__,
0215         major_version);
0216     if ((major_version > 3) ||
0217         (exact_match && major_version != exact_match)) {
0218         dev_err(&oct->pci_dev->dev, "bootmem ver mismatch %d.%d addr:0x%llx\n",
0219             major_version, minor_version,
0220             (long long)oct->bootmem_desc_addr);
0221         return -1;
0222     } else {
0223         return 0;
0224     }
0225 }
0226 
0227 static const struct cvmx_bootmem_named_block_desc
0228 *__cvmx_bootmem_find_named_block_flags(struct octeon_device *oct,
0229                     const char *name, u32 flags)
0230 {
0231     struct cvmx_bootmem_named_block_desc *desc =
0232         &oct->bootmem_named_block_desc;
0233     u64 named_addr = cvmx_bootmem_phy_named_block_find(oct, name, flags);
0234 
0235     if (named_addr) {
0236         desc->base_addr = __cvmx_bootmem_desc_get(
0237                 oct, named_addr,
0238                 offsetof(struct cvmx_bootmem_named_block_desc,
0239                      base_addr),
0240                 sizeof_field(
0241                     struct cvmx_bootmem_named_block_desc,
0242                     base_addr));
0243         desc->size = __cvmx_bootmem_desc_get(oct, named_addr,
0244                 offsetof(struct cvmx_bootmem_named_block_desc,
0245                      size),
0246                 sizeof_field(
0247                     struct cvmx_bootmem_named_block_desc,
0248                     size));
0249 
0250         strncpy(desc->name, name, sizeof(desc->name));
0251         desc->name[sizeof(desc->name) - 1] = 0;
0252         return &oct->bootmem_named_block_desc;
0253     } else {
0254         return NULL;
0255     }
0256 }
0257 
0258 static u64 cvmx_bootmem_phy_named_block_find(struct octeon_device *oct,
0259                          const char *name,
0260                          u32 flags)
0261 {
0262     u64 result = 0;
0263 
0264     if (!__cvmx_bootmem_check_version(oct, 3)) {
0265         u32 i;
0266 
0267         u64 named_block_array_addr = __cvmx_bootmem_desc_get(
0268                     oct, oct->bootmem_desc_addr,
0269                     offsetof(struct cvmx_bootmem_desc,
0270                          named_block_array_addr),
0271                     sizeof_field(struct cvmx_bootmem_desc,
0272                              named_block_array_addr));
0273         u32 num_blocks = (u32)__cvmx_bootmem_desc_get(
0274                     oct, oct->bootmem_desc_addr,
0275                     offsetof(struct cvmx_bootmem_desc,
0276                          nb_num_blocks),
0277                     sizeof_field(struct cvmx_bootmem_desc,
0278                              nb_num_blocks));
0279 
0280         u32 name_length = (u32)__cvmx_bootmem_desc_get(
0281                     oct, oct->bootmem_desc_addr,
0282                     offsetof(struct cvmx_bootmem_desc,
0283                          named_block_name_len),
0284                     sizeof_field(struct cvmx_bootmem_desc,
0285                              named_block_name_len));
0286 
0287         u64 named_addr = named_block_array_addr;
0288 
0289         for (i = 0; i < num_blocks; i++) {
0290             u64 named_size = __cvmx_bootmem_desc_get(
0291                     oct, named_addr,
0292                      offsetof(
0293                     struct cvmx_bootmem_named_block_desc,
0294                     size),
0295                      sizeof_field(
0296                     struct cvmx_bootmem_named_block_desc,
0297                     size));
0298 
0299             if (name && named_size) {
0300                 char *name_tmp =
0301                     kmalloc(name_length + 1, GFP_KERNEL);
0302                 if (!name_tmp)
0303                     break;
0304 
0305                 CVMX_BOOTMEM_NAMED_GET_NAME(oct, named_addr,
0306                                 name_tmp,
0307                                 name_length);
0308                 if (!strncmp(name, name_tmp, name_length)) {
0309                     result = named_addr;
0310                     kfree(name_tmp);
0311                     break;
0312                 }
0313                 kfree(name_tmp);
0314             } else if (!name && !named_size) {
0315                 result = named_addr;
0316                 break;
0317             }
0318 
0319             named_addr +=
0320                 sizeof(struct cvmx_bootmem_named_block_desc);
0321         }
0322     }
0323     return result;
0324 }
0325 
0326 /*
0327  * Find a named block on the remote Octeon
0328  *
0329  * @param name      Name of block to find
0330  * @param base_addr Address the block is at (OUTPUT)
0331  * @param size      The size of the block (OUTPUT)
0332  *
0333  * @return Zero on success, One on failure.
0334  */
0335 static int octeon_named_block_find(struct octeon_device *oct, const char *name,
0336                    u64 *base_addr, u64 *size)
0337 {
0338     const struct cvmx_bootmem_named_block_desc *named_block;
0339 
0340     octeon_remote_lock();
0341     named_block = __cvmx_bootmem_find_named_block_flags(oct, name, 0);
0342     octeon_remote_unlock();
0343     if (named_block) {
0344         *base_addr = named_block->base_addr;
0345         *size = named_block->size;
0346         return 0;
0347     }
0348     return 1;
0349 }
0350 
0351 static void octeon_remote_lock(void)
0352 {
0353     /* fill this in if any sharing is needed */
0354 }
0355 
0356 static void octeon_remote_unlock(void)
0357 {
0358     /* fill this in if any sharing is needed */
0359 }
0360 
0361 int octeon_console_send_cmd(struct octeon_device *oct, char *cmd_str,
0362                 u32 wait_hundredths)
0363 {
0364     u32 len = (u32)strlen(cmd_str);
0365 
0366     dev_dbg(&oct->pci_dev->dev, "sending \"%s\" to bootloader\n", cmd_str);
0367 
0368     if (len > BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1) {
0369         dev_err(&oct->pci_dev->dev, "Command string too long, max length is: %d\n",
0370             BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN - 1);
0371         return -1;
0372     }
0373 
0374     if (octeon_wait_for_bootloader(oct, wait_hundredths) != 0) {
0375         dev_err(&oct->pci_dev->dev, "Bootloader not ready for command.\n");
0376         return -1;
0377     }
0378 
0379     /* Write command to bootloader */
0380     octeon_remote_lock();
0381     octeon_pci_write_core_mem(oct, BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR,
0382                   (u8 *)cmd_str, len);
0383     octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR,
0384                   len);
0385     octeon_write_device_mem32(oct, BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR,
0386                   OCTEON_PCI_IO_BUF_OWNER_OCTEON);
0387 
0388     /* Bootloader should accept command very quickly
0389      * if it really was ready
0390      */
0391     if (octeon_wait_for_bootloader(oct, 200) != 0) {
0392         octeon_remote_unlock();
0393         dev_err(&oct->pci_dev->dev, "Bootloader did not accept command.\n");
0394         return -1;
0395     }
0396     octeon_remote_unlock();
0397     return 0;
0398 }
0399 
0400 int octeon_wait_for_bootloader(struct octeon_device *oct,
0401                    u32 wait_time_hundredths)
0402 {
0403     dev_dbg(&oct->pci_dev->dev, "waiting %d0 ms for bootloader\n",
0404         wait_time_hundredths);
0405 
0406     if (octeon_mem_access_ok(oct))
0407         return -1;
0408 
0409     while (wait_time_hundredths > 0 &&
0410            octeon_read_device_mem32(oct,
0411                     BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR)
0412            != OCTEON_PCI_IO_BUF_OWNER_HOST) {
0413         if (--wait_time_hundredths <= 0)
0414             return -1;
0415         schedule_timeout_uninterruptible(HZ / 100);
0416     }
0417     return 0;
0418 }
0419 
0420 static void octeon_console_handle_result(struct octeon_device *oct,
0421                      size_t console_num)
0422 {
0423     struct octeon_console *console;
0424 
0425     console = &oct->console[console_num];
0426 
0427     console->waiting = 0;
0428 }
0429 
0430 static char console_buffer[OCTEON_CONSOLE_MAX_READ_BYTES];
0431 
0432 static void output_console_line(struct octeon_device *oct,
0433                 struct octeon_console *console,
0434                 size_t console_num,
0435                 char *console_buffer,
0436                 s32 bytes_read)
0437 {
0438     char *line;
0439     s32 i;
0440     size_t len;
0441 
0442     line = console_buffer;
0443     for (i = 0; i < bytes_read; i++) {
0444         /* Output a line at a time, prefixed */
0445         if (console_buffer[i] == '\n') {
0446             console_buffer[i] = '\0';
0447             /* We need to output 'line', prefaced by 'leftover'.
0448              * However, it is possible we're being called to
0449              * output 'leftover' by itself (in the case of nothing
0450              * having been read from the console).
0451              *
0452              * To avoid duplication, check for this condition.
0453              */
0454             if (console->leftover[0] &&
0455                 (line != console->leftover)) {
0456                 if (console->print)
0457                     (*console->print)(oct, (u32)console_num,
0458                               console->leftover,
0459                               line);
0460                 console->leftover[0] = '\0';
0461             } else {
0462                 if (console->print)
0463                     (*console->print)(oct, (u32)console_num,
0464                               line, NULL);
0465             }
0466             line = &console_buffer[i + 1];
0467         }
0468     }
0469 
0470     /* Save off any leftovers */
0471     if (line != &console_buffer[bytes_read]) {
0472         console_buffer[bytes_read] = '\0';
0473         len = strlen(console->leftover);
0474         strncpy(&console->leftover[len], line,
0475             sizeof(console->leftover) - len);
0476     }
0477 }
0478 
0479 static void check_console(struct work_struct *work)
0480 {
0481     s32 bytes_read, tries, total_read;
0482     size_t len;
0483     struct octeon_console *console;
0484     struct cavium_wk *wk = (struct cavium_wk *)work;
0485     struct octeon_device *oct = (struct octeon_device *)wk->ctxptr;
0486     u32 console_num = (u32)wk->ctxul;
0487     u32 delay;
0488 
0489     console = &oct->console[console_num];
0490     tries = 0;
0491     total_read = 0;
0492 
0493     do {
0494         /* Take console output regardless of whether it will
0495          * be logged
0496          */
0497         bytes_read =
0498             octeon_console_read(oct, console_num, console_buffer,
0499                         sizeof(console_buffer) - 1);
0500         if (bytes_read > 0) {
0501             total_read += bytes_read;
0502             if (console->waiting)
0503                 octeon_console_handle_result(oct, console_num);
0504             if (console->print) {
0505                 output_console_line(oct, console, console_num,
0506                             console_buffer, bytes_read);
0507             }
0508         } else if (bytes_read < 0) {
0509             dev_err(&oct->pci_dev->dev, "Error reading console %u, ret=%d\n",
0510                 console_num, bytes_read);
0511         }
0512 
0513         tries++;
0514     } while ((bytes_read > 0) && (tries < 16));
0515 
0516     /* If nothing is read after polling the console,
0517      * output any leftovers if any
0518      */
0519     if (console->print && (total_read == 0) &&
0520         (console->leftover[0])) {
0521         /* append '\n' as terminator for 'output_console_line' */
0522         len = strlen(console->leftover);
0523         console->leftover[len] = '\n';
0524         output_console_line(oct, console, console_num,
0525                     console->leftover, (s32)(len + 1));
0526         console->leftover[0] = '\0';
0527     }
0528 
0529     delay = OCTEON_CONSOLE_POLL_INTERVAL_MS;
0530 
0531     schedule_delayed_work(&wk->work, msecs_to_jiffies(delay));
0532 }
0533 
0534 int octeon_init_consoles(struct octeon_device *oct)
0535 {
0536     int ret = 0;
0537     u64 addr, size;
0538 
0539     ret = octeon_mem_access_ok(oct);
0540     if (ret) {
0541         dev_err(&oct->pci_dev->dev, "Memory access not okay'\n");
0542         return ret;
0543     }
0544 
0545     ret = octeon_named_block_find(oct, OCTEON_PCI_CONSOLE_BLOCK_NAME, &addr,
0546                       &size);
0547     if (ret) {
0548         dev_err(&oct->pci_dev->dev, "Could not find console '%s'\n",
0549             OCTEON_PCI_CONSOLE_BLOCK_NAME);
0550         return ret;
0551     }
0552 
0553     /* Dedicate one of Octeon's BAR1 index registers to create a static
0554      * mapping to a region of Octeon DRAM that contains the PCI console
0555      * named block.
0556      */
0557     oct->console_nb_info.bar1_index = BAR1_INDEX_STATIC_MAP;
0558     oct->fn_list.bar1_idx_setup(oct, addr, oct->console_nb_info.bar1_index,
0559                     true);
0560     oct->console_nb_info.dram_region_base = addr
0561         & ~(OCTEON_BAR1_ENTRY_SIZE - 1ULL);
0562 
0563     /* num_consoles > 0, is an indication that the consoles
0564      * are accessible
0565      */
0566     oct->num_consoles = octeon_read_device_mem32(oct,
0567         addr + offsetof(struct octeon_pci_console_desc,
0568             num_consoles));
0569     oct->console_desc_addr = addr;
0570 
0571     dev_dbg(&oct->pci_dev->dev, "Initialized consoles. %d available\n",
0572         oct->num_consoles);
0573 
0574     return ret;
0575 }
0576 
0577 static void octeon_get_uboot_version(struct octeon_device *oct)
0578 {
0579     s32 bytes_read, tries, total_read;
0580     struct octeon_console *console;
0581     u32 console_num = 0;
0582     char *uboot_ver;
0583     char *buf;
0584     char *p;
0585 
0586 #define OCTEON_UBOOT_VER_BUF_SIZE 512
0587     buf = kmalloc(OCTEON_UBOOT_VER_BUF_SIZE, GFP_KERNEL);
0588     if (!buf)
0589         return;
0590 
0591     if (octeon_console_send_cmd(oct, "setenv stdout pci\n", 50)) {
0592         kfree(buf);
0593         return;
0594     }
0595 
0596     if (octeon_console_send_cmd(oct, "version\n", 1)) {
0597         kfree(buf);
0598         return;
0599     }
0600 
0601     console = &oct->console[console_num];
0602     tries = 0;
0603     total_read = 0;
0604 
0605     do {
0606         /* Take console output regardless of whether it will
0607          * be logged
0608          */
0609         bytes_read =
0610             octeon_console_read(oct,
0611                         console_num, buf + total_read,
0612                         OCTEON_UBOOT_VER_BUF_SIZE - 1 -
0613                         total_read);
0614         if (bytes_read > 0) {
0615             buf[bytes_read] = '\0';
0616 
0617             total_read += bytes_read;
0618             if (console->waiting)
0619                 octeon_console_handle_result(oct, console_num);
0620         } else if (bytes_read < 0) {
0621             dev_err(&oct->pci_dev->dev, "Error reading console %u, ret=%d\n",
0622                 console_num, bytes_read);
0623         }
0624 
0625         tries++;
0626     } while ((bytes_read > 0) && (tries < 16));
0627 
0628     /* If nothing is read after polling the console,
0629      * output any leftovers if any
0630      */
0631     if ((total_read == 0) && (console->leftover[0])) {
0632         dev_dbg(&oct->pci_dev->dev, "%u: %s\n",
0633             console_num, console->leftover);
0634         console->leftover[0] = '\0';
0635     }
0636 
0637     buf[OCTEON_UBOOT_VER_BUF_SIZE - 1] = '\0';
0638 
0639     uboot_ver = strstr(buf, "U-Boot");
0640     if (uboot_ver) {
0641         p = strstr(uboot_ver, "mips");
0642         if (p) {
0643             p--;
0644             *p = '\0';
0645             dev_info(&oct->pci_dev->dev, "%s\n", uboot_ver);
0646         }
0647     }
0648 
0649     kfree(buf);
0650     octeon_console_send_cmd(oct, "setenv stdout serial\n", 50);
0651 }
0652 
0653 int octeon_add_console(struct octeon_device *oct, u32 console_num,
0654                char *dbg_enb)
0655 {
0656     int ret = 0;
0657     u32 delay;
0658     u64 coreaddr;
0659     struct delayed_work *work;
0660     struct octeon_console *console;
0661 
0662     if (console_num >= oct->num_consoles) {
0663         dev_err(&oct->pci_dev->dev,
0664             "trying to read from console number %d when only 0 to %d exist\n",
0665             console_num, oct->num_consoles);
0666     } else {
0667         console = &oct->console[console_num];
0668 
0669         console->waiting = 0;
0670 
0671         coreaddr = oct->console_desc_addr + console_num * 8 +
0672             offsetof(struct octeon_pci_console_desc,
0673                  console_addr_array);
0674         console->addr = octeon_read_device_mem64(oct, coreaddr);
0675         coreaddr = console->addr + offsetof(struct octeon_pci_console,
0676                             buf_size);
0677         console->buffer_size = octeon_read_device_mem32(oct, coreaddr);
0678         coreaddr = console->addr + offsetof(struct octeon_pci_console,
0679                             input_base_addr);
0680         console->input_base_addr =
0681             octeon_read_device_mem64(oct, coreaddr);
0682         coreaddr = console->addr + offsetof(struct octeon_pci_console,
0683                             output_base_addr);
0684         console->output_base_addr =
0685             octeon_read_device_mem64(oct, coreaddr);
0686         console->leftover[0] = '\0';
0687 
0688         work = &oct->console_poll_work[console_num].work;
0689 
0690         octeon_get_uboot_version(oct);
0691 
0692         INIT_DELAYED_WORK(work, check_console);
0693         oct->console_poll_work[console_num].ctxptr = (void *)oct;
0694         oct->console_poll_work[console_num].ctxul = console_num;
0695         delay = OCTEON_CONSOLE_POLL_INTERVAL_MS;
0696         schedule_delayed_work(work, msecs_to_jiffies(delay));
0697 
0698         /* an empty string means use default debug console enablement */
0699         if (dbg_enb && !dbg_enb[0])
0700             dbg_enb = "setenv pci_console_active 1";
0701         if (dbg_enb)
0702             ret = octeon_console_send_cmd(oct, dbg_enb, 2000);
0703 
0704         console->active = 1;
0705     }
0706 
0707     return ret;
0708 }
0709 
0710 /*
0711  * Removes all consoles
0712  *
0713  * @param oct         octeon device
0714  */
0715 void octeon_remove_consoles(struct octeon_device *oct)
0716 {
0717     u32 i;
0718     struct octeon_console *console;
0719 
0720     for (i = 0; i < oct->num_consoles; i++) {
0721         console = &oct->console[i];
0722 
0723         if (!console->active)
0724             continue;
0725 
0726         cancel_delayed_work_sync(&oct->console_poll_work[i].
0727                         work);
0728         console->addr = 0;
0729         console->buffer_size = 0;
0730         console->input_base_addr = 0;
0731         console->output_base_addr = 0;
0732     }
0733 
0734     oct->num_consoles = 0;
0735 }
0736 
0737 static inline int octeon_console_free_bytes(u32 buffer_size,
0738                         u32 wr_idx,
0739                         u32 rd_idx)
0740 {
0741     if (rd_idx >= buffer_size || wr_idx >= buffer_size)
0742         return -1;
0743 
0744     return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size;
0745 }
0746 
0747 static inline int octeon_console_avail_bytes(u32 buffer_size,
0748                          u32 wr_idx,
0749                          u32 rd_idx)
0750 {
0751     if (rd_idx >= buffer_size || wr_idx >= buffer_size)
0752         return -1;
0753 
0754     return buffer_size - 1 -
0755            octeon_console_free_bytes(buffer_size, wr_idx, rd_idx);
0756 }
0757 
0758 static int octeon_console_read(struct octeon_device *oct, u32 console_num,
0759                    char *buffer, u32 buf_size)
0760 {
0761     int bytes_to_read;
0762     u32 rd_idx, wr_idx;
0763     struct octeon_console *console;
0764 
0765     if (console_num >= oct->num_consoles) {
0766         dev_err(&oct->pci_dev->dev, "Attempted to read from disabled console %d\n",
0767             console_num);
0768         return 0;
0769     }
0770 
0771     console = &oct->console[console_num];
0772 
0773     /* Check to see if any data is available.
0774      * Maybe optimize this with 64-bit read.
0775      */
0776     rd_idx = octeon_read_device_mem32(oct, console->addr +
0777         offsetof(struct octeon_pci_console, output_read_index));
0778     wr_idx = octeon_read_device_mem32(oct, console->addr +
0779         offsetof(struct octeon_pci_console, output_write_index));
0780 
0781     bytes_to_read = octeon_console_avail_bytes(console->buffer_size,
0782                            wr_idx, rd_idx);
0783     if (bytes_to_read <= 0)
0784         return bytes_to_read;
0785 
0786     bytes_to_read = min_t(s32, bytes_to_read, buf_size);
0787 
0788     /* Check to see if what we want to read is not contiguous, and limit
0789      * ourselves to the contiguous block
0790      */
0791     if (rd_idx + bytes_to_read >= console->buffer_size)
0792         bytes_to_read = console->buffer_size - rd_idx;
0793 
0794     octeon_pci_read_core_mem(oct, console->output_base_addr + rd_idx,
0795                  (u8 *)buffer, bytes_to_read);
0796     octeon_write_device_mem32(oct, console->addr +
0797                   offsetof(struct octeon_pci_console,
0798                        output_read_index),
0799                   (rd_idx + bytes_to_read) %
0800                   console->buffer_size);
0801 
0802     return bytes_to_read;
0803 }
0804 
0805 #define FBUF_SIZE   (4 * 1024 * 1024)
0806 #define MAX_BOOTTIME_SIZE    80
0807 
0808 int octeon_download_firmware(struct octeon_device *oct, const u8 *data,
0809                  size_t size)
0810 {
0811     struct octeon_firmware_file_header *h;
0812     char boottime[MAX_BOOTTIME_SIZE];
0813     struct timespec64 ts;
0814     u32 crc32_result;
0815     u64 load_addr;
0816     u32 image_len;
0817     int ret = 0;
0818     u32 i, rem;
0819 
0820     if (size < sizeof(struct octeon_firmware_file_header)) {
0821         dev_err(&oct->pci_dev->dev, "Firmware file too small (%d < %d).\n",
0822             (u32)size,
0823             (u32)sizeof(struct octeon_firmware_file_header));
0824         return -EINVAL;
0825     }
0826 
0827     h = (struct octeon_firmware_file_header *)data;
0828 
0829     if (be32_to_cpu(h->magic) != LIO_NIC_MAGIC) {
0830         dev_err(&oct->pci_dev->dev, "Unrecognized firmware file.\n");
0831         return -EINVAL;
0832     }
0833 
0834     crc32_result = crc32((unsigned int)~0, data,
0835                  sizeof(struct octeon_firmware_file_header) -
0836                  sizeof(u32)) ^ ~0U;
0837     if (crc32_result != be32_to_cpu(h->crc32)) {
0838         dev_err(&oct->pci_dev->dev, "Firmware CRC mismatch (0x%08x != 0x%08x).\n",
0839             crc32_result, be32_to_cpu(h->crc32));
0840         return -EINVAL;
0841     }
0842 
0843     if (memcmp(LIQUIDIO_BASE_VERSION, h->version,
0844            strlen(LIQUIDIO_BASE_VERSION))) {
0845         dev_err(&oct->pci_dev->dev, "Unmatched firmware version. Expected %s.x, got %s.\n",
0846             LIQUIDIO_BASE_VERSION,
0847             h->version);
0848         return -EINVAL;
0849     }
0850 
0851     if (be32_to_cpu(h->num_images) > LIO_MAX_IMAGES) {
0852         dev_err(&oct->pci_dev->dev, "Too many images in firmware file (%d).\n",
0853             be32_to_cpu(h->num_images));
0854         return -EINVAL;
0855     }
0856 
0857     dev_info(&oct->pci_dev->dev, "Firmware version: %s\n", h->version);
0858     snprintf(oct->fw_info.liquidio_firmware_version, 32, "LIQUIDIO: %s",
0859          h->version);
0860 
0861     data += sizeof(struct octeon_firmware_file_header);
0862 
0863     dev_info(&oct->pci_dev->dev, "%s: Loading %d images\n", __func__,
0864          be32_to_cpu(h->num_images));
0865     /* load all images */
0866     for (i = 0; i < be32_to_cpu(h->num_images); i++) {
0867         load_addr = be64_to_cpu(h->desc[i].addr);
0868         image_len = be32_to_cpu(h->desc[i].len);
0869 
0870         dev_info(&oct->pci_dev->dev, "Loading firmware %d at %llx\n",
0871              image_len, load_addr);
0872 
0873         /* Write in 4MB chunks*/
0874         rem = image_len;
0875 
0876         while (rem) {
0877             if (rem < FBUF_SIZE)
0878                 size = rem;
0879             else
0880                 size = FBUF_SIZE;
0881 
0882             /* download the image */
0883             octeon_pci_write_core_mem(oct, load_addr, data, (u32)size);
0884 
0885             data += size;
0886             rem -= (u32)size;
0887             load_addr += size;
0888         }
0889     }
0890 
0891     /* Pass date and time information to NIC at the time of loading
0892      * firmware and periodically update the host time to NIC firmware.
0893      * This is to make NIC firmware use the same time reference as Host,
0894      * so that it is easy to correlate logs from firmware and host for
0895      * debugging.
0896      *
0897      * Octeon always uses UTC time. so timezone information is not sent.
0898      */
0899     ktime_get_real_ts64(&ts);
0900     ret = snprintf(boottime, MAX_BOOTTIME_SIZE,
0901                " time_sec=%lld time_nsec=%ld",
0902                (s64)ts.tv_sec, ts.tv_nsec);
0903     if ((sizeof(h->bootcmd) - strnlen(h->bootcmd, sizeof(h->bootcmd))) <
0904         ret) {
0905         dev_err(&oct->pci_dev->dev, "Boot command buffer too small\n");
0906         return -EINVAL;
0907     }
0908     strncat(h->bootcmd, boottime,
0909         sizeof(h->bootcmd) - strnlen(h->bootcmd, sizeof(h->bootcmd)));
0910 
0911     dev_info(&oct->pci_dev->dev, "Writing boot command: %s\n",
0912          h->bootcmd);
0913 
0914     /* Invoke the bootcmd */
0915     ret = octeon_console_send_cmd(oct, h->bootcmd, 50);
0916     if (ret)
0917         dev_info(&oct->pci_dev->dev, "Boot command send failed\n");
0918 
0919     return ret;
0920 }
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