cavium/liquidio/octeon_config.h

0001 /**********************************************************************
0002  * Author: Cavium, Inc.
0003  *
0004  * Contact: support@cavium.com
0005  *          Please include "LiquidIO" in the subject.
0006  *
0007  * Copyright (c) 2003-2016 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more details.
0017  ***********************************************************************/
0018 /*! \file  octeon_config.h
0019  *  \brief Host Driver: Configuration data structures for the host driver.
0020  */
0021
0022 #ifndef __OCTEON_CONFIG_H__
0023 #define __OCTEON_CONFIG_H__
0024
0025 /*--------------------------CONFIG VALUES------------------------*/
0026
0027 /* The following macros affect the way the driver data structures
0028  * are generated for Octeon devices.
0029  * They can be modified.
0030  */
0031
0032 /* Maximum octeon devices defined as MAX_OCTEON_NICIF to support
0033  * multiple(<= MAX_OCTEON_NICIF) Miniports
0034  */
0035 #define   MAX_OCTEON_NICIF             128
0036 #define   MAX_OCTEON_DEVICES           MAX_OCTEON_NICIF
0037 #define   MAX_OCTEON_LINKS         MAX_OCTEON_NICIF
0038 #define   MAX_OCTEON_MULTICAST_ADDR    32
0039
0040 #define   MAX_OCTEON_FILL_COUNT        8
0041
0042 /* CN6xxx IQ configuration macros */
0043 #define   CN6XXX_MAX_INPUT_QUEUES      32
0044 #define   CN6XXX_MAX_IQ_DESCRIPTORS    2048
0045 #define   CN6XXX_DB_MIN                1
0046 #define   CN6XXX_DB_MAX                8
0047 #define   CN6XXX_DB_TIMEOUT            1
0048
0049 /* CN6xxx OQ configuration macros */
0050 #define   CN6XXX_MAX_OUTPUT_QUEUES     32
0051 #define   CN6XXX_MAX_OQ_DESCRIPTORS    2048
0052 #define   CN6XXX_OQ_BUF_SIZE           1664
0053 #define   CN6XXX_OQ_PKTSPER_INTR       ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
0054                     (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
0055 #define   CN6XXX_OQ_REFIL_THRESHOLD    ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
0056                     (CN6XXX_MAX_OQ_DESCRIPTORS / 4) : 128)
0057
0058 #define   CN6XXX_OQ_INTR_PKT           64
0059 #define   CN6XXX_OQ_INTR_TIME          100
0060 #define   DEFAULT_NUM_NIC_PORTS_66XX   2
0061 #define   DEFAULT_NUM_NIC_PORTS_68XX   4
0062 #define   DEFAULT_NUM_NIC_PORTS_68XX_210NV  2
0063
0064 /* CN23xx  IQ configuration macros */
0065 #define   CN23XX_MAX_VFS_PER_PF_PASS_1_0 8
0066 #define   CN23XX_MAX_VFS_PER_PF_PASS_1_1 31
0067 #define   CN23XX_MAX_VFS_PER_PF          63
0068 #define   CN23XX_MAX_RINGS_PER_VF        8
0069
0070 #define   CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12
0071 #define   CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32
0072 #define   CN23XX_MAX_RINGS_PER_PF          64
0073 #define   CN23XX_MAX_RINGS_PER_VF          8
0074
0075 #define   CN23XX_MAX_INPUT_QUEUES   CN23XX_MAX_RINGS_PER_PF
0076 #define   CN23XX_MAX_IQ_DESCRIPTORS 2048
0077 #define   CN23XX_DEFAULT_IQ_DESCRIPTORS 512
0078 #define   CN23XX_MIN_IQ_DESCRIPTORS 128
0079 #define   CN23XX_DB_MIN                 1
0080 #define   CN23XX_DB_MAX                 8
0081 #define   CN23XX_DB_TIMEOUT             1
0082
0083 #define   CN23XX_MAX_OUTPUT_QUEUES  CN23XX_MAX_RINGS_PER_PF
0084 #define   CN23XX_MAX_OQ_DESCRIPTORS 2048
0085 #define   CN23XX_DEFAULT_OQ_DESCRIPTORS 512
0086 #define   CN23XX_MIN_OQ_DESCRIPTORS 128
0087 #define   CN23XX_OQ_BUF_SIZE        1664
0088 #define   CN23XX_OQ_PKTSPER_INTR    128
0089 /*#define CAVIUM_ONLY_CN23XX_RX_PERF*/
0090 #define   CN23XX_OQ_REFIL_THRESHOLD 16
0091
0092 #define   CN23XX_OQ_INTR_PKT        64
0093 #define   CN23XX_OQ_INTR_TIME       100
0094 #define   DEFAULT_NUM_NIC_PORTS_23XX    1
0095
0096 #define   CN23XX_CFG_IO_QUEUES      CN23XX_MAX_RINGS_PER_PF
0097 /* PEMs count */
0098 #define   CN23XX_MAX_MACS       4
0099
0100 #define   CN23XX_DEF_IQ_INTR_THRESHOLD  32
0101 #define   CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD   (64 * 1024)
0102 /* common OCTEON configuration macros */
0103 #define   CN6XXX_CFG_IO_QUEUES         32
0104 #define   OCTEON_32BYTE_INSTR          32
0105 #define   OCTEON_64BYTE_INSTR          64
0106 #define   OCTEON_MAX_BASE_IOQ          4
0107
0108 #define   OCTEON_DMA_INTR_PKT          64
0109 #define   OCTEON_DMA_INTR_TIME         1000
0110
0111 #define MAX_TXQS_PER_INTF  8
0112 #define MAX_RXQS_PER_INTF  8
0113 #define DEF_TXQS_PER_INTF  4
0114 #define DEF_RXQS_PER_INTF  4
0115
0116 #define INVALID_IOQ_NO          0xff
0117
0118 #define   DEFAULT_POW_GRP       0
0119
0120 /* Macros to get octeon config params */
0121 #define CFG_GET_IQ_CFG(cfg)                      ((cfg)->iq)
0122 #define CFG_GET_IQ_MAX_Q(cfg)                    ((cfg)->iq.max_iqs)
0123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg)        ((cfg)->iq.pending_list_size)
0124 #define CFG_GET_IQ_INSTR_TYPE(cfg)               ((cfg)->iq.instr_type)
0125 #define CFG_GET_IQ_DB_MIN(cfg)                   ((cfg)->iq.db_min)
0126 #define CFG_GET_IQ_DB_TIMEOUT(cfg)               ((cfg)->iq.db_timeout)
0127
0128 #define CFG_GET_IQ_INTR_PKT(cfg)                 ((cfg)->iq.iq_intr_pkt)
0129 #define CFG_SET_IQ_INTR_PKT(cfg, val)            (cfg)->iq.iq_intr_pkt = val
0130
0131 #define CFG_GET_OQ_MAX_Q(cfg)                    ((cfg)->oq.max_oqs)
0132 #define CFG_GET_OQ_PKTS_PER_INTR(cfg)            ((cfg)->oq.pkts_per_intr)
0133 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg)         ((cfg)->oq.refill_threshold)
0134 #define CFG_GET_OQ_INTR_PKT(cfg)                 ((cfg)->oq.oq_intr_pkt)
0135 #define CFG_GET_OQ_INTR_TIME(cfg)                ((cfg)->oq.oq_intr_time)
0136 #define CFG_SET_OQ_INTR_PKT(cfg, val)            (cfg)->oq.oq_intr_pkt = val
0137 #define CFG_SET_OQ_INTR_TIME(cfg, val)           (cfg)->oq.oq_intr_time = val
0138
0139 #define CFG_GET_DMA_INTR_PKT(cfg)                ((cfg)->dma.dma_intr_pkt)
0140 #define CFG_GET_DMA_INTR_TIME(cfg)               ((cfg)->dma.dma_intr_time)
0141 #define CFG_GET_NUM_NIC_PORTS(cfg)               ((cfg)->num_nic_ports)
0142 #define CFG_GET_NUM_DEF_TX_DESCS(cfg)            ((cfg)->num_def_tx_descs)
0143 #define CFG_GET_NUM_DEF_RX_DESCS(cfg)            ((cfg)->num_def_rx_descs)
0144 #define CFG_GET_DEF_RX_BUF_SIZE(cfg)             ((cfg)->def_rx_buf_size)
0145
0146 #define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \
0147                 ((cfg)->nic_if_cfg[idx].max_txqs)
0148 #define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \
0149                 ((cfg)->nic_if_cfg[idx].num_txqs)
0150 #define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \
0151                 ((cfg)->nic_if_cfg[idx].max_rxqs)
0152 #define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \
0153                 ((cfg)->nic_if_cfg[idx].num_rxqs)
0154 #define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \
0155                 ((cfg)->nic_if_cfg[idx].num_rx_descs)
0156 #define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \
0157                 ((cfg)->nic_if_cfg[idx].num_tx_descs)
0158 #define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \
0159                 ((cfg)->nic_if_cfg[idx].rx_buf_size)
0160 #define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \
0161                 ((cfg)->nic_if_cfg[idx].base_queue)
0162 #define CFG_GET_GMXID_NIC_IF(cfg, idx) \
0163                 ((cfg)->nic_if_cfg[idx].gmx_port_id)
0164
0165 #define CFG_GET_CTRL_Q_GRP(cfg)                  ((cfg)->misc.ctrlq_grp)
0166 #define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \
0167                 ((cfg)->misc.host_link_query_interval)
0168 #define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \
0169                 ((cfg)->misc.oct_link_query_interval)
0170 #define CFG_GET_IS_SLI_BP_ON(cfg)                ((cfg)->misc.enable_sli_oq_bp)
0171
0172 #define CFG_SET_NUM_RX_DESCS_NIC_IF(cfg, idx, value) \
0173                 ((cfg)->nic_if_cfg[idx].num_rx_descs = value)
0174 #define CFG_SET_NUM_TX_DESCS_NIC_IF(cfg, idx, value) \
0175                 ((cfg)->nic_if_cfg[idx].num_tx_descs = value)
0176
0177 /* Max IOQs per OCTEON Link */
0178 #define MAX_IOQS_PER_NICIF              64
0179
0180 enum lio_card_type {
0181     LIO_210SV = 0, /* Two port, 66xx */
0182     LIO_210NV,     /* Two port, 68xx */
0183     LIO_410NV,     /* Four port, 68xx */
0184     LIO_23XX       /* 23xx */
0185 };
0186
0187 #define LIO_210SV_NAME "210sv"
0188 #define LIO_210NV_NAME "210nv"
0189 #define LIO_410NV_NAME "410nv"
0190 #define LIO_23XX_NAME  "23xx"
0191
0192 /** Structure to define the configuration attributes for each Input queue.
0193  *  Applicable to all Octeon processors
0194  **/
0195 struct octeon_iq_config {
0196 #ifdef __BIG_ENDIAN_BITFIELD
0197     u64 reserved:16;
0198
0199     /** Tx interrupt packets. Applicable to 23xx only */
0200     u64 iq_intr_pkt:16;
0201
0202     /** Minimum ticks to wait before checking for pending instructions. */
0203     u64 db_timeout:16;
0204
0205     /** Minimum number of commands pending to be posted to Octeon
0206      *  before driver hits the Input queue doorbell.
0207      */
0208     u64 db_min:8;
0209
0210     /** Command size - 32 or 64 bytes */
0211     u64 instr_type:32;
0212
0213     /** Pending list size (usually set to the sum of the size of all Input
0214      *  queues)
0215      */
0216     u64 pending_list_size:32;
0217
0218     /* Max number of IQs available */
0219     u64 max_iqs:8;
0220 #else
0221     /* Max number of IQs available */
0222     u64 max_iqs:8;
0223
0224     /** Pending list size (usually set to the sum of the size of all Input
0225      *  queues)
0226      */
0227     u64 pending_list_size:32;
0228
0229     /** Command size - 32 or 64 bytes */
0230     u64 instr_type:32;
0231
0232     /** Minimum number of commands pending to be posted to Octeon
0233      *  before driver hits the Input queue doorbell.
0234      */
0235     u64 db_min:8;
0236
0237     /** Minimum ticks to wait before checking for pending instructions. */
0238     u64 db_timeout:16;
0239
0240     /** Tx interrupt packets. Applicable to 23xx only */
0241     u64 iq_intr_pkt:16;
0242
0243     u64 reserved:16;
0244 #endif
0245 };
0246
0247 /** Structure to define the configuration attributes for each Output queue.
0248  *  Applicable to all Octeon processors
0249  **/
0250 struct octeon_oq_config {
0251 #ifdef __BIG_ENDIAN_BITFIELD
0252     u64 reserved:16;
0253
0254     u64 pkts_per_intr:16;
0255
0256     /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
0257      *  host if atleast one packet was sent in the time interval specified
0258      *  by this field. The driver uses time interval interrupt coalescing
0259      *  by default. The time is specified in microseconds.
0260      */
0261     u64 oq_intr_time:16;
0262
0263     /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
0264      *  only if it sent as many packets as specified by this field.
0265      *  The driver
0266      *  usually does not use packet count interrupt coalescing.
0267      */
0268     u64 oq_intr_pkt:16;
0269
0270     /** The number of buffers that were consumed during packet processing by
0271      *   the driver on this Output queue before the driver attempts to
0272      *   replenish
0273      *   the descriptor ring with new buffers.
0274      */
0275     u64 refill_threshold:16;
0276
0277     /* Max number of OQs available */
0278     u64 max_oqs:8;
0279
0280 #else
0281     /* Max number of OQs available */
0282     u64 max_oqs:8;
0283
0284     /** The number of buffers that were consumed during packet processing by
0285      *   the driver on this Output queue before the driver attempts to
0286      *   replenish
0287      *   the descriptor ring with new buffers.
0288      */
0289     u64 refill_threshold:16;
0290
0291     /** Interrupt Coalescing (Packet Count). Octeon will interrupt the host
0292      *  only if it sent as many packets as specified by this field.
0293      *  The driver
0294      *  usually does not use packet count interrupt coalescing.
0295      */
0296     u64 oq_intr_pkt:16;
0297
0298     /** Interrupt Coalescing (Time Interval). Octeon will interrupt the
0299      *  host if atleast one packet was sent in the time interval specified
0300      *  by this field. The driver uses time interval interrupt coalescing
0301      *  by default.  The time is specified in microseconds.
0302      */
0303     u64 oq_intr_time:16;
0304
0305     u64 pkts_per_intr:16;
0306
0307     u64 reserved:16;
0308 #endif
0309
0310 };
0311
0312 /** This structure conatins the NIC link configuration attributes,
0313  *  common for all the OCTEON Modles.
0314  */
0315 struct octeon_nic_if_config {
0316 #ifdef __BIG_ENDIAN_BITFIELD
0317     u64 reserved:56;
0318
0319     u64 base_queue:16;
0320
0321     u64 gmx_port_id:8;
0322
0323     /* SKB size, We need not change buf size even for Jumbo frames.
0324      * Octeon can send jumbo frames in 4 consecutive descriptors,
0325      */
0326     u64 rx_buf_size:16;
0327
0328     /* Num of desc for tx rings */
0329     u64 num_tx_descs:16;
0330
0331     /* Num of desc for rx rings */
0332     u64 num_rx_descs:16;
0333
0334     /* Actual configured value. Range could be: 1...max_rxqs */
0335     u64 num_rxqs:16;
0336
0337     /* Max Rxqs: Half for each of the two ports :max_oq/2  */
0338     u64 max_rxqs:16;
0339
0340     /* Actual configured value. Range could be: 1...max_txqs */
0341     u64 num_txqs:16;
0342
0343     /* Max Txqs: Half for each of the two ports :max_iq/2 */
0344     u64 max_txqs:16;
0345 #else
0346     /* Max Txqs: Half for each of the two ports :max_iq/2 */
0347     u64 max_txqs:16;
0348
0349     /* Actual configured value. Range could be: 1...max_txqs */
0350     u64 num_txqs:16;
0351
0352     /* Max Rxqs: Half for each of the two ports :max_oq/2  */
0353     u64 max_rxqs:16;
0354
0355     /* Actual configured value. Range could be: 1...max_rxqs */
0356     u64 num_rxqs:16;
0357
0358     /* Num of desc for rx rings */
0359     u64 num_rx_descs:16;
0360
0361     /* Num of desc for tx rings */
0362     u64 num_tx_descs:16;
0363
0364     /* SKB size, We need not change buf size even for Jumbo frames.
0365      * Octeon can send jumbo frames in 4 consecutive descriptors,
0366      */
0367     u64 rx_buf_size:16;
0368
0369     u64 gmx_port_id:8;
0370
0371     u64 base_queue:16;
0372
0373     u64 reserved:56;
0374 #endif
0375
0376 };
0377
0378 /** Structure to define the configuration attributes for meta data.
0379  *  Applicable to all Octeon processors.
0380  */
0381
0382 struct octeon_misc_config {
0383 #ifdef __BIG_ENDIAN_BITFIELD
0384     /** Host link status polling period */
0385     u64 host_link_query_interval:32;
0386     /** Oct link status polling period */
0387     u64 oct_link_query_interval:32;
0388
0389     u64 enable_sli_oq_bp:1;
0390     /** Control IQ Group */
0391     u64 ctrlq_grp:4;
0392 #else
0393     /** Control IQ Group */
0394     u64 ctrlq_grp:4;
0395     /** BP for SLI OQ */
0396     u64 enable_sli_oq_bp:1;
0397     /** Host link status polling period */
0398     u64 oct_link_query_interval:32;
0399     /** Oct link status polling period */
0400     u64 host_link_query_interval:32;
0401 #endif
0402 };
0403
0404 /** Structure to define the configuration for all OCTEON processors. */
0405 struct octeon_config {
0406     u16 card_type;
0407     char *card_name;
0408
0409     /** Input Queue attributes. */
0410     struct octeon_iq_config iq;
0411
0412     /** Output Queue attributes. */
0413     struct octeon_oq_config oq;
0414
0415     /** NIC Port Configuration */
0416     struct octeon_nic_if_config nic_if_cfg[MAX_OCTEON_NICIF];
0417
0418     /** Miscellaneous attributes */
0419     struct octeon_misc_config misc;
0420
0421     int num_nic_ports;
0422
0423     int num_def_tx_descs;
0424
0425     /* Num of desc for rx rings */
0426     int num_def_rx_descs;
0427
0428     int def_rx_buf_size;
0429
0430 };
0431
0432 /* The following config values are fixed and should not be modified. */
0433
0434 #define  BAR1_INDEX_DYNAMIC_MAP          2
0435 #define  BAR1_INDEX_STATIC_MAP          15
0436 #define  OCTEON_BAR1_ENTRY_SIZE         (4 * 1024 * 1024)
0437
0438 #define  MAX_BAR1_IOREMAP_SIZE  (16 * OCTEON_BAR1_ENTRY_SIZE)
0439
0440 /* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking
0441  *                  1 process done list, 1 zombie lists(timeouted sc list)
0442  * NoResponse Lists are now maintained with each IQ. (Dec' 2007).
0443  */
0444 #define MAX_RESPONSE_LISTS           6
0445
0446 /* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the
0447  * dispatch table.
0448  */
0449 #define OPCODE_MASK_BITS             6
0450
0451 /* Mask for the 6-bit lookup hash */
0452 #define OCTEON_OPCODE_MASK           0x3f
0453
0454 /* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */
0455 #define DISPATCH_LIST_SIZE                      BIT(OPCODE_MASK_BITS)
0456
0457 /* Maximum number of Octeon Instruction (command) queues */
0458 #define MAX_OCTEON_INSTR_QUEUES(oct)        \
0459         (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_INPUT_QUEUES : \
0460                     CN6XXX_MAX_INPUT_QUEUES)
0461
0462 /* Maximum number of Octeon Instruction (command) queues */
0463 #define MAX_OCTEON_OUTPUT_QUEUES(oct)       \
0464         (OCTEON_CN23XX_PF(oct) ? CN23XX_MAX_OUTPUT_QUEUES : \
0465                     CN6XXX_MAX_OUTPUT_QUEUES)
0466
0467 #define MAX_POSSIBLE_OCTEON_INSTR_QUEUES    CN23XX_MAX_INPUT_QUEUES
0468 #define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES   CN23XX_MAX_OUTPUT_QUEUES
0469
0470 #define MAX_POSSIBLE_VFS            64
0471
0472 #endif /* __OCTEON_CONFIG_H__  */