Back to home page

OSCL-LXR
 
 

     

0001 /**********************************************************************
0002  * Author: Cavium, Inc.
0003  *
0004  * Contact: support@cavium.com
0005  *          Please include "LiquidIO" in the subject.
0006  *
0007  * Copyright (c) 2003-2016 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more details.
0017  ***********************************************************************/
0018 #include <linux/pci.h>
0019 #include <linux/if_vlan.h>
0020 #include "liquidio_common.h"
0021 #include "octeon_droq.h"
0022 #include "octeon_iq.h"
0023 #include "response_manager.h"
0024 #include "octeon_device.h"
0025 #include "octeon_nic.h"
0026 #include "octeon_main.h"
0027 #include "octeon_network.h"
0028 
0029 /* OOM task polling interval */
0030 #define LIO_OOM_POLL_INTERVAL_MS 250
0031 
0032 #define OCTNIC_MAX_SG  MAX_SKB_FRAGS
0033 
0034 /**
0035  * lio_delete_glists - Delete gather lists
0036  * @lio: per-network private data
0037  */
0038 void lio_delete_glists(struct lio *lio)
0039 {
0040     struct octnic_gather *g;
0041     int i;
0042 
0043     kfree(lio->glist_lock);
0044     lio->glist_lock = NULL;
0045 
0046     if (!lio->glist)
0047         return;
0048 
0049     for (i = 0; i < lio->oct_dev->num_iqs; i++) {
0050         do {
0051             g = (struct octnic_gather *)
0052                 lio_list_delete_head(&lio->glist[i]);
0053             kfree(g);
0054         } while (g);
0055 
0056         if (lio->glists_virt_base && lio->glists_virt_base[i] &&
0057             lio->glists_dma_base && lio->glists_dma_base[i]) {
0058             lio_dma_free(lio->oct_dev,
0059                      lio->glist_entry_size * lio->tx_qsize,
0060                      lio->glists_virt_base[i],
0061                      lio->glists_dma_base[i]);
0062         }
0063     }
0064 
0065     kfree(lio->glists_virt_base);
0066     lio->glists_virt_base = NULL;
0067 
0068     kfree(lio->glists_dma_base);
0069     lio->glists_dma_base = NULL;
0070 
0071     kfree(lio->glist);
0072     lio->glist = NULL;
0073 }
0074 
0075 /**
0076  * lio_setup_glists - Setup gather lists
0077  * @oct: octeon_device
0078  * @lio: per-network private data
0079  * @num_iqs: count of iqs to allocate
0080  */
0081 int lio_setup_glists(struct octeon_device *oct, struct lio *lio, int num_iqs)
0082 {
0083     struct octnic_gather *g;
0084     int i, j;
0085 
0086     lio->glist_lock =
0087         kcalloc(num_iqs, sizeof(*lio->glist_lock), GFP_KERNEL);
0088     if (!lio->glist_lock)
0089         return -ENOMEM;
0090 
0091     lio->glist =
0092         kcalloc(num_iqs, sizeof(*lio->glist), GFP_KERNEL);
0093     if (!lio->glist) {
0094         kfree(lio->glist_lock);
0095         lio->glist_lock = NULL;
0096         return -ENOMEM;
0097     }
0098 
0099     lio->glist_entry_size =
0100         ROUNDUP8((ROUNDUP4(OCTNIC_MAX_SG) >> 2) * OCT_SG_ENTRY_SIZE);
0101 
0102     /* allocate memory to store virtual and dma base address of
0103      * per glist consistent memory
0104      */
0105     lio->glists_virt_base = kcalloc(num_iqs, sizeof(*lio->glists_virt_base),
0106                     GFP_KERNEL);
0107     lio->glists_dma_base = kcalloc(num_iqs, sizeof(*lio->glists_dma_base),
0108                        GFP_KERNEL);
0109 
0110     if (!lio->glists_virt_base || !lio->glists_dma_base) {
0111         lio_delete_glists(lio);
0112         return -ENOMEM;
0113     }
0114 
0115     for (i = 0; i < num_iqs; i++) {
0116         int numa_node = dev_to_node(&oct->pci_dev->dev);
0117 
0118         spin_lock_init(&lio->glist_lock[i]);
0119 
0120         INIT_LIST_HEAD(&lio->glist[i]);
0121 
0122         lio->glists_virt_base[i] =
0123             lio_dma_alloc(oct,
0124                       lio->glist_entry_size * lio->tx_qsize,
0125                       &lio->glists_dma_base[i]);
0126 
0127         if (!lio->glists_virt_base[i]) {
0128             lio_delete_glists(lio);
0129             return -ENOMEM;
0130         }
0131 
0132         for (j = 0; j < lio->tx_qsize; j++) {
0133             g = kzalloc_node(sizeof(*g), GFP_KERNEL,
0134                      numa_node);
0135             if (!g)
0136                 g = kzalloc(sizeof(*g), GFP_KERNEL);
0137             if (!g)
0138                 break;
0139 
0140             g->sg = lio->glists_virt_base[i] +
0141                 (j * lio->glist_entry_size);
0142 
0143             g->sg_dma_ptr = lio->glists_dma_base[i] +
0144                     (j * lio->glist_entry_size);
0145 
0146             list_add_tail(&g->list, &lio->glist[i]);
0147         }
0148 
0149         if (j != lio->tx_qsize) {
0150             lio_delete_glists(lio);
0151             return -ENOMEM;
0152         }
0153     }
0154 
0155     return 0;
0156 }
0157 
0158 int liquidio_set_feature(struct net_device *netdev, int cmd, u16 param1)
0159 {
0160     struct lio *lio = GET_LIO(netdev);
0161     struct octeon_device *oct = lio->oct_dev;
0162     struct octnic_ctrl_pkt nctrl;
0163     int ret = 0;
0164 
0165     memset(&nctrl, 0, sizeof(struct octnic_ctrl_pkt));
0166 
0167     nctrl.ncmd.u64 = 0;
0168     nctrl.ncmd.s.cmd = cmd;
0169     nctrl.ncmd.s.param1 = param1;
0170     nctrl.iq_no = lio->linfo.txpciq[0].s.q_no;
0171     nctrl.netpndev = (u64)netdev;
0172     nctrl.cb_fn = liquidio_link_ctrl_cmd_completion;
0173 
0174     ret = octnet_send_nic_ctrl_pkt(lio->oct_dev, &nctrl);
0175     if (ret) {
0176         dev_err(&oct->pci_dev->dev, "Feature change failed in core (ret: 0x%x)\n",
0177             ret);
0178         if (ret > 0)
0179             ret = -EIO;
0180     }
0181     return ret;
0182 }
0183 
0184 void octeon_report_tx_completion_to_bql(void *txq, unsigned int pkts_compl,
0185                     unsigned int bytes_compl)
0186 {
0187     struct netdev_queue *netdev_queue = txq;
0188 
0189     netdev_tx_completed_queue(netdev_queue, pkts_compl, bytes_compl);
0190 }
0191 
0192 void octeon_update_tx_completion_counters(void *buf, int reqtype,
0193                       unsigned int *pkts_compl,
0194                       unsigned int *bytes_compl)
0195 {
0196     struct octnet_buf_free_info *finfo;
0197     struct sk_buff *skb = NULL;
0198     struct octeon_soft_command *sc;
0199 
0200     switch (reqtype) {
0201     case REQTYPE_NORESP_NET:
0202     case REQTYPE_NORESP_NET_SG:
0203         finfo = buf;
0204         skb = finfo->skb;
0205         break;
0206 
0207     case REQTYPE_RESP_NET_SG:
0208     case REQTYPE_RESP_NET:
0209         sc = buf;
0210         skb = sc->callback_arg;
0211         break;
0212 
0213     default:
0214         return;
0215     }
0216 
0217     (*pkts_compl)++;
0218     *bytes_compl += skb->len;
0219 }
0220 
0221 int octeon_report_sent_bytes_to_bql(void *buf, int reqtype)
0222 {
0223     struct octnet_buf_free_info *finfo;
0224     struct sk_buff *skb;
0225     struct octeon_soft_command *sc;
0226     struct netdev_queue *txq;
0227 
0228     switch (reqtype) {
0229     case REQTYPE_NORESP_NET:
0230     case REQTYPE_NORESP_NET_SG:
0231         finfo = buf;
0232         skb = finfo->skb;
0233         break;
0234 
0235     case REQTYPE_RESP_NET_SG:
0236     case REQTYPE_RESP_NET:
0237         sc = buf;
0238         skb = sc->callback_arg;
0239         break;
0240 
0241     default:
0242         return 0;
0243     }
0244 
0245     txq = netdev_get_tx_queue(skb->dev, skb_get_queue_mapping(skb));
0246     netdev_tx_sent_queue(txq, skb->len);
0247 
0248     return netif_xmit_stopped(txq);
0249 }
0250 
0251 void liquidio_link_ctrl_cmd_completion(void *nctrl_ptr)
0252 {
0253     struct octnic_ctrl_pkt *nctrl = (struct octnic_ctrl_pkt *)nctrl_ptr;
0254     struct net_device *netdev = (struct net_device *)nctrl->netpndev;
0255     struct lio *lio = GET_LIO(netdev);
0256     struct octeon_device *oct = lio->oct_dev;
0257     u8 *mac;
0258 
0259     if (nctrl->sc_status)
0260         return;
0261 
0262     switch (nctrl->ncmd.s.cmd) {
0263     case OCTNET_CMD_CHANGE_DEVFLAGS:
0264     case OCTNET_CMD_SET_MULTI_LIST:
0265     case OCTNET_CMD_SET_UC_LIST:
0266         break;
0267 
0268     case OCTNET_CMD_CHANGE_MACADDR:
0269         mac = ((u8 *)&nctrl->udd[0]) + 2;
0270         if (nctrl->ncmd.s.param1) {
0271             /* vfidx is 0 based, but vf_num (param1) is 1 based */
0272             int vfidx = nctrl->ncmd.s.param1 - 1;
0273             bool mac_is_admin_assigned = nctrl->ncmd.s.param2;
0274 
0275             if (mac_is_admin_assigned)
0276                 netif_info(lio, probe, lio->netdev,
0277                        "MAC Address %pM is configured for VF %d\n",
0278                        mac, vfidx);
0279         } else {
0280             netif_info(lio, probe, lio->netdev,
0281                    " MACAddr changed to %pM\n",
0282                    mac);
0283         }
0284         break;
0285 
0286     case OCTNET_CMD_GPIO_ACCESS:
0287         netif_info(lio, probe, lio->netdev, "LED Flashing visual identification\n");
0288 
0289         break;
0290 
0291     case OCTNET_CMD_ID_ACTIVE:
0292         netif_info(lio, probe, lio->netdev, "LED Flashing visual identification\n");
0293 
0294         break;
0295 
0296     case OCTNET_CMD_LRO_ENABLE:
0297         dev_info(&oct->pci_dev->dev, "%s LRO Enabled\n", netdev->name);
0298         break;
0299 
0300     case OCTNET_CMD_LRO_DISABLE:
0301         dev_info(&oct->pci_dev->dev, "%s LRO Disabled\n",
0302              netdev->name);
0303         break;
0304 
0305     case OCTNET_CMD_VERBOSE_ENABLE:
0306         dev_info(&oct->pci_dev->dev, "%s Firmware debug enabled\n",
0307              netdev->name);
0308         break;
0309 
0310     case OCTNET_CMD_VERBOSE_DISABLE:
0311         dev_info(&oct->pci_dev->dev, "%s Firmware debug disabled\n",
0312              netdev->name);
0313         break;
0314 
0315     case OCTNET_CMD_VLAN_FILTER_CTL:
0316         if (nctrl->ncmd.s.param1)
0317             dev_info(&oct->pci_dev->dev,
0318                  "%s VLAN filter enabled\n", netdev->name);
0319         else
0320             dev_info(&oct->pci_dev->dev,
0321                  "%s VLAN filter disabled\n", netdev->name);
0322         break;
0323 
0324     case OCTNET_CMD_ADD_VLAN_FILTER:
0325         dev_info(&oct->pci_dev->dev, "%s VLAN filter %d added\n",
0326              netdev->name, nctrl->ncmd.s.param1);
0327         break;
0328 
0329     case OCTNET_CMD_DEL_VLAN_FILTER:
0330         dev_info(&oct->pci_dev->dev, "%s VLAN filter %d removed\n",
0331              netdev->name, nctrl->ncmd.s.param1);
0332         break;
0333 
0334     case OCTNET_CMD_SET_SETTINGS:
0335         dev_info(&oct->pci_dev->dev, "%s settings changed\n",
0336              netdev->name);
0337 
0338         break;
0339 
0340     /* Case to handle "OCTNET_CMD_TNL_RX_CSUM_CTL"
0341      * Command passed by NIC driver
0342      */
0343     case OCTNET_CMD_TNL_RX_CSUM_CTL:
0344         if (nctrl->ncmd.s.param1 == OCTNET_CMD_RXCSUM_ENABLE) {
0345             netif_info(lio, probe, lio->netdev,
0346                    "RX Checksum Offload Enabled\n");
0347         } else if (nctrl->ncmd.s.param1 ==
0348                OCTNET_CMD_RXCSUM_DISABLE) {
0349             netif_info(lio, probe, lio->netdev,
0350                    "RX Checksum Offload Disabled\n");
0351         }
0352         break;
0353 
0354         /* Case to handle "OCTNET_CMD_TNL_TX_CSUM_CTL"
0355          * Command passed by NIC driver
0356          */
0357     case OCTNET_CMD_TNL_TX_CSUM_CTL:
0358         if (nctrl->ncmd.s.param1 == OCTNET_CMD_TXCSUM_ENABLE) {
0359             netif_info(lio, probe, lio->netdev,
0360                    "TX Checksum Offload Enabled\n");
0361         } else if (nctrl->ncmd.s.param1 ==
0362                OCTNET_CMD_TXCSUM_DISABLE) {
0363             netif_info(lio, probe, lio->netdev,
0364                    "TX Checksum Offload Disabled\n");
0365         }
0366         break;
0367 
0368         /* Case to handle "OCTNET_CMD_VXLAN_PORT_CONFIG"
0369          * Command passed by NIC driver
0370          */
0371     case OCTNET_CMD_VXLAN_PORT_CONFIG:
0372         if (nctrl->ncmd.s.more == OCTNET_CMD_VXLAN_PORT_ADD) {
0373             netif_info(lio, probe, lio->netdev,
0374                    "VxLAN Destination UDP PORT:%d ADDED\n",
0375                    nctrl->ncmd.s.param1);
0376         } else if (nctrl->ncmd.s.more ==
0377                OCTNET_CMD_VXLAN_PORT_DEL) {
0378             netif_info(lio, probe, lio->netdev,
0379                    "VxLAN Destination UDP PORT:%d DELETED\n",
0380                    nctrl->ncmd.s.param1);
0381         }
0382         break;
0383 
0384     case OCTNET_CMD_SET_FLOW_CTL:
0385         netif_info(lio, probe, lio->netdev, "Set RX/TX flow control parameters\n");
0386         break;
0387 
0388     case OCTNET_CMD_QUEUE_COUNT_CTL:
0389         netif_info(lio, probe, lio->netdev, "Queue count updated to %d\n",
0390                nctrl->ncmd.s.param1);
0391         break;
0392 
0393     default:
0394         dev_err(&oct->pci_dev->dev, "%s Unknown cmd %d\n", __func__,
0395             nctrl->ncmd.s.cmd);
0396     }
0397 }
0398 
0399 void octeon_pf_changed_vf_macaddr(struct octeon_device *oct, u8 *mac)
0400 {
0401     bool macaddr_changed = false;
0402     struct net_device *netdev;
0403     struct lio *lio;
0404 
0405     rtnl_lock();
0406 
0407     netdev = oct->props[0].netdev;
0408     lio = GET_LIO(netdev);
0409 
0410     lio->linfo.macaddr_is_admin_asgnd = true;
0411 
0412     if (!ether_addr_equal(netdev->dev_addr, mac)) {
0413         macaddr_changed = true;
0414         eth_hw_addr_set(netdev, mac);
0415         ether_addr_copy(((u8 *)&lio->linfo.hw_addr) + 2, mac);
0416         call_netdevice_notifiers(NETDEV_CHANGEADDR, netdev);
0417     }
0418 
0419     rtnl_unlock();
0420 
0421     if (macaddr_changed)
0422         dev_info(&oct->pci_dev->dev,
0423              "PF changed VF's MAC address to %pM\n", mac);
0424 
0425     /* no need to notify the firmware of the macaddr change because
0426      * the PF did that already
0427      */
0428 }
0429 
0430 void octeon_schedule_rxq_oom_work(struct octeon_device *oct,
0431                   struct octeon_droq *droq)
0432 {
0433     struct net_device *netdev = oct->props[0].netdev;
0434     struct lio *lio = GET_LIO(netdev);
0435     struct cavium_wq *wq = &lio->rxq_status_wq[droq->q_no];
0436 
0437     queue_delayed_work(wq->wq, &wq->wk.work,
0438                msecs_to_jiffies(LIO_OOM_POLL_INTERVAL_MS));
0439 }
0440 
0441 static void octnet_poll_check_rxq_oom_status(struct work_struct *work)
0442 {
0443     struct cavium_wk *wk = (struct cavium_wk *)work;
0444     struct lio *lio = (struct lio *)wk->ctxptr;
0445     struct octeon_device *oct = lio->oct_dev;
0446     int q_no = wk->ctxul;
0447     struct octeon_droq *droq = oct->droq[q_no];
0448 
0449     if (!ifstate_check(lio, LIO_IFSTATE_RUNNING) || !droq)
0450         return;
0451 
0452     if (octeon_retry_droq_refill(droq))
0453         octeon_schedule_rxq_oom_work(oct, droq);
0454 }
0455 
0456 int setup_rx_oom_poll_fn(struct net_device *netdev)
0457 {
0458     struct lio *lio = GET_LIO(netdev);
0459     struct octeon_device *oct = lio->oct_dev;
0460     struct cavium_wq *wq;
0461     int q, q_no;
0462 
0463     for (q = 0; q < oct->num_oqs; q++) {
0464         q_no = lio->linfo.rxpciq[q].s.q_no;
0465         wq = &lio->rxq_status_wq[q_no];
0466         wq->wq = alloc_workqueue("rxq-oom-status",
0467                      WQ_MEM_RECLAIM, 0);
0468         if (!wq->wq) {
0469             dev_err(&oct->pci_dev->dev, "unable to create cavium rxq oom status wq\n");
0470             return -ENOMEM;
0471         }
0472 
0473         INIT_DELAYED_WORK(&wq->wk.work,
0474                   octnet_poll_check_rxq_oom_status);
0475         wq->wk.ctxptr = lio;
0476         wq->wk.ctxul = q_no;
0477     }
0478 
0479     return 0;
0480 }
0481 
0482 void cleanup_rx_oom_poll_fn(struct net_device *netdev)
0483 {
0484     struct lio *lio = GET_LIO(netdev);
0485     struct octeon_device *oct = lio->oct_dev;
0486     struct cavium_wq *wq;
0487     int q_no;
0488 
0489     for (q_no = 0; q_no < oct->num_oqs; q_no++) {
0490         wq = &lio->rxq_status_wq[q_no];
0491         if (wq->wq) {
0492             cancel_delayed_work_sync(&wq->wk.work);
0493             destroy_workqueue(wq->wq);
0494             wq->wq = NULL;
0495         }
0496     }
0497 }
0498 
0499 /* Runs in interrupt context. */
0500 static void lio_update_txq_status(struct octeon_device *oct, int iq_num)
0501 {
0502     struct octeon_instr_queue *iq = oct->instr_queue[iq_num];
0503     struct net_device *netdev;
0504     struct lio *lio;
0505 
0506     netdev = oct->props[iq->ifidx].netdev;
0507 
0508     /* This is needed because the first IQ does not have
0509      * a netdev associated with it.
0510      */
0511     if (!netdev)
0512         return;
0513 
0514     lio = GET_LIO(netdev);
0515     if (__netif_subqueue_stopped(netdev, iq->q_index) &&
0516         lio->linfo.link.s.link_up &&
0517         (!octnet_iq_is_full(oct, iq_num))) {
0518         netif_wake_subqueue(netdev, iq->q_index);
0519         INCR_INSTRQUEUE_PKT_COUNT(lio->oct_dev, iq_num,
0520                       tx_restart, 1);
0521     }
0522 }
0523 
0524 /**
0525  * octeon_setup_droq - Setup output queue
0526  * @oct: octeon device
0527  * @q_no: which queue
0528  * @num_descs: how many descriptors
0529  * @desc_size: size of each descriptor
0530  * @app_ctx: application context
0531  */
0532 static int octeon_setup_droq(struct octeon_device *oct, int q_no, int num_descs,
0533                  int desc_size, void *app_ctx)
0534 {
0535     int ret_val;
0536 
0537     dev_dbg(&oct->pci_dev->dev, "Creating Droq: %d\n", q_no);
0538     /* droq creation and local register settings. */
0539     ret_val = octeon_create_droq(oct, q_no, num_descs, desc_size, app_ctx);
0540     if (ret_val < 0)
0541         return ret_val;
0542 
0543     if (ret_val == 1) {
0544         dev_dbg(&oct->pci_dev->dev, "Using default droq %d\n", q_no);
0545         return 0;
0546     }
0547 
0548     /* Enable the droq queues */
0549     octeon_set_droq_pkt_op(oct, q_no, 1);
0550 
0551     /* Send Credit for Octeon Output queues. Credits are always
0552      * sent after the output queue is enabled.
0553      */
0554     writel(oct->droq[q_no]->max_count, oct->droq[q_no]->pkts_credit_reg);
0555 
0556     return ret_val;
0557 }
0558 
0559 /**
0560  * liquidio_push_packet - Routine to push packets arriving on Octeon interface upto network layer.
0561  * @octeon_id:octeon device id.
0562  * @skbuff:   skbuff struct to be passed to network layer.
0563  * @len:      size of total data received.
0564  * @rh:       Control header associated with the packet
0565  * @param:    additional control data with the packet
0566  * @arg:      farg registered in droq_ops
0567  */
0568 static void
0569 liquidio_push_packet(u32 __maybe_unused octeon_id,
0570              void *skbuff,
0571              u32 len,
0572              union octeon_rh *rh,
0573              void *param,
0574              void *arg)
0575 {
0576     struct net_device *netdev = (struct net_device *)arg;
0577     struct octeon_droq *droq =
0578         container_of(param, struct octeon_droq, napi);
0579     struct sk_buff *skb = (struct sk_buff *)skbuff;
0580     struct skb_shared_hwtstamps *shhwtstamps;
0581     struct napi_struct *napi = param;
0582     u16 vtag = 0;
0583     u32 r_dh_off;
0584     u64 ns;
0585 
0586     if (netdev) {
0587         struct lio *lio = GET_LIO(netdev);
0588         struct octeon_device *oct = lio->oct_dev;
0589 
0590         /* Do not proceed if the interface is not in RUNNING state. */
0591         if (!ifstate_check(lio, LIO_IFSTATE_RUNNING)) {
0592             recv_buffer_free(skb);
0593             droq->stats.rx_dropped++;
0594             return;
0595         }
0596 
0597         skb->dev = netdev;
0598 
0599         skb_record_rx_queue(skb, droq->q_no);
0600         if (likely(len > MIN_SKB_SIZE)) {
0601             struct octeon_skb_page_info *pg_info;
0602             unsigned char *va;
0603 
0604             pg_info = ((struct octeon_skb_page_info *)(skb->cb));
0605             if (pg_info->page) {
0606                 /* For Paged allocation use the frags */
0607                 va = page_address(pg_info->page) +
0608                     pg_info->page_offset;
0609                 memcpy(skb->data, va, MIN_SKB_SIZE);
0610                 skb_put(skb, MIN_SKB_SIZE);
0611                 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
0612                         pg_info->page,
0613                         pg_info->page_offset +
0614                         MIN_SKB_SIZE,
0615                         len - MIN_SKB_SIZE,
0616                         LIO_RXBUFFER_SZ);
0617             }
0618         } else {
0619             struct octeon_skb_page_info *pg_info =
0620                 ((struct octeon_skb_page_info *)(skb->cb));
0621             skb_copy_to_linear_data(skb, page_address(pg_info->page)
0622                         + pg_info->page_offset, len);
0623             skb_put(skb, len);
0624             put_page(pg_info->page);
0625         }
0626 
0627         r_dh_off = (rh->r_dh.len - 1) * BYTES_PER_DHLEN_UNIT;
0628 
0629         if (oct->ptp_enable) {
0630             if (rh->r_dh.has_hwtstamp) {
0631                 /* timestamp is included from the hardware at
0632                  * the beginning of the packet.
0633                  */
0634                 if (ifstate_check
0635                     (lio,
0636                      LIO_IFSTATE_RX_TIMESTAMP_ENABLED)) {
0637                     /* Nanoseconds are in the first 64-bits
0638                      * of the packet.
0639                      */
0640                     memcpy(&ns, (skb->data + r_dh_off),
0641                            sizeof(ns));
0642                     r_dh_off -= BYTES_PER_DHLEN_UNIT;
0643                     shhwtstamps = skb_hwtstamps(skb);
0644                     shhwtstamps->hwtstamp =
0645                         ns_to_ktime(ns +
0646                                 lio->ptp_adjust);
0647                 }
0648             }
0649         }
0650 
0651         if (rh->r_dh.has_hash) {
0652             __be32 *hash_be = (__be32 *)(skb->data + r_dh_off);
0653             u32 hash = be32_to_cpu(*hash_be);
0654 
0655             skb_set_hash(skb, hash, PKT_HASH_TYPE_L4);
0656             r_dh_off -= BYTES_PER_DHLEN_UNIT;
0657         }
0658 
0659         skb_pull(skb, rh->r_dh.len * BYTES_PER_DHLEN_UNIT);
0660         skb->protocol = eth_type_trans(skb, skb->dev);
0661 
0662         if ((netdev->features & NETIF_F_RXCSUM) &&
0663             (((rh->r_dh.encap_on) &&
0664               (rh->r_dh.csum_verified & CNNIC_TUN_CSUM_VERIFIED)) ||
0665              (!(rh->r_dh.encap_on) &&
0666               ((rh->r_dh.csum_verified & CNNIC_CSUM_VERIFIED) ==
0667             CNNIC_CSUM_VERIFIED))))
0668             /* checksum has already been verified */
0669             skb->ip_summed = CHECKSUM_UNNECESSARY;
0670         else
0671             skb->ip_summed = CHECKSUM_NONE;
0672 
0673         /* Setting Encapsulation field on basis of status received
0674          * from the firmware
0675          */
0676         if (rh->r_dh.encap_on) {
0677             skb->encapsulation = 1;
0678             skb->csum_level = 1;
0679             droq->stats.rx_vxlan++;
0680         }
0681 
0682         /* inbound VLAN tag */
0683         if ((netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
0684             rh->r_dh.vlan) {
0685             u16 priority = rh->r_dh.priority;
0686             u16 vid = rh->r_dh.vlan;
0687 
0688             vtag = (priority << VLAN_PRIO_SHIFT) | vid;
0689             __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vtag);
0690         }
0691 
0692         napi_gro_receive(napi, skb);
0693 
0694         droq->stats.rx_bytes_received += len -
0695             rh->r_dh.len * BYTES_PER_DHLEN_UNIT;
0696         droq->stats.rx_pkts_received++;
0697     } else {
0698         recv_buffer_free(skb);
0699     }
0700 }
0701 
0702 /**
0703  * napi_schedule_wrapper - wrapper for calling napi_schedule
0704  * @param: parameters to pass to napi_schedule
0705  *
0706  * Used when scheduling on different CPUs
0707  */
0708 static void napi_schedule_wrapper(void *param)
0709 {
0710     struct napi_struct *napi = param;
0711 
0712     napi_schedule(napi);
0713 }
0714 
0715 /**
0716  * liquidio_napi_drv_callback - callback when receive interrupt occurs and we are in NAPI mode
0717  * @arg: pointer to octeon output queue
0718  */
0719 static void liquidio_napi_drv_callback(void *arg)
0720 {
0721     struct octeon_device *oct;
0722     struct octeon_droq *droq = arg;
0723     int this_cpu = smp_processor_id();
0724 
0725     oct = droq->oct_dev;
0726 
0727     if (OCTEON_CN23XX_PF(oct) || OCTEON_CN23XX_VF(oct) ||
0728         droq->cpu_id == this_cpu) {
0729         napi_schedule_irqoff(&droq->napi);
0730     } else {
0731         INIT_CSD(&droq->csd, napi_schedule_wrapper, &droq->napi);
0732         smp_call_function_single_async(droq->cpu_id, &droq->csd);
0733     }
0734 }
0735 
0736 /**
0737  * liquidio_napi_poll - Entry point for NAPI polling
0738  * @napi: NAPI structure
0739  * @budget: maximum number of items to process
0740  */
0741 static int liquidio_napi_poll(struct napi_struct *napi, int budget)
0742 {
0743     struct octeon_instr_queue *iq;
0744     struct octeon_device *oct;
0745     struct octeon_droq *droq;
0746     int tx_done = 0, iq_no;
0747     int work_done;
0748 
0749     droq = container_of(napi, struct octeon_droq, napi);
0750     oct = droq->oct_dev;
0751     iq_no = droq->q_no;
0752 
0753     /* Handle Droq descriptors */
0754     work_done = octeon_droq_process_poll_pkts(oct, droq, budget);
0755 
0756     /* Flush the instruction queue */
0757     iq = oct->instr_queue[iq_no];
0758     if (iq) {
0759         /* TODO: move this check to inside octeon_flush_iq,
0760          * once check_db_timeout is removed
0761          */
0762         if (atomic_read(&iq->instr_pending))
0763             /* Process iq buffers with in the budget limits */
0764             tx_done = octeon_flush_iq(oct, iq, budget);
0765         else
0766             tx_done = 1;
0767         /* Update iq read-index rather than waiting for next interrupt.
0768          * Return back if tx_done is false.
0769          */
0770         /* sub-queue status update */
0771         lio_update_txq_status(oct, iq_no);
0772     } else {
0773         dev_err(&oct->pci_dev->dev, "%s:  iq (%d) num invalid\n",
0774             __func__, iq_no);
0775     }
0776 
0777 #define MAX_REG_CNT  2000000U
0778     /* force enable interrupt if reg cnts are high to avoid wraparound */
0779     if ((work_done < budget && tx_done) ||
0780         (iq && iq->pkt_in_done >= MAX_REG_CNT) ||
0781         (droq->pkt_count >= MAX_REG_CNT)) {
0782         napi_complete_done(napi, work_done);
0783 
0784         octeon_enable_irq(droq->oct_dev, droq->q_no);
0785         return 0;
0786     }
0787 
0788     return (!tx_done) ? (budget) : (work_done);
0789 }
0790 
0791 /**
0792  * liquidio_setup_io_queues - Setup input and output queues
0793  * @octeon_dev: octeon device
0794  * @ifidx: Interface index
0795  * @num_iqs: input io queue count
0796  * @num_oqs: output io queue count
0797  *
0798  * Note: Queues are with respect to the octeon device. Thus
0799  * an input queue is for egress packets, and output queues
0800  * are for ingress packets.
0801  */
0802 int liquidio_setup_io_queues(struct octeon_device *octeon_dev, int ifidx,
0803                  u32 num_iqs, u32 num_oqs)
0804 {
0805     struct octeon_droq_ops droq_ops;
0806     struct net_device *netdev;
0807     struct octeon_droq *droq;
0808     struct napi_struct *napi;
0809     int cpu_id_modulus;
0810     int num_tx_descs;
0811     struct lio *lio;
0812     int retval = 0;
0813     int q, q_no;
0814     int cpu_id;
0815 
0816     netdev = octeon_dev->props[ifidx].netdev;
0817 
0818     lio = GET_LIO(netdev);
0819 
0820     memset(&droq_ops, 0, sizeof(struct octeon_droq_ops));
0821 
0822     droq_ops.fptr = liquidio_push_packet;
0823     droq_ops.farg = netdev;
0824 
0825     droq_ops.poll_mode = 1;
0826     droq_ops.napi_fn = liquidio_napi_drv_callback;
0827     cpu_id = 0;
0828     cpu_id_modulus = num_present_cpus();
0829 
0830     /* set up DROQs. */
0831     for (q = 0; q < num_oqs; q++) {
0832         q_no = lio->linfo.rxpciq[q].s.q_no;
0833         dev_dbg(&octeon_dev->pci_dev->dev,
0834             "%s index:%d linfo.rxpciq.s.q_no:%d\n",
0835             __func__, q, q_no);
0836         retval = octeon_setup_droq(
0837             octeon_dev, q_no,
0838             CFG_GET_NUM_RX_DESCS_NIC_IF(octeon_get_conf(octeon_dev),
0839                         lio->ifidx),
0840             CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(octeon_get_conf(octeon_dev),
0841                            lio->ifidx),
0842             NULL);
0843         if (retval) {
0844             dev_err(&octeon_dev->pci_dev->dev,
0845                 "%s : Runtime DROQ(RxQ) creation failed.\n",
0846                 __func__);
0847             return 1;
0848         }
0849 
0850         droq = octeon_dev->droq[q_no];
0851         napi = &droq->napi;
0852         dev_dbg(&octeon_dev->pci_dev->dev, "netif_napi_add netdev:%llx oct:%llx\n",
0853             (u64)netdev, (u64)octeon_dev);
0854         netif_napi_add(netdev, napi, liquidio_napi_poll, 64);
0855 
0856         /* designate a CPU for this droq */
0857         droq->cpu_id = cpu_id;
0858         cpu_id++;
0859         if (cpu_id >= cpu_id_modulus)
0860             cpu_id = 0;
0861 
0862         octeon_register_droq_ops(octeon_dev, q_no, &droq_ops);
0863     }
0864 
0865     if (OCTEON_CN23XX_PF(octeon_dev) || OCTEON_CN23XX_VF(octeon_dev)) {
0866         /* 23XX PF/VF can send/recv control messages (via the first
0867          * PF/VF-owned droq) from the firmware even if the ethX
0868          * interface is down, so that's why poll_mode must be off
0869          * for the first droq.
0870          */
0871         octeon_dev->droq[0]->ops.poll_mode = 0;
0872     }
0873 
0874     /* set up IQs. */
0875     for (q = 0; q < num_iqs; q++) {
0876         num_tx_descs = CFG_GET_NUM_TX_DESCS_NIC_IF(
0877             octeon_get_conf(octeon_dev), lio->ifidx);
0878         retval = octeon_setup_iq(octeon_dev, ifidx, q,
0879                      lio->linfo.txpciq[q], num_tx_descs,
0880                      netdev_get_tx_queue(netdev, q));
0881         if (retval) {
0882             dev_err(&octeon_dev->pci_dev->dev,
0883                 " %s : Runtime IQ(TxQ) creation failed.\n",
0884                 __func__);
0885             return 1;
0886         }
0887 
0888         /* XPS */
0889         if (!OCTEON_CN23XX_VF(octeon_dev) && octeon_dev->msix_on &&
0890             octeon_dev->ioq_vector) {
0891             struct octeon_ioq_vector    *ioq_vector;
0892 
0893             ioq_vector = &octeon_dev->ioq_vector[q];
0894             netif_set_xps_queue(netdev,
0895                         &ioq_vector->affinity_mask,
0896                         ioq_vector->iq_index);
0897         }
0898     }
0899 
0900     return 0;
0901 }
0902 
0903 static
0904 int liquidio_schedule_msix_droq_pkt_handler(struct octeon_droq *droq, u64 ret)
0905 {
0906     struct octeon_device *oct = droq->oct_dev;
0907     struct octeon_device_priv *oct_priv =
0908         (struct octeon_device_priv *)oct->priv;
0909 
0910     if (droq->ops.poll_mode) {
0911         droq->ops.napi_fn(droq);
0912     } else {
0913         if (ret & MSIX_PO_INT) {
0914             if (OCTEON_CN23XX_VF(oct))
0915                 dev_err(&oct->pci_dev->dev,
0916                     "should not come here should not get rx when poll mode = 0 for vf\n");
0917             tasklet_schedule(&oct_priv->droq_tasklet);
0918             return 1;
0919         }
0920         /* this will be flushed periodically by check iq db */
0921         if (ret & MSIX_PI_INT)
0922             return 0;
0923     }
0924 
0925     return 0;
0926 }
0927 
0928 irqreturn_t
0929 liquidio_msix_intr_handler(int __maybe_unused irq, void *dev)
0930 {
0931     struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev;
0932     struct octeon_device *oct = ioq_vector->oct_dev;
0933     struct octeon_droq *droq = oct->droq[ioq_vector->droq_index];
0934     u64 ret;
0935 
0936     ret = oct->fn_list.msix_interrupt_handler(ioq_vector);
0937 
0938     if (ret & MSIX_PO_INT || ret & MSIX_PI_INT)
0939         liquidio_schedule_msix_droq_pkt_handler(droq, ret);
0940 
0941     return IRQ_HANDLED;
0942 }
0943 
0944 /**
0945  * liquidio_schedule_droq_pkt_handlers - Droq packet processor sceduler
0946  * @oct: octeon device
0947  */
0948 static void liquidio_schedule_droq_pkt_handlers(struct octeon_device *oct)
0949 {
0950     struct octeon_device_priv *oct_priv =
0951         (struct octeon_device_priv *)oct->priv;
0952     struct octeon_droq *droq;
0953     u64 oq_no;
0954 
0955     if (oct->int_status & OCT_DEV_INTR_PKT_DATA) {
0956         for (oq_no = 0; oq_no < MAX_OCTEON_OUTPUT_QUEUES(oct);
0957              oq_no++) {
0958             if (!(oct->droq_intr & BIT_ULL(oq_no)))
0959                 continue;
0960 
0961             droq = oct->droq[oq_no];
0962 
0963             if (droq->ops.poll_mode) {
0964                 droq->ops.napi_fn(droq);
0965                 oct_priv->napi_mask |= BIT_ULL(oq_no);
0966             } else {
0967                 tasklet_schedule(&oct_priv->droq_tasklet);
0968             }
0969         }
0970     }
0971 }
0972 
0973 /**
0974  * liquidio_legacy_intr_handler - Interrupt handler for octeon
0975  * @irq: unused
0976  * @dev: octeon device
0977  */
0978 static
0979 irqreturn_t liquidio_legacy_intr_handler(int __maybe_unused irq, void *dev)
0980 {
0981     struct octeon_device *oct = (struct octeon_device *)dev;
0982     irqreturn_t ret;
0983 
0984     /* Disable our interrupts for the duration of ISR */
0985     oct->fn_list.disable_interrupt(oct, OCTEON_ALL_INTR);
0986 
0987     ret = oct->fn_list.process_interrupt_regs(oct);
0988 
0989     if (ret == IRQ_HANDLED)
0990         liquidio_schedule_droq_pkt_handlers(oct);
0991 
0992     /* Re-enable our interrupts  */
0993     if (!(atomic_read(&oct->status) == OCT_DEV_IN_RESET))
0994         oct->fn_list.enable_interrupt(oct, OCTEON_ALL_INTR);
0995 
0996     return ret;
0997 }
0998 
0999 /**
1000  * octeon_setup_interrupt - Setup interrupt for octeon device
1001  * @oct: octeon device
1002  * @num_ioqs: number of queues
1003  *
1004  *  Enable interrupt in Octeon device as given in the PCI interrupt mask.
1005  */
1006 int octeon_setup_interrupt(struct octeon_device *oct, u32 num_ioqs)
1007 {
1008     struct msix_entry *msix_entries;
1009     char *queue_irq_names = NULL;
1010     int i, num_interrupts = 0;
1011     int num_alloc_ioq_vectors;
1012     char *aux_irq_name = NULL;
1013     int num_ioq_vectors;
1014     int irqret, err;
1015 
1016     if (oct->msix_on) {
1017         oct->num_msix_irqs = num_ioqs;
1018         if (OCTEON_CN23XX_PF(oct)) {
1019             num_interrupts = MAX_IOQ_INTERRUPTS_PER_PF + 1;
1020 
1021             /* one non ioq interrupt for handling
1022              * sli_mac_pf_int_sum
1023              */
1024             oct->num_msix_irqs += 1;
1025         } else if (OCTEON_CN23XX_VF(oct)) {
1026             num_interrupts = MAX_IOQ_INTERRUPTS_PER_VF;
1027         }
1028 
1029         /* allocate storage for the names assigned to each irq */
1030         oct->irq_name_storage =
1031             kcalloc(num_interrupts, INTRNAMSIZ, GFP_KERNEL);
1032         if (!oct->irq_name_storage) {
1033             dev_err(&oct->pci_dev->dev, "Irq name storage alloc failed...\n");
1034             return -ENOMEM;
1035         }
1036 
1037         queue_irq_names = oct->irq_name_storage;
1038 
1039         if (OCTEON_CN23XX_PF(oct))
1040             aux_irq_name = &queue_irq_names
1041                 [IRQ_NAME_OFF(MAX_IOQ_INTERRUPTS_PER_PF)];
1042 
1043         oct->msix_entries = kcalloc(oct->num_msix_irqs,
1044                         sizeof(struct msix_entry),
1045                         GFP_KERNEL);
1046         if (!oct->msix_entries) {
1047             dev_err(&oct->pci_dev->dev, "Memory Alloc failed...\n");
1048             kfree(oct->irq_name_storage);
1049             oct->irq_name_storage = NULL;
1050             return -ENOMEM;
1051         }
1052 
1053         msix_entries = (struct msix_entry *)oct->msix_entries;
1054 
1055         /*Assumption is that pf msix vectors start from pf srn to pf to
1056          * trs and not from 0. if not change this code
1057          */
1058         if (OCTEON_CN23XX_PF(oct)) {
1059             for (i = 0; i < oct->num_msix_irqs - 1; i++)
1060                 msix_entries[i].entry =
1061                     oct->sriov_info.pf_srn + i;
1062 
1063             msix_entries[oct->num_msix_irqs - 1].entry =
1064                 oct->sriov_info.trs;
1065         } else if (OCTEON_CN23XX_VF(oct)) {
1066             for (i = 0; i < oct->num_msix_irqs; i++)
1067                 msix_entries[i].entry = i;
1068         }
1069         num_alloc_ioq_vectors = pci_enable_msix_range(
1070                         oct->pci_dev, msix_entries,
1071                         oct->num_msix_irqs,
1072                         oct->num_msix_irqs);
1073         if (num_alloc_ioq_vectors < 0) {
1074             dev_err(&oct->pci_dev->dev, "unable to Allocate MSI-X interrupts\n");
1075             kfree(oct->msix_entries);
1076             oct->msix_entries = NULL;
1077             kfree(oct->irq_name_storage);
1078             oct->irq_name_storage = NULL;
1079             return num_alloc_ioq_vectors;
1080         }
1081 
1082         dev_dbg(&oct->pci_dev->dev, "OCTEON: Enough MSI-X interrupts are allocated...\n");
1083 
1084         num_ioq_vectors = oct->num_msix_irqs;
1085         /* For PF, there is one non-ioq interrupt handler */
1086         if (OCTEON_CN23XX_PF(oct)) {
1087             num_ioq_vectors -= 1;
1088 
1089             snprintf(aux_irq_name, INTRNAMSIZ,
1090                  "LiquidIO%u-pf%u-aux", oct->octeon_id,
1091                  oct->pf_num);
1092             irqret = request_irq(
1093                     msix_entries[num_ioq_vectors].vector,
1094                     liquidio_legacy_intr_handler, 0,
1095                     aux_irq_name, oct);
1096             if (irqret) {
1097                 dev_err(&oct->pci_dev->dev,
1098                     "Request_irq failed for MSIX interrupt Error: %d\n",
1099                     irqret);
1100                 pci_disable_msix(oct->pci_dev);
1101                 kfree(oct->msix_entries);
1102                 kfree(oct->irq_name_storage);
1103                 oct->irq_name_storage = NULL;
1104                 oct->msix_entries = NULL;
1105                 return irqret;
1106             }
1107         }
1108         for (i = 0 ; i < num_ioq_vectors ; i++) {
1109             if (OCTEON_CN23XX_PF(oct))
1110                 snprintf(&queue_irq_names[IRQ_NAME_OFF(i)],
1111                      INTRNAMSIZ, "LiquidIO%u-pf%u-rxtx-%u",
1112                      oct->octeon_id, oct->pf_num, i);
1113 
1114             if (OCTEON_CN23XX_VF(oct))
1115                 snprintf(&queue_irq_names[IRQ_NAME_OFF(i)],
1116                      INTRNAMSIZ, "LiquidIO%u-vf%u-rxtx-%u",
1117                      oct->octeon_id, oct->vf_num, i);
1118 
1119             irqret = request_irq(msix_entries[i].vector,
1120                          liquidio_msix_intr_handler, 0,
1121                          &queue_irq_names[IRQ_NAME_OFF(i)],
1122                          &oct->ioq_vector[i]);
1123 
1124             if (irqret) {
1125                 dev_err(&oct->pci_dev->dev,
1126                     "Request_irq failed for MSIX interrupt Error: %d\n",
1127                     irqret);
1128                 /* Freeing the non-ioq irq vector here . */
1129                 free_irq(msix_entries[num_ioq_vectors].vector,
1130                      oct);
1131 
1132                 while (i) {
1133                     i--;
1134                     /* clearing affinity mask. */
1135                     irq_set_affinity_hint(
1136                               msix_entries[i].vector,
1137                               NULL);
1138                     free_irq(msix_entries[i].vector,
1139                          &oct->ioq_vector[i]);
1140                 }
1141                 pci_disable_msix(oct->pci_dev);
1142                 kfree(oct->msix_entries);
1143                 kfree(oct->irq_name_storage);
1144                 oct->irq_name_storage = NULL;
1145                 oct->msix_entries = NULL;
1146                 return irqret;
1147             }
1148             oct->ioq_vector[i].vector = msix_entries[i].vector;
1149             /* assign the cpu mask for this msix interrupt vector */
1150             irq_set_affinity_hint(msix_entries[i].vector,
1151                           &oct->ioq_vector[i].affinity_mask
1152                           );
1153         }
1154         dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: MSI-X enabled\n",
1155             oct->octeon_id);
1156     } else {
1157         err = pci_enable_msi(oct->pci_dev);
1158         if (err)
1159             dev_warn(&oct->pci_dev->dev, "Reverting to legacy interrupts. Error: %d\n",
1160                  err);
1161         else
1162             oct->flags |= LIO_FLAG_MSI_ENABLED;
1163 
1164         /* allocate storage for the names assigned to the irq */
1165         oct->irq_name_storage = kzalloc(INTRNAMSIZ, GFP_KERNEL);
1166         if (!oct->irq_name_storage)
1167             return -ENOMEM;
1168 
1169         queue_irq_names = oct->irq_name_storage;
1170 
1171         if (OCTEON_CN23XX_PF(oct))
1172             snprintf(&queue_irq_names[IRQ_NAME_OFF(0)], INTRNAMSIZ,
1173                  "LiquidIO%u-pf%u-rxtx-%u",
1174                  oct->octeon_id, oct->pf_num, 0);
1175 
1176         if (OCTEON_CN23XX_VF(oct))
1177             snprintf(&queue_irq_names[IRQ_NAME_OFF(0)], INTRNAMSIZ,
1178                  "LiquidIO%u-vf%u-rxtx-%u",
1179                  oct->octeon_id, oct->vf_num, 0);
1180 
1181         irqret = request_irq(oct->pci_dev->irq,
1182                      liquidio_legacy_intr_handler,
1183                      IRQF_SHARED,
1184                      &queue_irq_names[IRQ_NAME_OFF(0)], oct);
1185         if (irqret) {
1186             if (oct->flags & LIO_FLAG_MSI_ENABLED)
1187                 pci_disable_msi(oct->pci_dev);
1188             dev_err(&oct->pci_dev->dev, "Request IRQ failed with code: %d\n",
1189                 irqret);
1190             kfree(oct->irq_name_storage);
1191             oct->irq_name_storage = NULL;
1192             return irqret;
1193         }
1194     }
1195     return 0;
1196 }
1197 
1198 /**
1199  * liquidio_change_mtu - Net device change_mtu
1200  * @netdev: network device
1201  * @new_mtu: the new max transmit unit size
1202  */
1203 int liquidio_change_mtu(struct net_device *netdev, int new_mtu)
1204 {
1205     struct lio *lio = GET_LIO(netdev);
1206     struct octeon_device *oct = lio->oct_dev;
1207     struct octeon_soft_command *sc;
1208     union octnet_cmd *ncmd;
1209     int ret = 0;
1210 
1211     sc = (struct octeon_soft_command *)
1212         octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE, 16, 0);
1213     if (!sc) {
1214         netif_info(lio, rx_err, lio->netdev,
1215                "Failed to allocate soft command\n");
1216         return -ENOMEM;
1217     }
1218 
1219     ncmd = (union octnet_cmd *)sc->virtdptr;
1220 
1221     init_completion(&sc->complete);
1222     sc->sc_status = OCTEON_REQUEST_PENDING;
1223 
1224     ncmd->u64 = 0;
1225     ncmd->s.cmd = OCTNET_CMD_CHANGE_MTU;
1226     ncmd->s.param1 = new_mtu;
1227 
1228     octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1229 
1230     sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1231 
1232     octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1233                     OPCODE_NIC_CMD, 0, 0, 0);
1234 
1235     ret = octeon_send_soft_command(oct, sc);
1236     if (ret == IQ_SEND_FAILED) {
1237         netif_info(lio, rx_err, lio->netdev, "Failed to change MTU\n");
1238         octeon_free_soft_command(oct, sc);
1239         return -EINVAL;
1240     }
1241     /* Sleep on a wait queue till the cond flag indicates that the
1242      * response arrived or timed-out.
1243      */
1244     ret = wait_for_sc_completion_timeout(oct, sc, 0);
1245     if (ret)
1246         return ret;
1247 
1248     if (sc->sc_status) {
1249         WRITE_ONCE(sc->caller_is_done, true);
1250         return -EINVAL;
1251     }
1252 
1253     netdev->mtu = new_mtu;
1254     lio->mtu = new_mtu;
1255 
1256     WRITE_ONCE(sc->caller_is_done, true);
1257     return 0;
1258 }
1259 
1260 int lio_wait_for_clean_oq(struct octeon_device *oct)
1261 {
1262     int retry = 100, pending_pkts = 0;
1263     int idx;
1264 
1265     do {
1266         pending_pkts = 0;
1267 
1268         for (idx = 0; idx < MAX_OCTEON_OUTPUT_QUEUES(oct); idx++) {
1269             if (!(oct->io_qmask.oq & BIT_ULL(idx)))
1270                 continue;
1271             pending_pkts +=
1272                 atomic_read(&oct->droq[idx]->pkts_pending);
1273         }
1274 
1275         if (pending_pkts > 0)
1276             schedule_timeout_uninterruptible(1);
1277 
1278     } while (retry-- && pending_pkts);
1279 
1280     return pending_pkts;
1281 }
1282 
1283 static void
1284 octnet_nic_stats_callback(struct octeon_device *oct_dev,
1285               u32 status, void *ptr)
1286 {
1287     struct octeon_soft_command *sc = (struct octeon_soft_command *)ptr;
1288     struct oct_nic_stats_resp *resp =
1289         (struct oct_nic_stats_resp *)sc->virtrptr;
1290     struct nic_rx_stats *rsp_rstats = &resp->stats.fromwire;
1291     struct nic_tx_stats *rsp_tstats = &resp->stats.fromhost;
1292     struct nic_rx_stats *rstats = &oct_dev->link_stats.fromwire;
1293     struct nic_tx_stats *tstats = &oct_dev->link_stats.fromhost;
1294 
1295     if (status != OCTEON_REQUEST_TIMEOUT && !resp->status) {
1296         octeon_swap_8B_data((u64 *)&resp->stats,
1297                     (sizeof(struct oct_link_stats)) >> 3);
1298 
1299         /* RX link-level stats */
1300         rstats->total_rcvd = rsp_rstats->total_rcvd;
1301         rstats->bytes_rcvd = rsp_rstats->bytes_rcvd;
1302         rstats->total_bcst = rsp_rstats->total_bcst;
1303         rstats->total_mcst = rsp_rstats->total_mcst;
1304         rstats->runts      = rsp_rstats->runts;
1305         rstats->ctl_rcvd   = rsp_rstats->ctl_rcvd;
1306         /* Accounts for over/under-run of buffers */
1307         rstats->fifo_err  = rsp_rstats->fifo_err;
1308         rstats->dmac_drop = rsp_rstats->dmac_drop;
1309         rstats->fcs_err   = rsp_rstats->fcs_err;
1310         rstats->jabber_err = rsp_rstats->jabber_err;
1311         rstats->l2_err    = rsp_rstats->l2_err;
1312         rstats->frame_err = rsp_rstats->frame_err;
1313         rstats->red_drops = rsp_rstats->red_drops;
1314 
1315         /* RX firmware stats */
1316         rstats->fw_total_rcvd = rsp_rstats->fw_total_rcvd;
1317         rstats->fw_total_fwd = rsp_rstats->fw_total_fwd;
1318         rstats->fw_total_mcast = rsp_rstats->fw_total_mcast;
1319         rstats->fw_total_bcast = rsp_rstats->fw_total_bcast;
1320         rstats->fw_err_pko = rsp_rstats->fw_err_pko;
1321         rstats->fw_err_link = rsp_rstats->fw_err_link;
1322         rstats->fw_err_drop = rsp_rstats->fw_err_drop;
1323         rstats->fw_rx_vxlan = rsp_rstats->fw_rx_vxlan;
1324         rstats->fw_rx_vxlan_err = rsp_rstats->fw_rx_vxlan_err;
1325 
1326         /* Number of packets that are LROed      */
1327         rstats->fw_lro_pkts = rsp_rstats->fw_lro_pkts;
1328         /* Number of octets that are LROed       */
1329         rstats->fw_lro_octs = rsp_rstats->fw_lro_octs;
1330         /* Number of LRO packets formed          */
1331         rstats->fw_total_lro = rsp_rstats->fw_total_lro;
1332         /* Number of times lRO of packet aborted */
1333         rstats->fw_lro_aborts = rsp_rstats->fw_lro_aborts;
1334         rstats->fw_lro_aborts_port = rsp_rstats->fw_lro_aborts_port;
1335         rstats->fw_lro_aborts_seq = rsp_rstats->fw_lro_aborts_seq;
1336         rstats->fw_lro_aborts_tsval = rsp_rstats->fw_lro_aborts_tsval;
1337         rstats->fw_lro_aborts_timer = rsp_rstats->fw_lro_aborts_timer;
1338         /* intrmod: packet forward rate */
1339         rstats->fwd_rate = rsp_rstats->fwd_rate;
1340 
1341         /* TX link-level stats */
1342         tstats->total_pkts_sent = rsp_tstats->total_pkts_sent;
1343         tstats->total_bytes_sent = rsp_tstats->total_bytes_sent;
1344         tstats->mcast_pkts_sent = rsp_tstats->mcast_pkts_sent;
1345         tstats->bcast_pkts_sent = rsp_tstats->bcast_pkts_sent;
1346         tstats->ctl_sent = rsp_tstats->ctl_sent;
1347         /* Packets sent after one collision*/
1348         tstats->one_collision_sent = rsp_tstats->one_collision_sent;
1349         /* Packets sent after multiple collision*/
1350         tstats->multi_collision_sent = rsp_tstats->multi_collision_sent;
1351         /* Packets not sent due to max collisions */
1352         tstats->max_collision_fail = rsp_tstats->max_collision_fail;
1353         /* Packets not sent due to max deferrals */
1354         tstats->max_deferral_fail = rsp_tstats->max_deferral_fail;
1355         /* Accounts for over/under-run of buffers */
1356         tstats->fifo_err = rsp_tstats->fifo_err;
1357         tstats->runts = rsp_tstats->runts;
1358         /* Total number of collisions detected */
1359         tstats->total_collisions = rsp_tstats->total_collisions;
1360 
1361         /* firmware stats */
1362         tstats->fw_total_sent = rsp_tstats->fw_total_sent;
1363         tstats->fw_total_fwd = rsp_tstats->fw_total_fwd;
1364         tstats->fw_total_mcast_sent = rsp_tstats->fw_total_mcast_sent;
1365         tstats->fw_total_bcast_sent = rsp_tstats->fw_total_bcast_sent;
1366         tstats->fw_err_pko = rsp_tstats->fw_err_pko;
1367         tstats->fw_err_pki = rsp_tstats->fw_err_pki;
1368         tstats->fw_err_link = rsp_tstats->fw_err_link;
1369         tstats->fw_err_drop = rsp_tstats->fw_err_drop;
1370         tstats->fw_tso = rsp_tstats->fw_tso;
1371         tstats->fw_tso_fwd = rsp_tstats->fw_tso_fwd;
1372         tstats->fw_err_tso = rsp_tstats->fw_err_tso;
1373         tstats->fw_tx_vxlan = rsp_tstats->fw_tx_vxlan;
1374 
1375         resp->status = 1;
1376     } else {
1377         dev_err(&oct_dev->pci_dev->dev, "sc OPCODE_NIC_PORT_STATS command failed\n");
1378         resp->status = -1;
1379     }
1380 }
1381 
1382 static int lio_fetch_vf_stats(struct lio *lio)
1383 {
1384     struct octeon_device *oct_dev = lio->oct_dev;
1385     struct octeon_soft_command *sc;
1386     struct oct_nic_vf_stats_resp *resp;
1387 
1388     int retval;
1389 
1390     /* Alloc soft command */
1391     sc = (struct octeon_soft_command *)
1392         octeon_alloc_soft_command(oct_dev,
1393                       0,
1394                       sizeof(struct oct_nic_vf_stats_resp),
1395                       0);
1396 
1397     if (!sc) {
1398         dev_err(&oct_dev->pci_dev->dev, "Soft command allocation failed\n");
1399         retval = -ENOMEM;
1400         goto lio_fetch_vf_stats_exit;
1401     }
1402 
1403     resp = (struct oct_nic_vf_stats_resp *)sc->virtrptr;
1404     memset(resp, 0, sizeof(struct oct_nic_vf_stats_resp));
1405 
1406     init_completion(&sc->complete);
1407     sc->sc_status = OCTEON_REQUEST_PENDING;
1408 
1409     sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1410 
1411     octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
1412                     OPCODE_NIC_VF_PORT_STATS, 0, 0, 0);
1413 
1414     retval = octeon_send_soft_command(oct_dev, sc);
1415     if (retval == IQ_SEND_FAILED) {
1416         octeon_free_soft_command(oct_dev, sc);
1417         goto lio_fetch_vf_stats_exit;
1418     }
1419 
1420     retval =
1421         wait_for_sc_completion_timeout(oct_dev, sc,
1422                            (2 * LIO_SC_MAX_TMO_MS));
1423     if (retval)  {
1424         dev_err(&oct_dev->pci_dev->dev,
1425             "sc OPCODE_NIC_VF_PORT_STATS command failed\n");
1426         goto lio_fetch_vf_stats_exit;
1427     }
1428 
1429     if (sc->sc_status != OCTEON_REQUEST_TIMEOUT && !resp->status) {
1430         octeon_swap_8B_data((u64 *)&resp->spoofmac_cnt,
1431                     (sizeof(u64)) >> 3);
1432 
1433         if (resp->spoofmac_cnt != 0) {
1434             dev_warn(&oct_dev->pci_dev->dev,
1435                  "%llu Spoofed packets detected\n",
1436                  resp->spoofmac_cnt);
1437         }
1438     }
1439     WRITE_ONCE(sc->caller_is_done, 1);
1440 
1441 lio_fetch_vf_stats_exit:
1442     return retval;
1443 }
1444 
1445 void lio_fetch_stats(struct work_struct *work)
1446 {
1447     struct cavium_wk *wk = (struct cavium_wk *)work;
1448     struct lio *lio = wk->ctxptr;
1449     struct octeon_device *oct_dev = lio->oct_dev;
1450     struct octeon_soft_command *sc;
1451     struct oct_nic_stats_resp *resp;
1452     unsigned long time_in_jiffies;
1453     int retval;
1454 
1455     if (OCTEON_CN23XX_PF(oct_dev)) {
1456         /* report spoofchk every 2 seconds */
1457         if (!(oct_dev->vfstats_poll % LIO_VFSTATS_POLL) &&
1458             (oct_dev->fw_info.app_cap_flags & LIQUIDIO_SPOOFCHK_CAP) &&
1459             oct_dev->sriov_info.num_vfs_alloced) {
1460             lio_fetch_vf_stats(lio);
1461         }
1462 
1463         oct_dev->vfstats_poll++;
1464     }
1465 
1466     /* Alloc soft command */
1467     sc = (struct octeon_soft_command *)
1468         octeon_alloc_soft_command(oct_dev,
1469                       0,
1470                       sizeof(struct oct_nic_stats_resp),
1471                       0);
1472 
1473     if (!sc) {
1474         dev_err(&oct_dev->pci_dev->dev, "Soft command allocation failed\n");
1475         goto lio_fetch_stats_exit;
1476     }
1477 
1478     resp = (struct oct_nic_stats_resp *)sc->virtrptr;
1479     memset(resp, 0, sizeof(struct oct_nic_stats_resp));
1480 
1481     init_completion(&sc->complete);
1482     sc->sc_status = OCTEON_REQUEST_PENDING;
1483 
1484     sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1485 
1486     octeon_prepare_soft_command(oct_dev, sc, OPCODE_NIC,
1487                     OPCODE_NIC_PORT_STATS, 0, 0, 0);
1488 
1489     retval = octeon_send_soft_command(oct_dev, sc);
1490     if (retval == IQ_SEND_FAILED) {
1491         octeon_free_soft_command(oct_dev, sc);
1492         goto lio_fetch_stats_exit;
1493     }
1494 
1495     retval = wait_for_sc_completion_timeout(oct_dev, sc,
1496                         (2 * LIO_SC_MAX_TMO_MS));
1497     if (retval)  {
1498         dev_err(&oct_dev->pci_dev->dev, "sc OPCODE_NIC_PORT_STATS command failed\n");
1499         goto lio_fetch_stats_exit;
1500     }
1501 
1502     octnet_nic_stats_callback(oct_dev, sc->sc_status, sc);
1503     WRITE_ONCE(sc->caller_is_done, true);
1504 
1505 lio_fetch_stats_exit:
1506     time_in_jiffies = msecs_to_jiffies(LIQUIDIO_NDEV_STATS_POLL_TIME_MS);
1507     if (ifstate_check(lio, LIO_IFSTATE_RUNNING))
1508         schedule_delayed_work(&lio->stats_wk.work, time_in_jiffies);
1509 
1510     return;
1511 }
1512 
1513 int liquidio_set_speed(struct lio *lio, int speed)
1514 {
1515     struct octeon_device *oct = lio->oct_dev;
1516     struct oct_nic_seapi_resp *resp;
1517     struct octeon_soft_command *sc;
1518     union octnet_cmd *ncmd;
1519     int retval;
1520     u32 var;
1521 
1522     if (oct->speed_setting == speed)
1523         return 0;
1524 
1525     if (!OCTEON_CN23XX_PF(oct)) {
1526         dev_err(&oct->pci_dev->dev, "%s: SET SPEED only for PF\n",
1527             __func__);
1528         return -EOPNOTSUPP;
1529     }
1530 
1531     sc = octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
1532                        sizeof(struct oct_nic_seapi_resp),
1533                        0);
1534     if (!sc)
1535         return -ENOMEM;
1536 
1537     ncmd = sc->virtdptr;
1538     resp = sc->virtrptr;
1539     memset(resp, 0, sizeof(struct oct_nic_seapi_resp));
1540 
1541     init_completion(&sc->complete);
1542     sc->sc_status = OCTEON_REQUEST_PENDING;
1543 
1544     ncmd->u64 = 0;
1545     ncmd->s.cmd = SEAPI_CMD_SPEED_SET;
1546     ncmd->s.param1 = speed;
1547 
1548     octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1549 
1550     sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1551 
1552     octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1553                     OPCODE_NIC_UBOOT_CTL, 0, 0, 0);
1554 
1555     retval = octeon_send_soft_command(oct, sc);
1556     if (retval == IQ_SEND_FAILED) {
1557         dev_info(&oct->pci_dev->dev, "Failed to send soft command\n");
1558         octeon_free_soft_command(oct, sc);
1559         retval = -EBUSY;
1560     } else {
1561         /* Wait for response or timeout */
1562         retval = wait_for_sc_completion_timeout(oct, sc, 0);
1563         if (retval)
1564             return retval;
1565 
1566         retval = resp->status;
1567 
1568         if (retval) {
1569             dev_err(&oct->pci_dev->dev, "%s failed, retval=%d\n",
1570                 __func__, retval);
1571             WRITE_ONCE(sc->caller_is_done, true);
1572 
1573             return -EIO;
1574         }
1575 
1576         var = be32_to_cpu((__force __be32)resp->speed);
1577         if (var != speed) {
1578             dev_err(&oct->pci_dev->dev,
1579                 "%s: setting failed speed= %x, expect %x\n",
1580                 __func__, var, speed);
1581         }
1582 
1583         oct->speed_setting = var;
1584         WRITE_ONCE(sc->caller_is_done, true);
1585     }
1586 
1587     return retval;
1588 }
1589 
1590 int liquidio_get_speed(struct lio *lio)
1591 {
1592     struct octeon_device *oct = lio->oct_dev;
1593     struct oct_nic_seapi_resp *resp;
1594     struct octeon_soft_command *sc;
1595     union octnet_cmd *ncmd;
1596     int retval;
1597 
1598     sc = octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
1599                        sizeof(struct oct_nic_seapi_resp),
1600                        0);
1601     if (!sc)
1602         return -ENOMEM;
1603 
1604     ncmd = sc->virtdptr;
1605     resp = sc->virtrptr;
1606     memset(resp, 0, sizeof(struct oct_nic_seapi_resp));
1607 
1608     init_completion(&sc->complete);
1609     sc->sc_status = OCTEON_REQUEST_PENDING;
1610 
1611     ncmd->u64 = 0;
1612     ncmd->s.cmd = SEAPI_CMD_SPEED_GET;
1613 
1614     octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1615 
1616     sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1617 
1618     octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1619                     OPCODE_NIC_UBOOT_CTL, 0, 0, 0);
1620 
1621     retval = octeon_send_soft_command(oct, sc);
1622     if (retval == IQ_SEND_FAILED) {
1623         dev_info(&oct->pci_dev->dev, "Failed to send soft command\n");
1624         octeon_free_soft_command(oct, sc);
1625         retval = -EIO;
1626     } else {
1627         retval = wait_for_sc_completion_timeout(oct, sc, 0);
1628         if (retval)
1629             return retval;
1630 
1631         retval = resp->status;
1632         if (retval) {
1633             dev_err(&oct->pci_dev->dev,
1634                 "%s failed retval=%d\n", __func__, retval);
1635             retval = -EIO;
1636         } else {
1637             u32 var;
1638 
1639             var = be32_to_cpu((__force __be32)resp->speed);
1640             oct->speed_setting = var;
1641             if (var == 0xffff) {
1642                 /* unable to access boot variables
1643                  * get the default value based on the NIC type
1644                  */
1645                 if (oct->subsystem_id ==
1646                         OCTEON_CN2350_25GB_SUBSYS_ID ||
1647                     oct->subsystem_id ==
1648                         OCTEON_CN2360_25GB_SUBSYS_ID) {
1649                     oct->no_speed_setting = 1;
1650                     oct->speed_setting = 25;
1651                 } else {
1652                     oct->speed_setting = 10;
1653                 }
1654             }
1655 
1656         }
1657         WRITE_ONCE(sc->caller_is_done, true);
1658     }
1659 
1660     return retval;
1661 }
1662 
1663 int liquidio_set_fec(struct lio *lio, int on_off)
1664 {
1665     struct oct_nic_seapi_resp *resp;
1666     struct octeon_soft_command *sc;
1667     struct octeon_device *oct;
1668     union octnet_cmd *ncmd;
1669     int retval;
1670     u32 var;
1671 
1672     oct = lio->oct_dev;
1673 
1674     if (oct->props[lio->ifidx].fec == on_off)
1675         return 0;
1676 
1677     if (!OCTEON_CN23XX_PF(oct)) {
1678         dev_err(&oct->pci_dev->dev, "%s: SET FEC only for PF\n",
1679             __func__);
1680         return -1;
1681     }
1682 
1683     if (oct->speed_boot != 25)  {
1684         dev_err(&oct->pci_dev->dev,
1685             "Set FEC only when link speed is 25G during insmod\n");
1686         return -1;
1687     }
1688 
1689     sc = octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
1690                        sizeof(struct oct_nic_seapi_resp), 0);
1691     if (!sc) {
1692         dev_err(&oct->pci_dev->dev,
1693             "Failed to allocate soft command\n");
1694         return -ENOMEM;
1695     }
1696 
1697     ncmd = sc->virtdptr;
1698     resp = sc->virtrptr;
1699     memset(resp, 0, sizeof(struct oct_nic_seapi_resp));
1700 
1701     init_completion(&sc->complete);
1702     sc->sc_status = OCTEON_REQUEST_PENDING;
1703 
1704     ncmd->u64 = 0;
1705     ncmd->s.cmd = SEAPI_CMD_FEC_SET;
1706     ncmd->s.param1 = on_off;
1707     /* SEAPI_CMD_FEC_DISABLE(0) or SEAPI_CMD_FEC_RS(1) */
1708 
1709     octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1710 
1711     sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1712 
1713     octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1714                     OPCODE_NIC_UBOOT_CTL, 0, 0, 0);
1715 
1716     retval = octeon_send_soft_command(oct, sc);
1717     if (retval == IQ_SEND_FAILED) {
1718         dev_info(&oct->pci_dev->dev, "Failed to send soft command\n");
1719         octeon_free_soft_command(oct, sc);
1720         return -EIO;
1721     }
1722 
1723     retval = wait_for_sc_completion_timeout(oct, sc, 0);
1724     if (retval)
1725         return (-EIO);
1726 
1727     var = be32_to_cpu(resp->fec_setting);
1728     resp->fec_setting = var;
1729     if (var != on_off) {
1730         dev_err(&oct->pci_dev->dev,
1731             "Setting failed fec= %x, expect %x\n",
1732             var, on_off);
1733         oct->props[lio->ifidx].fec = var;
1734         if (resp->fec_setting == SEAPI_CMD_FEC_SET_RS)
1735             oct->props[lio->ifidx].fec = 1;
1736         else
1737             oct->props[lio->ifidx].fec = 0;
1738     }
1739 
1740     WRITE_ONCE(sc->caller_is_done, true);
1741 
1742     if (oct->props[lio->ifidx].fec !=
1743         oct->props[lio->ifidx].fec_boot) {
1744         dev_dbg(&oct->pci_dev->dev,
1745             "Reload driver to change fec to %s\n",
1746             oct->props[lio->ifidx].fec ? "on" : "off");
1747     }
1748 
1749     return retval;
1750 }
1751 
1752 int liquidio_get_fec(struct lio *lio)
1753 {
1754     struct oct_nic_seapi_resp *resp;
1755     struct octeon_soft_command *sc;
1756     struct octeon_device *oct;
1757     union octnet_cmd *ncmd;
1758     int retval;
1759     u32 var;
1760 
1761     oct = lio->oct_dev;
1762 
1763     sc = octeon_alloc_soft_command(oct, OCTNET_CMD_SIZE,
1764                        sizeof(struct oct_nic_seapi_resp), 0);
1765     if (!sc)
1766         return -ENOMEM;
1767 
1768     ncmd = sc->virtdptr;
1769     resp = sc->virtrptr;
1770     memset(resp, 0, sizeof(struct oct_nic_seapi_resp));
1771 
1772     init_completion(&sc->complete);
1773     sc->sc_status = OCTEON_REQUEST_PENDING;
1774 
1775     ncmd->u64 = 0;
1776     ncmd->s.cmd = SEAPI_CMD_FEC_GET;
1777 
1778     octeon_swap_8B_data((u64 *)ncmd, (OCTNET_CMD_SIZE >> 3));
1779 
1780     sc->iq_no = lio->linfo.txpciq[0].s.q_no;
1781 
1782     octeon_prepare_soft_command(oct, sc, OPCODE_NIC,
1783                     OPCODE_NIC_UBOOT_CTL, 0, 0, 0);
1784 
1785     retval = octeon_send_soft_command(oct, sc);
1786     if (retval == IQ_SEND_FAILED) {
1787         dev_info(&oct->pci_dev->dev,
1788              "%s: Failed to send soft command\n", __func__);
1789         octeon_free_soft_command(oct, sc);
1790         return -EIO;
1791     }
1792 
1793     retval = wait_for_sc_completion_timeout(oct, sc, 0);
1794     if (retval)
1795         return retval;
1796 
1797     var = be32_to_cpu(resp->fec_setting);
1798     resp->fec_setting = var;
1799     if (resp->fec_setting == SEAPI_CMD_FEC_SET_RS)
1800         oct->props[lio->ifidx].fec = 1;
1801     else
1802         oct->props[lio->ifidx].fec = 0;
1803 
1804     WRITE_ONCE(sc->caller_is_done, true);
1805 
1806     if (oct->props[lio->ifidx].fec !=
1807         oct->props[lio->ifidx].fec_boot) {
1808         dev_dbg(&oct->pci_dev->dev,
1809             "Reload driver to change fec to %s\n",
1810             oct->props[lio->ifidx].fec ? "on" : "off");
1811     }
1812 
1813     return retval;
1814 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!