cavium/liquidio/cn68xx_device.c

0001 /**********************************************************************
0002  * Author: Cavium, Inc.
0003  *
0004  * Contact: support@cavium.com
0005  *          Please include "LiquidIO" in the subject.
0006  *
0007  * Copyright (c) 2003-2016 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more details.
0017  ***********************************************************************/
0018 #include <linux/pci.h>
0019 #include <linux/netdevice.h>
0020 #include "liquidio_common.h"
0021 #include "octeon_droq.h"
0022 #include "octeon_iq.h"
0023 #include "response_manager.h"
0024 #include "octeon_device.h"
0025 #include "octeon_main.h"
0026 #include "cn66xx_regs.h"
0027 #include "cn66xx_device.h"
0028 #include "cn68xx_device.h"
0029 #include "cn68xx_regs.h"
0030
0031 static void lio_cn68xx_set_dpi_regs(struct octeon_device *oct)
0032 {
0033     u32 i;
0034     u32 fifo_sizes[6] = { 3, 3, 1, 1, 1, 8 };
0035
0036     lio_pci_writeq(oct, CN6XXX_DPI_DMA_CTL_MASK, CN6XXX_DPI_DMA_CONTROL);
0037     dev_dbg(&oct->pci_dev->dev, "DPI_DMA_CONTROL: 0x%016llx\n",
0038         lio_pci_readq(oct, CN6XXX_DPI_DMA_CONTROL));
0039
0040     for (i = 0; i < 6; i++) {
0041         /* Prevent service of instruction queue for all DMA engines
0042          * Engine 5 will remain 0. Engines 0 - 4 will be setup by
0043          * core.
0044          */
0045         lio_pci_writeq(oct, 0, CN6XXX_DPI_DMA_ENG_ENB(i));
0046         lio_pci_writeq(oct, fifo_sizes[i], CN6XXX_DPI_DMA_ENG_BUF(i));
0047         dev_dbg(&oct->pci_dev->dev, "DPI_ENG_BUF%d: 0x%016llx\n", i,
0048             lio_pci_readq(oct, CN6XXX_DPI_DMA_ENG_BUF(i)));
0049     }
0050
0051     /* DPI_SLI_PRT_CFG has MPS and MRRS settings that will be set
0052      * separately.
0053      */
0054
0055     lio_pci_writeq(oct, 1, CN6XXX_DPI_CTL);
0056     dev_dbg(&oct->pci_dev->dev, "DPI_CTL: 0x%016llx\n",
0057         lio_pci_readq(oct, CN6XXX_DPI_CTL));
0058 }
0059
0060 static int lio_cn68xx_soft_reset(struct octeon_device *oct)
0061 {
0062     lio_cn6xxx_soft_reset(oct);
0063     lio_cn68xx_set_dpi_regs(oct);
0064
0065     return 0;
0066 }
0067
0068 static void lio_cn68xx_setup_pkt_ctl_regs(struct octeon_device *oct)
0069 {
0070     struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;
0071     u64 pktctl, tx_pipe, max_oqs;
0072
0073     pktctl = octeon_read_csr64(oct, CN6XXX_SLI_PKT_CTL);
0074
0075     /* 68XX specific */
0076     max_oqs = CFG_GET_OQ_MAX_Q(CHIP_CONF(oct, cn6xxx));
0077     tx_pipe  = octeon_read_csr64(oct, CN68XX_SLI_TX_PIPE);
0078     tx_pipe &= 0xffffffffff00ffffULL; /* clear out NUMP field */
0079     tx_pipe |= max_oqs << 16; /* put max_oqs in NUMP field */
0080     octeon_write_csr64(oct, CN68XX_SLI_TX_PIPE, tx_pipe);
0081
0082     if (CFG_GET_IS_SLI_BP_ON(cn68xx->conf))
0083         pktctl |= 0xF;
0084     else
0085         /* Disable per-port backpressure. */
0086         pktctl &= ~0xF;
0087     octeon_write_csr64(oct, CN6XXX_SLI_PKT_CTL, pktctl);
0088 }
0089
0090 static int lio_cn68xx_setup_device_regs(struct octeon_device *oct)
0091 {
0092     lio_cn6xxx_setup_pcie_mps(oct, PCIE_MPS_DEFAULT);
0093     lio_cn6xxx_setup_pcie_mrrs(oct, PCIE_MRRS_256B);
0094     lio_cn6xxx_enable_error_reporting(oct);
0095
0096     lio_cn6xxx_setup_global_input_regs(oct);
0097     lio_cn68xx_setup_pkt_ctl_regs(oct);
0098     lio_cn6xxx_setup_global_output_regs(oct);
0099
0100     /* Default error timeout value should be 0x200000 to avoid host hang
0101      * when reads invalid register
0102      */
0103     octeon_write_csr64(oct, CN6XXX_SLI_WINDOW_CTL, 0x200000ULL);
0104
0105     return 0;
0106 }
0107
0108 static inline void lio_cn68xx_vendor_message_fix(struct octeon_device *oct)
0109 {
0110     u32 val = 0;
0111
0112     /* Set M_VEND1_DRP and M_VEND0_DRP bits */
0113     pci_read_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, &val);
0114     val |= 0x3;
0115     pci_write_config_dword(oct->pci_dev, CN6XXX_PCIE_FLTMSK, val);
0116 }
0117
0118 static int lio_is_210nv(struct octeon_device *oct)
0119 {
0120     u64 mio_qlm4_cfg = lio_pci_readq(oct, CN6XXX_MIO_QLM4_CFG);
0121
0122     return ((mio_qlm4_cfg & CN6XXX_MIO_QLM_CFG_MASK) == 0);
0123 }
0124
0125 int lio_setup_cn68xx_octeon_device(struct octeon_device *oct)
0126 {
0127     struct octeon_cn6xxx *cn68xx = (struct octeon_cn6xxx *)oct->chip;
0128     u16 card_type = LIO_410NV;
0129
0130     if (octeon_map_pci_barx(oct, 0, 0))
0131         return 1;
0132
0133     if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) {
0134         dev_err(&oct->pci_dev->dev, "%s CN68XX BAR1 map failed\n",
0135             __func__);
0136         octeon_unmap_pci_barx(oct, 0);
0137         return 1;
0138     }
0139
0140     spin_lock_init(&cn68xx->lock_for_droq_int_enb_reg);
0141
0142     oct->fn_list.setup_iq_regs = lio_cn6xxx_setup_iq_regs;
0143     oct->fn_list.setup_oq_regs = lio_cn6xxx_setup_oq_regs;
0144
0145     oct->fn_list.process_interrupt_regs = lio_cn6xxx_process_interrupt_regs;
0146     oct->fn_list.soft_reset = lio_cn68xx_soft_reset;
0147     oct->fn_list.setup_device_regs = lio_cn68xx_setup_device_regs;
0148     oct->fn_list.update_iq_read_idx = lio_cn6xxx_update_read_index;
0149
0150     oct->fn_list.bar1_idx_setup = lio_cn6xxx_bar1_idx_setup;
0151     oct->fn_list.bar1_idx_write = lio_cn6xxx_bar1_idx_write;
0152     oct->fn_list.bar1_idx_read = lio_cn6xxx_bar1_idx_read;
0153
0154     oct->fn_list.enable_interrupt = lio_cn6xxx_enable_interrupt;
0155     oct->fn_list.disable_interrupt = lio_cn6xxx_disable_interrupt;
0156
0157     oct->fn_list.enable_io_queues = lio_cn6xxx_enable_io_queues;
0158     oct->fn_list.disable_io_queues = lio_cn6xxx_disable_io_queues;
0159
0160     lio_cn6xxx_setup_reg_address(oct, oct->chip, &oct->reg_list);
0161
0162     /* Determine variant of card */
0163     if (lio_is_210nv(oct))
0164         card_type = LIO_210NV;
0165
0166     cn68xx->conf = (struct octeon_config *)
0167                oct_get_config_info(oct, card_type);
0168     if (!cn68xx->conf) {
0169         dev_err(&oct->pci_dev->dev, "%s No Config found for CN68XX %s\n",
0170             __func__,
0171             (card_type == LIO_410NV) ? LIO_410NV_NAME :
0172             LIO_210NV_NAME);
0173         octeon_unmap_pci_barx(oct, 0);
0174         octeon_unmap_pci_barx(oct, 1);
0175         return 1;
0176     }
0177
0178     oct->coproc_clock_rate = 1000000ULL * lio_cn6xxx_coprocessor_clock(oct);
0179
0180     lio_cn68xx_vendor_message_fix(oct);
0181
0182     return 0;
0183 }