cavium/liquidio/cn66xx_device.h

0001 /**********************************************************************
0002  * Author: Cavium, Inc.
0003  *
0004  * Contact: support@cavium.com
0005  *          Please include "LiquidIO" in the subject.
0006  *
0007  * Copyright (c) 2003-2016 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more details.
0017  ***********************************************************************/
0018 /*! \file  cn66xx_device.h
0019  *  \brief Host Driver: Routines that perform CN66XX specific operations.
0020  */
0021
0022 #ifndef __CN66XX_DEVICE_H__
0023 #define  __CN66XX_DEVICE_H__
0024
0025 /* Register address and configuration for a CN6XXX devices.
0026  * If device specific changes need to be made then add a struct to include
0027  * device specific fields as shown in the commented section
0028  */
0029 struct octeon_cn6xxx {
0030     /** PCI interrupt summary register */
0031     u8 __iomem *intr_sum_reg64;
0032
0033     /** PCI interrupt enable register */
0034     u8 __iomem *intr_enb_reg64;
0035
0036     /** The PCI interrupt mask used by interrupt handler */
0037     u64 intr_mask64;
0038
0039     struct octeon_config *conf;
0040
0041     /* Example additional fields - not used currently
0042      *  struct {
0043      *  }cn6xyz;
0044      */
0045
0046     /* For the purpose of atomic access to interrupt enable reg */
0047     spinlock_t lock_for_droq_int_enb_reg;
0048
0049 };
0050
0051 enum octeon_pcie_mps {
0052     PCIE_MPS_DEFAULT = -1,  /* Use the default setup by BIOS */
0053     PCIE_MPS_128B = 0,
0054     PCIE_MPS_256B = 1
0055 };
0056
0057 enum octeon_pcie_mrrs {
0058     PCIE_MRRS_DEFAULT = -1, /* Use the default setup by BIOS */
0059     PCIE_MRRS_128B = 0,
0060     PCIE_MRRS_256B = 1,
0061     PCIE_MRRS_512B = 2,
0062     PCIE_MRRS_1024B = 3,
0063     PCIE_MRRS_2048B = 4,
0064     PCIE_MRRS_4096B = 5
0065 };
0066
0067 /* Common functions for 66xx and 68xx */
0068 int lio_cn6xxx_soft_reset(struct octeon_device *oct);
0069 void lio_cn6xxx_enable_error_reporting(struct octeon_device *oct);
0070 void lio_cn6xxx_setup_pcie_mps(struct octeon_device *oct,
0071                    enum octeon_pcie_mps mps);
0072 void lio_cn6xxx_setup_pcie_mrrs(struct octeon_device *oct,
0073                 enum octeon_pcie_mrrs mrrs);
0074 void lio_cn6xxx_setup_global_input_regs(struct octeon_device *oct);
0075 void lio_cn6xxx_setup_global_output_regs(struct octeon_device *oct);
0076 void lio_cn6xxx_setup_iq_regs(struct octeon_device *oct, u32 iq_no);
0077 void lio_cn6xxx_setup_oq_regs(struct octeon_device *oct, u32 oq_no);
0078 int lio_cn6xxx_enable_io_queues(struct octeon_device *oct);
0079 void lio_cn6xxx_disable_io_queues(struct octeon_device *oct);
0080 irqreturn_t lio_cn6xxx_process_interrupt_regs(void *dev);
0081 void lio_cn6xxx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr,
0082                    u32 idx, int valid);
0083 void lio_cn6xxx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask);
0084 u32 lio_cn6xxx_bar1_idx_read(struct octeon_device *oct, u32 idx);
0085 u32
0086 lio_cn6xxx_update_read_index(struct octeon_instr_queue *iq);
0087 void lio_cn6xxx_enable_interrupt(struct octeon_device *oct, u8 unused);
0088 void lio_cn6xxx_disable_interrupt(struct octeon_device *oct, u8 unused);
0089 void cn6xxx_get_pcie_qlmport(struct octeon_device *oct);
0090 void lio_cn6xxx_setup_reg_address(struct octeon_device *oct, void *chip,
0091                   struct octeon_reg_list *reg_list);
0092 u32 lio_cn6xxx_coprocessor_clock(struct octeon_device *oct);
0093 u32 lio_cn6xxx_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us);
0094 int lio_setup_cn66xx_octeon_device(struct octeon_device *oct);
0095 int lio_validate_cn6xxx_config_info(struct octeon_device *oct,
0096                     struct octeon_config *conf6xxx);
0097
0098 #endif