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0001 /**********************************************************************
0002  * Author: Cavium, Inc.
0003  *
0004  * Contact: support@cavium.com
0005  *          Please include "LiquidIO" in the subject.
0006  *
0007  * Copyright (c) 2003-2016 Cavium, Inc.
0008  *
0009  * This file is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License, Version 2, as
0011  * published by the Free Software Foundation.
0012  *
0013  * This file is distributed in the hope that it will be useful, but
0014  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
0015  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
0016  * NONINFRINGEMENT.  See the GNU General Public License for more details.
0017  ***********************************************************************/
0018 #include <linux/pci.h>
0019 #include <linux/vmalloc.h>
0020 #include <linux/etherdevice.h>
0021 #include "liquidio_common.h"
0022 #include "octeon_droq.h"
0023 #include "octeon_iq.h"
0024 #include "response_manager.h"
0025 #include "octeon_device.h"
0026 #include "cn23xx_pf_device.h"
0027 #include "octeon_main.h"
0028 #include "octeon_mailbox.h"
0029 
0030 #define RESET_NOTDONE 0
0031 #define RESET_DONE 1
0032 
0033 /* Change the value of SLI Packet Input Jabber Register to allow
0034  * VXLAN TSO packets which can be 64424 bytes, exceeding the
0035  * MAX_GSO_SIZE we supplied to the kernel
0036  */
0037 #define CN23XX_INPUT_JABBER 64600
0038 
0039 void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct)
0040 {
0041     int i = 0;
0042     u32 regval = 0;
0043     struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
0044 
0045     /*In cn23xx_soft_reset*/
0046     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%llx\n",
0047         "CN23XX_WIN_WR_MASK_REG", CVM_CAST64(CN23XX_WIN_WR_MASK_REG),
0048         CVM_CAST64(octeon_read_csr64(oct, CN23XX_WIN_WR_MASK_REG)));
0049     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
0050         "CN23XX_SLI_SCRATCH1", CVM_CAST64(CN23XX_SLI_SCRATCH1),
0051         CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1)));
0052     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
0053         "CN23XX_RST_SOFT_RST", CN23XX_RST_SOFT_RST,
0054         lio_pci_readq(oct, CN23XX_RST_SOFT_RST));
0055 
0056     /*In cn23xx_set_dpi_regs*/
0057     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
0058         "CN23XX_DPI_DMA_CONTROL", CN23XX_DPI_DMA_CONTROL,
0059         lio_pci_readq(oct, CN23XX_DPI_DMA_CONTROL));
0060 
0061     for (i = 0; i < 6; i++) {
0062         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0063             "CN23XX_DPI_DMA_ENG_ENB", i,
0064             CN23XX_DPI_DMA_ENG_ENB(i),
0065             lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_ENB(i)));
0066         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0067             "CN23XX_DPI_DMA_ENG_BUF", i,
0068             CN23XX_DPI_DMA_ENG_BUF(i),
0069             lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_BUF(i)));
0070     }
0071 
0072     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", "CN23XX_DPI_CTL",
0073         CN23XX_DPI_CTL, lio_pci_readq(oct, CN23XX_DPI_CTL));
0074 
0075     /*In cn23xx_setup_pcie_mps and cn23xx_setup_pcie_mrrs */
0076     pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval);
0077     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
0078         "CN23XX_CONFIG_PCIE_DEVCTL",
0079         CVM_CAST64(CN23XX_CONFIG_PCIE_DEVCTL), CVM_CAST64(regval));
0080 
0081     dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0082         "CN23XX_DPI_SLI_PRTX_CFG", oct->pcie_port,
0083         CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port),
0084         lio_pci_readq(oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port)));
0085 
0086     /*In cn23xx_specific_regs_setup */
0087     dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0088         "CN23XX_SLI_S2M_PORTX_CTL", oct->pcie_port,
0089         CVM_CAST64(CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)),
0090         CVM_CAST64(octeon_read_csr64(
0091             oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port))));
0092 
0093     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
0094         "CN23XX_SLI_RING_RST", CVM_CAST64(CN23XX_SLI_PKT_IOQ_RING_RST),
0095         (u64)octeon_read_csr64(oct, CN23XX_SLI_PKT_IOQ_RING_RST));
0096 
0097     /*In cn23xx_setup_global_mac_regs*/
0098     for (i = 0; i < CN23XX_MAX_MACS; i++) {
0099         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0100             "CN23XX_SLI_PKT_MAC_RINFO64", i,
0101             CVM_CAST64(CN23XX_SLI_PKT_MAC_RINFO64(i, oct->pf_num)),
0102             CVM_CAST64(octeon_read_csr64
0103                 (oct, CN23XX_SLI_PKT_MAC_RINFO64
0104                     (i, oct->pf_num))));
0105     }
0106 
0107     /*In cn23xx_setup_global_input_regs*/
0108     for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
0109         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0110             "CN23XX_SLI_IQ_PKT_CONTROL64", i,
0111             CVM_CAST64(CN23XX_SLI_IQ_PKT_CONTROL64(i)),
0112             CVM_CAST64(octeon_read_csr64
0113                 (oct, CN23XX_SLI_IQ_PKT_CONTROL64(i))));
0114     }
0115 
0116     /*In cn23xx_setup_global_output_regs*/
0117     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
0118         "CN23XX_SLI_OQ_WMARK", CVM_CAST64(CN23XX_SLI_OQ_WMARK),
0119         CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_OQ_WMARK)));
0120 
0121     for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
0122         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0123             "CN23XX_SLI_OQ_PKT_CONTROL", i,
0124             CVM_CAST64(CN23XX_SLI_OQ_PKT_CONTROL(i)),
0125             CVM_CAST64(octeon_read_csr(
0126                 oct, CN23XX_SLI_OQ_PKT_CONTROL(i))));
0127         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0128             "CN23XX_SLI_OQ_PKT_INT_LEVELS", i,
0129             CVM_CAST64(CN23XX_SLI_OQ_PKT_INT_LEVELS(i)),
0130             CVM_CAST64(octeon_read_csr64(
0131                 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(i))));
0132     }
0133 
0134     /*In cn23xx_enable_interrupt and cn23xx_disable_interrupt*/
0135     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
0136         "cn23xx->intr_enb_reg64",
0137         CVM_CAST64((long)(cn23xx->intr_enb_reg64)),
0138         CVM_CAST64(readq(cn23xx->intr_enb_reg64)));
0139 
0140     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
0141         "cn23xx->intr_sum_reg64",
0142         CVM_CAST64((long)(cn23xx->intr_sum_reg64)),
0143         CVM_CAST64(readq(cn23xx->intr_sum_reg64)));
0144 
0145     /*In cn23xx_setup_iq_regs*/
0146     for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
0147         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0148             "CN23XX_SLI_IQ_BASE_ADDR64", i,
0149             CVM_CAST64(CN23XX_SLI_IQ_BASE_ADDR64(i)),
0150             CVM_CAST64(octeon_read_csr64(
0151                 oct, CN23XX_SLI_IQ_BASE_ADDR64(i))));
0152         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0153             "CN23XX_SLI_IQ_SIZE", i,
0154             CVM_CAST64(CN23XX_SLI_IQ_SIZE(i)),
0155             CVM_CAST64(octeon_read_csr
0156                 (oct, CN23XX_SLI_IQ_SIZE(i))));
0157         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0158             "CN23XX_SLI_IQ_DOORBELL", i,
0159             CVM_CAST64(CN23XX_SLI_IQ_DOORBELL(i)),
0160             CVM_CAST64(octeon_read_csr64(
0161                 oct, CN23XX_SLI_IQ_DOORBELL(i))));
0162         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0163             "CN23XX_SLI_IQ_INSTR_COUNT64", i,
0164             CVM_CAST64(CN23XX_SLI_IQ_INSTR_COUNT64(i)),
0165             CVM_CAST64(octeon_read_csr64(
0166                 oct, CN23XX_SLI_IQ_INSTR_COUNT64(i))));
0167     }
0168 
0169     /*In cn23xx_setup_oq_regs*/
0170     for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
0171         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0172             "CN23XX_SLI_OQ_BASE_ADDR64", i,
0173             CVM_CAST64(CN23XX_SLI_OQ_BASE_ADDR64(i)),
0174             CVM_CAST64(octeon_read_csr64(
0175                 oct, CN23XX_SLI_OQ_BASE_ADDR64(i))));
0176         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0177             "CN23XX_SLI_OQ_SIZE", i,
0178             CVM_CAST64(CN23XX_SLI_OQ_SIZE(i)),
0179             CVM_CAST64(octeon_read_csr
0180                 (oct, CN23XX_SLI_OQ_SIZE(i))));
0181         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0182             "CN23XX_SLI_OQ_BUFF_INFO_SIZE", i,
0183             CVM_CAST64(CN23XX_SLI_OQ_BUFF_INFO_SIZE(i)),
0184             CVM_CAST64(octeon_read_csr(
0185                 oct, CN23XX_SLI_OQ_BUFF_INFO_SIZE(i))));
0186         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0187             "CN23XX_SLI_OQ_PKTS_SENT", i,
0188             CVM_CAST64(CN23XX_SLI_OQ_PKTS_SENT(i)),
0189             CVM_CAST64(octeon_read_csr64(
0190                 oct, CN23XX_SLI_OQ_PKTS_SENT(i))));
0191         dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
0192             "CN23XX_SLI_OQ_PKTS_CREDIT", i,
0193             CVM_CAST64(CN23XX_SLI_OQ_PKTS_CREDIT(i)),
0194             CVM_CAST64(octeon_read_csr64(
0195                 oct, CN23XX_SLI_OQ_PKTS_CREDIT(i))));
0196     }
0197 
0198     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
0199         "CN23XX_SLI_PKT_TIME_INT",
0200         CVM_CAST64(CN23XX_SLI_PKT_TIME_INT),
0201         CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_TIME_INT)));
0202     dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
0203         "CN23XX_SLI_PKT_CNT_INT",
0204         CVM_CAST64(CN23XX_SLI_PKT_CNT_INT),
0205         CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_CNT_INT)));
0206 }
0207 
0208 static int cn23xx_pf_soft_reset(struct octeon_device *oct)
0209 {
0210     octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF);
0211 
0212     dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: BIST enabled for CN23XX soft reset\n",
0213         oct->octeon_id);
0214 
0215     octeon_write_csr64(oct, CN23XX_SLI_SCRATCH1, 0x1234ULL);
0216 
0217     /* Initiate chip-wide soft reset */
0218     lio_pci_readq(oct, CN23XX_RST_SOFT_RST);
0219     lio_pci_writeq(oct, 1, CN23XX_RST_SOFT_RST);
0220 
0221     /* Wait for 100ms as Octeon resets. */
0222     mdelay(100);
0223 
0224     if (octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1)) {
0225         dev_err(&oct->pci_dev->dev, "OCTEON[%d]: Soft reset failed\n",
0226             oct->octeon_id);
0227         return 1;
0228     }
0229 
0230     dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: Reset completed\n",
0231         oct->octeon_id);
0232 
0233     /* restore the  reset value*/
0234     octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF);
0235 
0236     return 0;
0237 }
0238 
0239 static void cn23xx_enable_error_reporting(struct octeon_device *oct)
0240 {
0241     u32 regval;
0242     u32 uncorrectable_err_mask, corrtable_err_status;
0243 
0244     pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval);
0245     if (regval & CN23XX_CONFIG_PCIE_DEVCTL_MASK) {
0246         uncorrectable_err_mask = 0;
0247         corrtable_err_status = 0;
0248         pci_read_config_dword(oct->pci_dev,
0249                       CN23XX_CONFIG_PCIE_UNCORRECT_ERR_MASK,
0250                       &uncorrectable_err_mask);
0251         pci_read_config_dword(oct->pci_dev,
0252                       CN23XX_CONFIG_PCIE_CORRECT_ERR_STATUS,
0253                       &corrtable_err_status);
0254         dev_err(&oct->pci_dev->dev, "PCI-E Fatal error detected;\n"
0255                  "\tdev_ctl_status_reg = 0x%08x\n"
0256                  "\tuncorrectable_error_mask_reg = 0x%08x\n"
0257                  "\tcorrectable_error_status_reg = 0x%08x\n",
0258                 regval, uncorrectable_err_mask,
0259                 corrtable_err_status);
0260     }
0261 
0262     regval |= 0xf; /* Enable Link error reporting */
0263 
0264     dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: Enabling PCI-E error reporting..\n",
0265         oct->octeon_id);
0266     pci_write_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, regval);
0267 }
0268 
0269 static u32 cn23xx_coprocessor_clock(struct octeon_device *oct)
0270 {
0271     /* Bits 29:24 of RST_BOOT[PNR_MUL] holds the ref.clock MULTIPLIER
0272      * for SLI.
0273      */
0274 
0275     /* TBD: get the info in Hand-shake */
0276     return (((lio_pci_readq(oct, CN23XX_RST_BOOT) >> 24) & 0x3f) * 50);
0277 }
0278 
0279 u32 cn23xx_pf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us)
0280 {
0281     /* This gives the SLI clock per microsec */
0282     u32 oqticks_per_us = cn23xx_coprocessor_clock(oct);
0283 
0284     oct->pfvf_hsword.coproc_tics_per_us = oqticks_per_us;
0285 
0286     /* This gives the clock cycles per millisecond */
0287     oqticks_per_us *= 1000;
0288 
0289     /* This gives the oq ticks (1024 core clock cycles) per millisecond */
0290     oqticks_per_us /= 1024;
0291 
0292     /* time_intr is in microseconds. The next 2 steps gives the oq ticks
0293      *  corressponding to time_intr.
0294      */
0295     oqticks_per_us *= time_intr_in_us;
0296     oqticks_per_us /= 1000;
0297 
0298     return oqticks_per_us;
0299 }
0300 
0301 static void cn23xx_setup_global_mac_regs(struct octeon_device *oct)
0302 {
0303     u16 mac_no = oct->pcie_port;
0304     u16 pf_num = oct->pf_num;
0305     u64 reg_val;
0306     u64 temp;
0307 
0308     /* programming SRN and TRS for each MAC(0..3)  */
0309 
0310     dev_dbg(&oct->pci_dev->dev, "%s:Using pcie port %d\n",
0311         __func__, mac_no);
0312     /* By default, mapping all 64 IOQs to  a single MACs */
0313 
0314     reg_val =
0315         octeon_read_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num));
0316 
0317     if (oct->rev_id == OCTEON_CN23XX_REV_1_1) {
0318         /* setting SRN <6:0>  */
0319         reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF_PASS_1_1;
0320     } else {
0321         /* setting SRN <6:0>  */
0322         reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF;
0323     }
0324 
0325     /* setting TRS <23:16> */
0326     reg_val = reg_val |
0327           (oct->sriov_info.trs << CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS);
0328     /* setting RPVF <39:32> */
0329     temp = oct->sriov_info.rings_per_vf & 0xff;
0330     reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS);
0331 
0332     /* setting NVFS <55:48> */
0333     temp = oct->sriov_info.max_vfs & 0xff;
0334     reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS);
0335 
0336     /* write these settings to MAC register */
0337     octeon_write_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num),
0338                reg_val);
0339 
0340     dev_dbg(&oct->pci_dev->dev, "SLI_PKT_MAC(%d)_PF(%d)_RINFO : 0x%016llx\n",
0341         mac_no, pf_num, (u64)octeon_read_csr64
0342         (oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num)));
0343 }
0344 
0345 static int cn23xx_reset_io_queues(struct octeon_device *oct)
0346 {
0347     int ret_val = 0;
0348     u64 d64;
0349     u32 q_no, srn, ern;
0350     u32 loop = 1000;
0351 
0352     srn = oct->sriov_info.pf_srn;
0353     ern = srn + oct->sriov_info.num_pf_rings;
0354 
0355     /*As per HRM reg description, s/w cant write 0 to ENB. */
0356     /*to make the queue off, need to set the RST bit. */
0357 
0358     /* Reset the Enable bit for all the 64 IQs.  */
0359     for (q_no = srn; q_no < ern; q_no++) {
0360         /* set RST bit to 1. This bit applies to both IQ and OQ */
0361         d64 = octeon_read_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
0362         d64 = d64 | CN23XX_PKT_INPUT_CTL_RST;
0363         octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), d64);
0364     }
0365 
0366     /*wait until the RST bit is clear or the RST and quite bits are set*/
0367     for (q_no = srn; q_no < ern; q_no++) {
0368         u64 reg_val = octeon_read_csr64(oct,
0369                     CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
0370         while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) &&
0371                !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) &&
0372                loop--) {
0373             WRITE_ONCE(reg_val, octeon_read_csr64(
0374                 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)));
0375         }
0376         if (!loop) {
0377             dev_err(&oct->pci_dev->dev,
0378                 "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
0379                 q_no);
0380             return -1;
0381         }
0382         WRITE_ONCE(reg_val, READ_ONCE(reg_val) &
0383             ~CN23XX_PKT_INPUT_CTL_RST);
0384         octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
0385                    READ_ONCE(reg_val));
0386 
0387         WRITE_ONCE(reg_val, octeon_read_csr64(
0388                oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)));
0389         if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) {
0390             dev_err(&oct->pci_dev->dev,
0391                 "clearing the reset failed for qno: %u\n",
0392                 q_no);
0393             ret_val = -1;
0394         }
0395     }
0396 
0397     return ret_val;
0398 }
0399 
0400 static int cn23xx_pf_setup_global_input_regs(struct octeon_device *oct)
0401 {
0402     struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
0403     struct octeon_instr_queue *iq;
0404     u64 intr_threshold, reg_val;
0405     u32 q_no, ern, srn;
0406     u64 pf_num;
0407     u64 vf_num;
0408 
0409     pf_num = oct->pf_num;
0410 
0411     srn = oct->sriov_info.pf_srn;
0412     ern = srn + oct->sriov_info.num_pf_rings;
0413 
0414     if (cn23xx_reset_io_queues(oct))
0415         return -1;
0416 
0417     /** Set the MAC_NUM and PVF_NUM in IQ_PKT_CONTROL reg
0418      * for all queues.Only PF can set these bits.
0419      * bits 29:30 indicate the MAC num.
0420      * bits 32:47 indicate the PVF num.
0421      */
0422     for (q_no = 0; q_no < ern; q_no++) {
0423         reg_val = (u64)oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;
0424 
0425         /* for VF assigned queues. */
0426         if (q_no < oct->sriov_info.pf_srn) {
0427             vf_num = q_no / oct->sriov_info.rings_per_vf;
0428             vf_num += 1; /* VF1, VF2,........ */
0429         } else {
0430             vf_num = 0;
0431         }
0432 
0433         reg_val |= vf_num << CN23XX_PKT_INPUT_CTL_VF_NUM_POS;
0434         reg_val |= pf_num << CN23XX_PKT_INPUT_CTL_PF_NUM_POS;
0435 
0436         octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
0437                    reg_val);
0438     }
0439 
0440     /* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
0441      * pf queues
0442      */
0443     for (q_no = srn; q_no < ern; q_no++) {
0444         void __iomem *inst_cnt_reg;
0445 
0446         iq = oct->instr_queue[q_no];
0447         if (iq)
0448             inst_cnt_reg = iq->inst_cnt_reg;
0449         else
0450             inst_cnt_reg = (u8 *)oct->mmio[0].hw_addr +
0451                        CN23XX_SLI_IQ_INSTR_COUNT64(q_no);
0452 
0453         reg_val =
0454             octeon_read_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
0455 
0456         reg_val |= CN23XX_PKT_INPUT_CTL_MASK;
0457 
0458         octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
0459                    reg_val);
0460 
0461         /* Set WMARK level for triggering PI_INT */
0462         /* intr_threshold = CN23XX_DEF_IQ_INTR_THRESHOLD & */
0463         intr_threshold = CFG_GET_IQ_INTR_PKT(cn23xx->conf) &
0464                  CN23XX_PKT_IN_DONE_WMARK_MASK;
0465 
0466         writeq((readq(inst_cnt_reg) &
0467             ~(CN23XX_PKT_IN_DONE_WMARK_MASK <<
0468               CN23XX_PKT_IN_DONE_WMARK_BIT_POS)) |
0469                (intr_threshold << CN23XX_PKT_IN_DONE_WMARK_BIT_POS),
0470                inst_cnt_reg);
0471     }
0472     return 0;
0473 }
0474 
0475 static void cn23xx_pf_setup_global_output_regs(struct octeon_device *oct)
0476 {
0477     u32 reg_val;
0478     u32 q_no, ern, srn;
0479     u64 time_threshold;
0480 
0481     struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
0482 
0483     srn = oct->sriov_info.pf_srn;
0484     ern = srn + oct->sriov_info.num_pf_rings;
0485 
0486     if (CFG_GET_IS_SLI_BP_ON(cn23xx->conf)) {
0487         octeon_write_csr64(oct, CN23XX_SLI_OQ_WMARK, 32);
0488     } else {
0489         /** Set Output queue watermark to 0 to disable backpressure */
0490         octeon_write_csr64(oct, CN23XX_SLI_OQ_WMARK, 0);
0491     }
0492 
0493     for (q_no = srn; q_no < ern; q_no++) {
0494         reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
0495 
0496         /* clear IPTR */
0497         reg_val &= ~CN23XX_PKT_OUTPUT_CTL_IPTR;
0498 
0499         /* set DPTR */
0500         reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR;
0501 
0502         /* reset BMODE */
0503         reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
0504 
0505         /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
0506          * for Output Queue ScatterList
0507          * reset ROR_P, NSR_P
0508          */
0509         reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
0510         reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
0511 
0512 #ifdef __LITTLE_ENDIAN_BITFIELD
0513         reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
0514 #else
0515         reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
0516 #endif
0517         /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
0518          * for Output Queue Data
0519          * reset ROR, NSR
0520          */
0521         reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
0522         reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
0523         /* set the ES bit */
0524         reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
0525 
0526         /* write all the selected settings */
0527         octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no), reg_val);
0528 
0529         /* Enabling these interrupt in oct->fn_list.enable_interrupt()
0530          * routine which called after IOQ init.
0531          * Set up interrupt packet and time thresholds
0532          * for all the OQs
0533          */
0534         time_threshold = cn23xx_pf_get_oq_ticks(
0535             oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf));
0536 
0537         octeon_write_csr64(oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no),
0538                    (CFG_GET_OQ_INTR_PKT(cn23xx->conf) |
0539                     (time_threshold << 32)));
0540     }
0541 
0542     /** Setting the water mark level for pko back pressure **/
0543     writeq(0x40, (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_WMARK);
0544 
0545     /** Disabling setting OQs in reset when ring has no dorebells
0546      * enabling this will cause of head of line blocking
0547      */
0548     /* Do it only for pass1.1. and pass1.2 */
0549     if ((oct->rev_id == OCTEON_CN23XX_REV_1_0) ||
0550         (oct->rev_id == OCTEON_CN23XX_REV_1_1))
0551         writeq(readq((u8 *)oct->mmio[0].hw_addr +
0552                      CN23XX_SLI_GBL_CONTROL) | 0x2,
0553                (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_GBL_CONTROL);
0554 
0555     /** Enable channel-level backpressure */
0556     if (oct->pf_num)
0557         writeq(0xffffffffffffffffULL,
0558                (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OUT_BP_EN2_W1S);
0559     else
0560         writeq(0xffffffffffffffffULL,
0561                (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OUT_BP_EN_W1S);
0562 }
0563 
0564 static int cn23xx_setup_pf_device_regs(struct octeon_device *oct)
0565 {
0566     cn23xx_enable_error_reporting(oct);
0567 
0568     /* program the MAC(0..3)_RINFO before setting up input/output regs */
0569     cn23xx_setup_global_mac_regs(oct);
0570 
0571     if (cn23xx_pf_setup_global_input_regs(oct))
0572         return -1;
0573 
0574     cn23xx_pf_setup_global_output_regs(oct);
0575 
0576     /* Default error timeout value should be 0x200000 to avoid host hang
0577      * when reads invalid register
0578      */
0579     octeon_write_csr64(oct, CN23XX_SLI_WINDOW_CTL,
0580                CN23XX_SLI_WINDOW_CTL_DEFAULT);
0581 
0582     /* set SLI_PKT_IN_JABBER to handle large VXLAN packets */
0583     octeon_write_csr64(oct, CN23XX_SLI_PKT_IN_JABBER, CN23XX_INPUT_JABBER);
0584     return 0;
0585 }
0586 
0587 static void cn23xx_setup_iq_regs(struct octeon_device *oct, u32 iq_no)
0588 {
0589     struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
0590     u64 pkt_in_done;
0591 
0592     iq_no += oct->sriov_info.pf_srn;
0593 
0594     /* Write the start of the input queue's ring and its size  */
0595     octeon_write_csr64(oct, CN23XX_SLI_IQ_BASE_ADDR64(iq_no),
0596                iq->base_addr_dma);
0597     octeon_write_csr(oct, CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count);
0598 
0599     /* Remember the doorbell & instruction count register addr
0600      * for this queue
0601      */
0602     iq->doorbell_reg =
0603         (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_IQ_DOORBELL(iq_no);
0604     iq->inst_cnt_reg =
0605         (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_IQ_INSTR_COUNT64(iq_no);
0606     dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",
0607         iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
0608 
0609     /* Store the current instruction counter (used in flush_iq
0610      * calculation)
0611      */
0612     pkt_in_done = readq(iq->inst_cnt_reg);
0613 
0614     if (oct->msix_on) {
0615         /* Set CINT_ENB to enable IQ interrupt   */
0616         writeq((pkt_in_done | CN23XX_INTR_CINT_ENB),
0617                iq->inst_cnt_reg);
0618     } else {
0619         /* Clear the count by writing back what we read, but don't
0620          * enable interrupts
0621          */
0622         writeq(pkt_in_done, iq->inst_cnt_reg);
0623     }
0624 
0625     iq->reset_instr_cnt = 0;
0626 }
0627 
0628 static void cn23xx_setup_oq_regs(struct octeon_device *oct, u32 oq_no)
0629 {
0630     u32 reg_val;
0631     struct octeon_droq *droq = oct->droq[oq_no];
0632     struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
0633     u64 time_threshold;
0634     u64 cnt_threshold;
0635 
0636     oq_no += oct->sriov_info.pf_srn;
0637 
0638     octeon_write_csr64(oct, CN23XX_SLI_OQ_BASE_ADDR64(oq_no),
0639                droq->desc_ring_dma);
0640     octeon_write_csr(oct, CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count);
0641 
0642     octeon_write_csr(oct, CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no),
0643              droq->buffer_size);
0644 
0645     /* Get the mapped address of the pkt_sent and pkts_credit regs */
0646     droq->pkts_sent_reg =
0647         (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_PKTS_SENT(oq_no);
0648     droq->pkts_credit_reg =
0649         (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_PKTS_CREDIT(oq_no);
0650 
0651     if (!oct->msix_on) {
0652         /* Enable this output queue to generate Packet Timer Interrupt
0653          */
0654         reg_val =
0655             octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no));
0656         reg_val |= CN23XX_PKT_OUTPUT_CTL_TENB;
0657         octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no),
0658                  reg_val);
0659 
0660         /* Enable this output queue to generate Packet Count Interrupt
0661          */
0662         reg_val =
0663             octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no));
0664         reg_val |= CN23XX_PKT_OUTPUT_CTL_CENB;
0665         octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no),
0666                  reg_val);
0667     } else {
0668         time_threshold = cn23xx_pf_get_oq_ticks(
0669             oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf));
0670         cnt_threshold = (u32)CFG_GET_OQ_INTR_PKT(cn23xx->conf);
0671 
0672         octeon_write_csr64(
0673             oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(oq_no),
0674             ((time_threshold << 32 | cnt_threshold)));
0675     }
0676 }
0677 
0678 static void cn23xx_pf_mbox_thread(struct work_struct *work)
0679 {
0680     struct cavium_wk *wk = (struct cavium_wk *)work;
0681     struct octeon_mbox *mbox = (struct octeon_mbox *)wk->ctxptr;
0682     struct octeon_device *oct = mbox->oct_dev;
0683     u64 mbox_int_val, val64;
0684     u32 q_no, i;
0685 
0686     if (oct->rev_id < OCTEON_CN23XX_REV_1_1) {
0687         /*read and clear by writing 1*/
0688         mbox_int_val = readq(mbox->mbox_int_reg);
0689         writeq(mbox_int_val, mbox->mbox_int_reg);
0690 
0691         for (i = 0; i < oct->sriov_info.num_vfs_alloced; i++) {
0692             q_no = i * oct->sriov_info.rings_per_vf;
0693 
0694             val64 = readq(oct->mbox[q_no]->mbox_write_reg);
0695 
0696             if (val64 && (val64 != OCTEON_PFVFACK)) {
0697                 if (octeon_mbox_read(oct->mbox[q_no]))
0698                     octeon_mbox_process_message(
0699                         oct->mbox[q_no]);
0700             }
0701         }
0702 
0703         schedule_delayed_work(&wk->work, msecs_to_jiffies(10));
0704     } else {
0705         octeon_mbox_process_message(mbox);
0706     }
0707 }
0708 
0709 static int cn23xx_setup_pf_mbox(struct octeon_device *oct)
0710 {
0711     struct octeon_mbox *mbox = NULL;
0712     u16 mac_no = oct->pcie_port;
0713     u16 pf_num = oct->pf_num;
0714     u32 q_no, i;
0715 
0716     if (!oct->sriov_info.max_vfs)
0717         return 0;
0718 
0719     for (i = 0; i < oct->sriov_info.max_vfs; i++) {
0720         q_no = i * oct->sriov_info.rings_per_vf;
0721 
0722         mbox = vmalloc(sizeof(*mbox));
0723         if (!mbox)
0724             goto free_mbox;
0725 
0726         memset(mbox, 0, sizeof(struct octeon_mbox));
0727 
0728         spin_lock_init(&mbox->lock);
0729 
0730         mbox->oct_dev = oct;
0731 
0732         mbox->q_no = q_no;
0733 
0734         mbox->state = OCTEON_MBOX_STATE_IDLE;
0735 
0736         /* PF mbox interrupt reg */
0737         mbox->mbox_int_reg = (u8 *)oct->mmio[0].hw_addr +
0738                      CN23XX_SLI_MAC_PF_MBOX_INT(mac_no, pf_num);
0739 
0740         /* PF writes into SIG0 reg */
0741         mbox->mbox_write_reg = (u8 *)oct->mmio[0].hw_addr +
0742                        CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q_no, 0);
0743 
0744         /* PF reads from SIG1 reg */
0745         mbox->mbox_read_reg = (u8 *)oct->mmio[0].hw_addr +
0746                       CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q_no, 1);
0747 
0748         /*Mail Box Thread creation*/
0749         INIT_DELAYED_WORK(&mbox->mbox_poll_wk.work,
0750                   cn23xx_pf_mbox_thread);
0751         mbox->mbox_poll_wk.ctxptr = (void *)mbox;
0752 
0753         oct->mbox[q_no] = mbox;
0754 
0755         writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
0756     }
0757 
0758     if (oct->rev_id < OCTEON_CN23XX_REV_1_1)
0759         schedule_delayed_work(&oct->mbox[0]->mbox_poll_wk.work,
0760                       msecs_to_jiffies(0));
0761 
0762     return 0;
0763 
0764 free_mbox:
0765     while (i) {
0766         i--;
0767         vfree(oct->mbox[i]);
0768     }
0769 
0770     return 1;
0771 }
0772 
0773 static int cn23xx_free_pf_mbox(struct octeon_device *oct)
0774 {
0775     u32 q_no, i;
0776 
0777     if (!oct->sriov_info.max_vfs)
0778         return 0;
0779 
0780     for (i = 0; i < oct->sriov_info.max_vfs; i++) {
0781         q_no = i * oct->sriov_info.rings_per_vf;
0782         cancel_delayed_work_sync(
0783             &oct->mbox[q_no]->mbox_poll_wk.work);
0784         vfree(oct->mbox[q_no]);
0785     }
0786 
0787     return 0;
0788 }
0789 
0790 static int cn23xx_enable_io_queues(struct octeon_device *oct)
0791 {
0792     u64 reg_val;
0793     u32 srn, ern, q_no;
0794     u32 loop = 1000;
0795 
0796     srn = oct->sriov_info.pf_srn;
0797     ern = srn + oct->num_iqs;
0798 
0799     for (q_no = srn; q_no < ern; q_no++) {
0800         /* set the corresponding IQ IS_64B bit */
0801         if (oct->io_qmask.iq64B & BIT_ULL(q_no - srn)) {
0802             reg_val = octeon_read_csr64(
0803                 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
0804             reg_val = reg_val | CN23XX_PKT_INPUT_CTL_IS_64B;
0805             octeon_write_csr64(
0806                 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
0807         }
0808 
0809         /* set the corresponding IQ ENB bit */
0810         if (oct->io_qmask.iq & BIT_ULL(q_no - srn)) {
0811             /* IOQs are in reset by default in PEM2 mode,
0812              * clearing reset bit
0813              */
0814             reg_val = octeon_read_csr64(
0815                 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
0816 
0817             if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
0818                 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
0819                        !(reg_val &
0820                      CN23XX_PKT_INPUT_CTL_QUIET) &&
0821                        --loop) {
0822                     reg_val = octeon_read_csr64(
0823                         oct,
0824                         CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
0825                 }
0826                 if (!loop) {
0827                     dev_err(&oct->pci_dev->dev,
0828                         "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
0829                         q_no);
0830                     return -1;
0831                 }
0832                 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
0833                 octeon_write_csr64(
0834                     oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
0835                     reg_val);
0836 
0837                 reg_val = octeon_read_csr64(
0838                     oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
0839                 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
0840                     dev_err(&oct->pci_dev->dev,
0841                         "clearing the reset failed for qno: %u\n",
0842                         q_no);
0843                     return -1;
0844                 }
0845             }
0846             reg_val = octeon_read_csr64(
0847                 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
0848             reg_val = reg_val | CN23XX_PKT_INPUT_CTL_RING_ENB;
0849             octeon_write_csr64(
0850                 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
0851         }
0852     }
0853     for (q_no = srn; q_no < ern; q_no++) {
0854         u32 reg_val;
0855         /* set the corresponding OQ ENB bit */
0856         if (oct->io_qmask.oq & BIT_ULL(q_no - srn)) {
0857             reg_val = octeon_read_csr(
0858                 oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
0859             reg_val = reg_val | CN23XX_PKT_OUTPUT_CTL_RING_ENB;
0860             octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no),
0861                      reg_val);
0862         }
0863     }
0864     return 0;
0865 }
0866 
0867 static void cn23xx_disable_io_queues(struct octeon_device *oct)
0868 {
0869     int q_no, loop;
0870     u64 d64;
0871     u32 d32;
0872     u32 srn, ern;
0873 
0874     srn = oct->sriov_info.pf_srn;
0875     ern = srn + oct->num_iqs;
0876 
0877     /*** Disable Input Queues. ***/
0878     for (q_no = srn; q_no < ern; q_no++) {
0879         loop = HZ;
0880 
0881         /* start the Reset for a particular ring */
0882         WRITE_ONCE(d64, octeon_read_csr64(
0883                oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)));
0884         WRITE_ONCE(d64, READ_ONCE(d64) &
0885                     (~(CN23XX_PKT_INPUT_CTL_RING_ENB)));
0886         WRITE_ONCE(d64, READ_ONCE(d64) | CN23XX_PKT_INPUT_CTL_RST);
0887         octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
0888                    READ_ONCE(d64));
0889 
0890         /* Wait until hardware indicates that the particular IQ
0891          * is out of reset.
0892          */
0893         WRITE_ONCE(d64, octeon_read_csr64(
0894                     oct, CN23XX_SLI_PKT_IOQ_RING_RST));
0895         while (!(READ_ONCE(d64) & BIT_ULL(q_no)) && loop--) {
0896             WRITE_ONCE(d64, octeon_read_csr64(
0897                     oct, CN23XX_SLI_PKT_IOQ_RING_RST));
0898             schedule_timeout_uninterruptible(1);
0899         }
0900 
0901         /* Reset the doorbell register for this Input Queue. */
0902         octeon_write_csr(oct, CN23XX_SLI_IQ_DOORBELL(q_no), 0xFFFFFFFF);
0903         while (octeon_read_csr64(oct, CN23XX_SLI_IQ_DOORBELL(q_no)) &&
0904                loop--) {
0905             schedule_timeout_uninterruptible(1);
0906         }
0907     }
0908 
0909     /*** Disable Output Queues. ***/
0910     for (q_no = srn; q_no < ern; q_no++) {
0911         loop = HZ;
0912 
0913         /* Wait until hardware indicates that the particular IQ
0914          * is out of reset.It given that SLI_PKT_RING_RST is
0915          * common for both IQs and OQs
0916          */
0917         WRITE_ONCE(d64, octeon_read_csr64(
0918                     oct, CN23XX_SLI_PKT_IOQ_RING_RST));
0919         while (!(READ_ONCE(d64) & BIT_ULL(q_no)) && loop--) {
0920             WRITE_ONCE(d64, octeon_read_csr64(
0921                     oct, CN23XX_SLI_PKT_IOQ_RING_RST));
0922             schedule_timeout_uninterruptible(1);
0923         }
0924 
0925         /* Reset the doorbell register for this Output Queue. */
0926         octeon_write_csr(oct, CN23XX_SLI_OQ_PKTS_CREDIT(q_no),
0927                  0xFFFFFFFF);
0928         while (octeon_read_csr64(oct,
0929                      CN23XX_SLI_OQ_PKTS_CREDIT(q_no)) &&
0930                loop--) {
0931             schedule_timeout_uninterruptible(1);
0932         }
0933 
0934         /* clear the SLI_PKT(0..63)_CNTS[CNT] reg value */
0935         WRITE_ONCE(d32, octeon_read_csr(
0936                     oct, CN23XX_SLI_OQ_PKTS_SENT(q_no)));
0937         octeon_write_csr(oct, CN23XX_SLI_OQ_PKTS_SENT(q_no),
0938                  READ_ONCE(d32));
0939     }
0940 }
0941 
0942 static u64 cn23xx_pf_msix_interrupt_handler(void *dev)
0943 {
0944     struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev;
0945     struct octeon_device *oct = ioq_vector->oct_dev;
0946     u64 pkts_sent;
0947     u64 ret = 0;
0948     struct octeon_droq *droq = oct->droq[ioq_vector->droq_index];
0949 
0950     dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct);
0951 
0952     if (!droq) {
0953         dev_err(&oct->pci_dev->dev, "23XX bringup FIXME: oct pfnum:%d ioq_vector->ioq_num :%d droq is NULL\n",
0954             oct->pf_num, ioq_vector->ioq_num);
0955         return 0;
0956     }
0957 
0958     pkts_sent = readq(droq->pkts_sent_reg);
0959 
0960     /* If our device has interrupted, then proceed. Also check
0961      * for all f's if interrupt was triggered on an error
0962      * and the PCI read fails.
0963      */
0964     if (!pkts_sent || (pkts_sent == 0xFFFFFFFFFFFFFFFFULL))
0965         return ret;
0966 
0967     /* Write count reg in sli_pkt_cnts to clear these int.*/
0968     if ((pkts_sent & CN23XX_INTR_PO_INT) ||
0969         (pkts_sent & CN23XX_INTR_PI_INT)) {
0970         if (pkts_sent & CN23XX_INTR_PO_INT)
0971             ret |= MSIX_PO_INT;
0972     }
0973 
0974     if (pkts_sent & CN23XX_INTR_PI_INT)
0975         /* We will clear the count when we update the read_index. */
0976         ret |= MSIX_PI_INT;
0977 
0978     /* Never need to handle msix mbox intr for pf. They arrive on the last
0979      * msix
0980      */
0981     return ret;
0982 }
0983 
0984 static void cn23xx_handle_pf_mbox_intr(struct octeon_device *oct)
0985 {
0986     struct delayed_work *work;
0987     u64 mbox_int_val;
0988     u32 i, q_no;
0989 
0990     mbox_int_val = readq(oct->mbox[0]->mbox_int_reg);
0991 
0992     for (i = 0; i < oct->sriov_info.num_vfs_alloced; i++) {
0993         q_no = i * oct->sriov_info.rings_per_vf;
0994 
0995         if (mbox_int_val & BIT_ULL(q_no)) {
0996             writeq(BIT_ULL(q_no),
0997                    oct->mbox[0]->mbox_int_reg);
0998             if (octeon_mbox_read(oct->mbox[q_no])) {
0999                 work = &oct->mbox[q_no]->mbox_poll_wk.work;
1000                 schedule_delayed_work(work,
1001                               msecs_to_jiffies(0));
1002             }
1003         }
1004     }
1005 }
1006 
1007 static irqreturn_t cn23xx_interrupt_handler(void *dev)
1008 {
1009     struct octeon_device *oct = (struct octeon_device *)dev;
1010     struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
1011     u64 intr64;
1012 
1013     dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct);
1014     intr64 = readq(cn23xx->intr_sum_reg64);
1015 
1016     oct->int_status = 0;
1017 
1018     if (intr64 & CN23XX_INTR_ERR)
1019         dev_err(&oct->pci_dev->dev, "OCTEON[%d]: Error Intr: 0x%016llx\n",
1020             oct->octeon_id, CVM_CAST64(intr64));
1021 
1022     /* When VFs write into MBOX_SIG2 reg,these intr is set in PF */
1023     if (intr64 & CN23XX_INTR_VF_MBOX)
1024         cn23xx_handle_pf_mbox_intr(oct);
1025 
1026     if (oct->msix_on != LIO_FLAG_MSIX_ENABLED) {
1027         if (intr64 & CN23XX_INTR_PKT_DATA)
1028             oct->int_status |= OCT_DEV_INTR_PKT_DATA;
1029     }
1030 
1031     if (intr64 & (CN23XX_INTR_DMA0_FORCE))
1032         oct->int_status |= OCT_DEV_INTR_DMA0_FORCE;
1033     if (intr64 & (CN23XX_INTR_DMA1_FORCE))
1034         oct->int_status |= OCT_DEV_INTR_DMA1_FORCE;
1035 
1036     /* Clear the current interrupts */
1037     writeq(intr64, cn23xx->intr_sum_reg64);
1038 
1039     return IRQ_HANDLED;
1040 }
1041 
1042 static void cn23xx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr,
1043                   u32 idx, int valid)
1044 {
1045     u64 bar1;
1046     u64 reg_adr;
1047 
1048     if (!valid) {
1049         reg_adr = lio_pci_readq(
1050             oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1051         WRITE_ONCE(bar1, reg_adr);
1052         lio_pci_writeq(oct, (READ_ONCE(bar1) & 0xFFFFFFFEULL),
1053                    CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1054         reg_adr = lio_pci_readq(
1055             oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1056         WRITE_ONCE(bar1, reg_adr);
1057         return;
1058     }
1059 
1060     /*  The PEM(0..3)_BAR1_INDEX(0..15)[ADDR_IDX]<23:4> stores
1061      *  bits <41:22> of the Core Addr
1062      */
1063     lio_pci_writeq(oct, (((core_addr >> 22) << 4) | PCI_BAR1_MASK),
1064                CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1065 
1066     WRITE_ONCE(bar1, lio_pci_readq(
1067            oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)));
1068 }
1069 
1070 static void cn23xx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask)
1071 {
1072     lio_pci_writeq(oct, mask,
1073                CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1074 }
1075 
1076 static u32 cn23xx_bar1_idx_read(struct octeon_device *oct, u32 idx)
1077 {
1078     return (u32)lio_pci_readq(
1079         oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1080 }
1081 
1082 /* always call with lock held */
1083 static u32 cn23xx_update_read_index(struct octeon_instr_queue *iq)
1084 {
1085     u32 new_idx;
1086     u32 last_done;
1087     u32 pkt_in_done = readl(iq->inst_cnt_reg);
1088 
1089     last_done = pkt_in_done - iq->pkt_in_done;
1090     iq->pkt_in_done = pkt_in_done;
1091 
1092     /* Modulo of the new index with the IQ size will give us
1093      * the new index.  The iq->reset_instr_cnt is always zero for
1094      * cn23xx, so no extra adjustments are needed.
1095      */
1096     new_idx = (iq->octeon_read_index +
1097            (u32)(last_done & CN23XX_PKT_IN_DONE_CNT_MASK)) %
1098           iq->max_count;
1099 
1100     return new_idx;
1101 }
1102 
1103 static void cn23xx_enable_pf_interrupt(struct octeon_device *oct, u8 intr_flag)
1104 {
1105     struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
1106     u64 intr_val = 0;
1107 
1108     /*  Divide the single write to multiple writes based on the flag. */
1109     /* Enable Interrupt */
1110     if (intr_flag == OCTEON_ALL_INTR) {
1111         writeq(cn23xx->intr_mask64, cn23xx->intr_enb_reg64);
1112     } else if (intr_flag & OCTEON_OUTPUT_INTR) {
1113         intr_val = readq(cn23xx->intr_enb_reg64);
1114         intr_val |= CN23XX_INTR_PKT_DATA;
1115         writeq(intr_val, cn23xx->intr_enb_reg64);
1116     } else if ((intr_flag & OCTEON_MBOX_INTR) &&
1117            (oct->sriov_info.max_vfs > 0)) {
1118         if (oct->rev_id >= OCTEON_CN23XX_REV_1_1) {
1119             intr_val = readq(cn23xx->intr_enb_reg64);
1120             intr_val |= CN23XX_INTR_VF_MBOX;
1121             writeq(intr_val, cn23xx->intr_enb_reg64);
1122         }
1123     }
1124 }
1125 
1126 static void cn23xx_disable_pf_interrupt(struct octeon_device *oct, u8 intr_flag)
1127 {
1128     struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
1129     u64 intr_val = 0;
1130 
1131     /* Disable Interrupts */
1132     if (intr_flag == OCTEON_ALL_INTR) {
1133         writeq(0, cn23xx->intr_enb_reg64);
1134     } else if (intr_flag & OCTEON_OUTPUT_INTR) {
1135         intr_val = readq(cn23xx->intr_enb_reg64);
1136         intr_val &= ~CN23XX_INTR_PKT_DATA;
1137         writeq(intr_val, cn23xx->intr_enb_reg64);
1138     } else if ((intr_flag & OCTEON_MBOX_INTR) &&
1139            (oct->sriov_info.max_vfs > 0)) {
1140         if (oct->rev_id >= OCTEON_CN23XX_REV_1_1) {
1141             intr_val = readq(cn23xx->intr_enb_reg64);
1142             intr_val &= ~CN23XX_INTR_VF_MBOX;
1143             writeq(intr_val, cn23xx->intr_enb_reg64);
1144         }
1145     }
1146 }
1147 
1148 static void cn23xx_get_pcie_qlmport(struct octeon_device *oct)
1149 {
1150     oct->pcie_port = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff;
1151 
1152     dev_dbg(&oct->pci_dev->dev, "OCTEON: CN23xx uses PCIE Port %d\n",
1153         oct->pcie_port);
1154 }
1155 
1156 static int cn23xx_get_pf_num(struct octeon_device *oct)
1157 {
1158     u32 fdl_bit = 0;
1159     u64 pkt0_in_ctl, d64;
1160     int pfnum, mac, trs, ret;
1161 
1162     ret = 0;
1163 
1164     /** Read Function Dependency Link reg to get the function number */
1165     if (pci_read_config_dword(oct->pci_dev, CN23XX_PCIE_SRIOV_FDL,
1166                   &fdl_bit) == 0) {
1167         oct->pf_num = ((fdl_bit >> CN23XX_PCIE_SRIOV_FDL_BIT_POS) &
1168                    CN23XX_PCIE_SRIOV_FDL_MASK);
1169     } else {
1170         ret = -EINVAL;
1171 
1172         /* Under some virtual environments, extended PCI regs are
1173          * inaccessible, in which case the above read will have failed.
1174          * In this case, read the PF number from the
1175          * SLI_PKT0_INPUT_CONTROL reg (written by f/w)
1176          */
1177         pkt0_in_ctl = octeon_read_csr64(oct,
1178                         CN23XX_SLI_IQ_PKT_CONTROL64(0));
1179         pfnum = (pkt0_in_ctl >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
1180             CN23XX_PKT_INPUT_CTL_PF_NUM_MASK;
1181         mac = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff;
1182 
1183         /* validate PF num by reading RINFO; f/w writes RINFO.trs == 1*/
1184         d64 = octeon_read_csr64(oct,
1185                     CN23XX_SLI_PKT_MAC_RINFO64(mac, pfnum));
1186         trs = (int)(d64 >> CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS) & 0xff;
1187         if (trs == 1) {
1188             dev_err(&oct->pci_dev->dev,
1189                 "OCTEON: error reading PCI cfg space pfnum, re-read %u\n",
1190                 pfnum);
1191             oct->pf_num = pfnum;
1192             ret = 0;
1193         } else {
1194             dev_err(&oct->pci_dev->dev,
1195                 "OCTEON: error reading PCI cfg space pfnum; could not ascertain PF number\n");
1196         }
1197     }
1198 
1199     return ret;
1200 }
1201 
1202 static void cn23xx_setup_reg_address(struct octeon_device *oct)
1203 {
1204     u8 __iomem *bar0_pciaddr = oct->mmio[0].hw_addr;
1205     struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
1206 
1207     oct->reg_list.pci_win_wr_addr_hi =
1208         (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_ADDR_HI);
1209     oct->reg_list.pci_win_wr_addr_lo =
1210         (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_ADDR_LO);
1211     oct->reg_list.pci_win_wr_addr =
1212         (u64 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_ADDR64);
1213 
1214     oct->reg_list.pci_win_rd_addr_hi =
1215         (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_ADDR_HI);
1216     oct->reg_list.pci_win_rd_addr_lo =
1217         (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_ADDR_LO);
1218     oct->reg_list.pci_win_rd_addr =
1219         (u64 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_ADDR64);
1220 
1221     oct->reg_list.pci_win_wr_data_hi =
1222         (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_DATA_HI);
1223     oct->reg_list.pci_win_wr_data_lo =
1224         (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_DATA_LO);
1225     oct->reg_list.pci_win_wr_data =
1226         (u64 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_DATA64);
1227 
1228     oct->reg_list.pci_win_rd_data_hi =
1229         (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_DATA_HI);
1230     oct->reg_list.pci_win_rd_data_lo =
1231         (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_DATA_LO);
1232     oct->reg_list.pci_win_rd_data =
1233         (u64 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_DATA64);
1234 
1235     cn23xx_get_pcie_qlmport(oct);
1236 
1237     cn23xx->intr_mask64 = CN23XX_INTR_MASK;
1238     if (!oct->msix_on)
1239         cn23xx->intr_mask64 |= CN23XX_INTR_PKT_TIME;
1240     if (oct->rev_id >= OCTEON_CN23XX_REV_1_1)
1241         cn23xx->intr_mask64 |= CN23XX_INTR_VF_MBOX;
1242 
1243     cn23xx->intr_sum_reg64 =
1244         bar0_pciaddr +
1245         CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);
1246     cn23xx->intr_enb_reg64 =
1247         bar0_pciaddr +
1248         CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);
1249 }
1250 
1251 int cn23xx_sriov_config(struct octeon_device *oct)
1252 {
1253     struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
1254     u32 max_rings, total_rings, max_vfs, rings_per_vf;
1255     u32 pf_srn, num_pf_rings;
1256     u32 max_possible_vfs;
1257 
1258     cn23xx->conf =
1259         (struct octeon_config *)oct_get_config_info(oct, LIO_23XX);
1260     switch (oct->rev_id) {
1261     case OCTEON_CN23XX_REV_1_0:
1262         max_rings = CN23XX_MAX_RINGS_PER_PF_PASS_1_0;
1263         max_possible_vfs = CN23XX_MAX_VFS_PER_PF_PASS_1_0;
1264         break;
1265     case OCTEON_CN23XX_REV_1_1:
1266         max_rings = CN23XX_MAX_RINGS_PER_PF_PASS_1_1;
1267         max_possible_vfs = CN23XX_MAX_VFS_PER_PF_PASS_1_1;
1268         break;
1269     default:
1270         max_rings = CN23XX_MAX_RINGS_PER_PF;
1271         max_possible_vfs = CN23XX_MAX_VFS_PER_PF;
1272         break;
1273     }
1274 
1275     if (oct->sriov_info.num_pf_rings)
1276         num_pf_rings = oct->sriov_info.num_pf_rings;
1277     else
1278         num_pf_rings = num_present_cpus();
1279 
1280 #ifdef CONFIG_PCI_IOV
1281     max_vfs = min_t(u32,
1282             (max_rings - num_pf_rings), max_possible_vfs);
1283     rings_per_vf = 1;
1284 #else
1285     max_vfs = 0;
1286     rings_per_vf = 0;
1287 #endif
1288 
1289     total_rings = num_pf_rings + max_vfs;
1290 
1291     /* the first ring of the pf */
1292     pf_srn = total_rings - num_pf_rings;
1293 
1294     oct->sriov_info.trs = total_rings;
1295     oct->sriov_info.max_vfs = max_vfs;
1296     oct->sriov_info.rings_per_vf = rings_per_vf;
1297     oct->sriov_info.pf_srn = pf_srn;
1298     oct->sriov_info.num_pf_rings = num_pf_rings;
1299     dev_notice(&oct->pci_dev->dev, "trs:%d max_vfs:%d rings_per_vf:%d pf_srn:%d num_pf_rings:%d\n",
1300            oct->sriov_info.trs, oct->sriov_info.max_vfs,
1301            oct->sriov_info.rings_per_vf, oct->sriov_info.pf_srn,
1302            oct->sriov_info.num_pf_rings);
1303 
1304     oct->sriov_info.sriov_enabled = 0;
1305 
1306     return 0;
1307 }
1308 
1309 int setup_cn23xx_octeon_pf_device(struct octeon_device *oct)
1310 {
1311     u32 data32;
1312     u64 BAR0, BAR1;
1313 
1314     pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_0, &data32);
1315     BAR0 = (u64)(data32 & ~0xf);
1316     pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_1, &data32);
1317     BAR0 |= ((u64)data32 << 32);
1318     pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_2, &data32);
1319     BAR1 = (u64)(data32 & ~0xf);
1320     pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_3, &data32);
1321     BAR1 |= ((u64)data32 << 32);
1322 
1323     if (!BAR0 || !BAR1) {
1324         if (!BAR0)
1325             dev_err(&oct->pci_dev->dev, "device BAR0 unassigned\n");
1326         if (!BAR1)
1327             dev_err(&oct->pci_dev->dev, "device BAR1 unassigned\n");
1328         return 1;
1329     }
1330 
1331     if (octeon_map_pci_barx(oct, 0, 0))
1332         return 1;
1333 
1334     if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) {
1335         dev_err(&oct->pci_dev->dev, "%s CN23XX BAR1 map failed\n",
1336             __func__);
1337         octeon_unmap_pci_barx(oct, 0);
1338         return 1;
1339     }
1340 
1341     if (cn23xx_get_pf_num(oct) != 0)
1342         return 1;
1343 
1344     if (cn23xx_sriov_config(oct)) {
1345         octeon_unmap_pci_barx(oct, 0);
1346         octeon_unmap_pci_barx(oct, 1);
1347         return 1;
1348     }
1349 
1350     octeon_write_csr64(oct, CN23XX_SLI_MAC_CREDIT_CNT, 0x3F802080802080ULL);
1351 
1352     oct->fn_list.setup_iq_regs = cn23xx_setup_iq_regs;
1353     oct->fn_list.setup_oq_regs = cn23xx_setup_oq_regs;
1354     oct->fn_list.setup_mbox = cn23xx_setup_pf_mbox;
1355     oct->fn_list.free_mbox = cn23xx_free_pf_mbox;
1356 
1357     oct->fn_list.process_interrupt_regs = cn23xx_interrupt_handler;
1358     oct->fn_list.msix_interrupt_handler = cn23xx_pf_msix_interrupt_handler;
1359 
1360     oct->fn_list.soft_reset = cn23xx_pf_soft_reset;
1361     oct->fn_list.setup_device_regs = cn23xx_setup_pf_device_regs;
1362     oct->fn_list.update_iq_read_idx = cn23xx_update_read_index;
1363 
1364     oct->fn_list.bar1_idx_setup = cn23xx_bar1_idx_setup;
1365     oct->fn_list.bar1_idx_write = cn23xx_bar1_idx_write;
1366     oct->fn_list.bar1_idx_read = cn23xx_bar1_idx_read;
1367 
1368     oct->fn_list.enable_interrupt = cn23xx_enable_pf_interrupt;
1369     oct->fn_list.disable_interrupt = cn23xx_disable_pf_interrupt;
1370 
1371     oct->fn_list.enable_io_queues = cn23xx_enable_io_queues;
1372     oct->fn_list.disable_io_queues = cn23xx_disable_io_queues;
1373 
1374     cn23xx_setup_reg_address(oct);
1375 
1376     oct->coproc_clock_rate = 1000000ULL * cn23xx_coprocessor_clock(oct);
1377 
1378     return 0;
1379 }
1380 
1381 int validate_cn23xx_pf_config_info(struct octeon_device *oct,
1382                    struct octeon_config *conf23xx)
1383 {
1384     if (CFG_GET_IQ_MAX_Q(conf23xx) > CN23XX_MAX_INPUT_QUEUES) {
1385         dev_err(&oct->pci_dev->dev, "%s: Num IQ (%d) exceeds Max (%d)\n",
1386             __func__, CFG_GET_IQ_MAX_Q(conf23xx),
1387             CN23XX_MAX_INPUT_QUEUES);
1388         return 1;
1389     }
1390 
1391     if (CFG_GET_OQ_MAX_Q(conf23xx) > CN23XX_MAX_OUTPUT_QUEUES) {
1392         dev_err(&oct->pci_dev->dev, "%s: Num OQ (%d) exceeds Max (%d)\n",
1393             __func__, CFG_GET_OQ_MAX_Q(conf23xx),
1394             CN23XX_MAX_OUTPUT_QUEUES);
1395         return 1;
1396     }
1397 
1398     if (CFG_GET_IQ_INSTR_TYPE(conf23xx) != OCTEON_32BYTE_INSTR &&
1399         CFG_GET_IQ_INSTR_TYPE(conf23xx) != OCTEON_64BYTE_INSTR) {
1400         dev_err(&oct->pci_dev->dev, "%s: Invalid instr type for IQ\n",
1401             __func__);
1402         return 1;
1403     }
1404 
1405     if (!CFG_GET_OQ_REFILL_THRESHOLD(conf23xx)) {
1406         dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n",
1407             __func__);
1408         return 1;
1409     }
1410 
1411     if (!(CFG_GET_OQ_INTR_TIME(conf23xx))) {
1412         dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n",
1413             __func__);
1414         return 1;
1415     }
1416 
1417     return 0;
1418 }
1419 
1420 int cn23xx_fw_loaded(struct octeon_device *oct)
1421 {
1422     u64 val;
1423 
1424     /* If there's more than one active PF on this NIC, then that
1425      * implies that the NIC firmware is loaded and running.  This check
1426      * prevents a rare false negative that might occur if we only relied
1427      * on checking the SCR2_BIT_FW_LOADED flag.  The false negative would
1428      * happen if the PF driver sees SCR2_BIT_FW_LOADED as cleared even
1429      * though the firmware was already loaded but still booting and has yet
1430      * to set SCR2_BIT_FW_LOADED.
1431      */
1432     if (atomic_read(oct->adapter_refcount) > 1)
1433         return 1;
1434 
1435     val = octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2);
1436     return (val >> SCR2_BIT_FW_LOADED) & 1ULL;
1437 }
1438 
1439 void cn23xx_tell_vf_its_macaddr_changed(struct octeon_device *oct, int vfidx,
1440                     u8 *mac)
1441 {
1442     if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vfidx)) {
1443         struct octeon_mbox_cmd mbox_cmd;
1444 
1445         mbox_cmd.msg.u64 = 0;
1446         mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST;
1447         mbox_cmd.msg.s.resp_needed = 0;
1448         mbox_cmd.msg.s.cmd = OCTEON_PF_CHANGED_VF_MACADDR;
1449         mbox_cmd.msg.s.len = 1;
1450         mbox_cmd.recv_len = 0;
1451         mbox_cmd.recv_status = 0;
1452         mbox_cmd.fn = NULL;
1453         mbox_cmd.fn_arg = NULL;
1454         ether_addr_copy(mbox_cmd.msg.s.params, mac);
1455         mbox_cmd.q_no = vfidx * oct->sriov_info.rings_per_vf;
1456         octeon_mbox_write(oct, &mbox_cmd);
1457     }
1458 }
1459 
1460 static void
1461 cn23xx_get_vf_stats_callback(struct octeon_device *oct,
1462                  struct octeon_mbox_cmd *cmd, void *arg)
1463 {
1464     struct oct_vf_stats_ctx *ctx = arg;
1465 
1466     memcpy(ctx->stats, cmd->data, sizeof(struct oct_vf_stats));
1467     atomic_set(&ctx->status, 1);
1468 }
1469 
1470 int cn23xx_get_vf_stats(struct octeon_device *oct, int vfidx,
1471             struct oct_vf_stats *stats)
1472 {
1473     u32 timeout = HZ; // 1sec
1474     struct octeon_mbox_cmd mbox_cmd;
1475     struct oct_vf_stats_ctx ctx;
1476     u32 count = 0, ret;
1477 
1478     if (!(oct->sriov_info.vf_drv_loaded_mask & (1ULL << vfidx)))
1479         return -1;
1480 
1481     if (sizeof(struct oct_vf_stats) > sizeof(mbox_cmd.data))
1482         return -1;
1483 
1484     mbox_cmd.msg.u64 = 0;
1485     mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST;
1486     mbox_cmd.msg.s.resp_needed = 1;
1487     mbox_cmd.msg.s.cmd = OCTEON_GET_VF_STATS;
1488     mbox_cmd.msg.s.len = 1;
1489     mbox_cmd.q_no = vfidx * oct->sriov_info.rings_per_vf;
1490     mbox_cmd.recv_len = 0;
1491     mbox_cmd.recv_status = 0;
1492     mbox_cmd.fn = (octeon_mbox_callback_t)cn23xx_get_vf_stats_callback;
1493     ctx.stats = stats;
1494     atomic_set(&ctx.status, 0);
1495     mbox_cmd.fn_arg = (void *)&ctx;
1496     memset(mbox_cmd.data, 0, sizeof(mbox_cmd.data));
1497     octeon_mbox_write(oct, &mbox_cmd);
1498 
1499     do {
1500         schedule_timeout_uninterruptible(1);
1501     } while ((atomic_read(&ctx.status) == 0) && (count++ < timeout));
1502 
1503     ret = atomic_read(&ctx.status);
1504     if (ret == 0) {
1505         octeon_mbox_cancel(oct, 0);
1506         dev_err(&oct->pci_dev->dev, "Unable to get stats from VF-%d, timedout\n",
1507             vfidx);
1508         return -1;
1509     }
1510 
1511     return 0;
1512 }
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