cavium/common/cavium_ptp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* cavium_ptp.c - PTP 1588 clock on Cavium hardware
0003  * Copyright (c) 2003-2015, 2017 Cavium, Inc.
0004  */
0005
0006 #include <linux/device.h>
0007 #include <linux/module.h>
0008 #include <linux/timecounter.h>
0009 #include <linux/pci.h>
0010
0011 #include "cavium_ptp.h"
0012
0013 #define DRV_NAME "cavium_ptp"
0014
0015 #define PCI_DEVICE_ID_CAVIUM_PTP    0xA00C
0016 #define PCI_SUBSYS_DEVID_88XX_PTP   0xA10C
0017 #define PCI_SUBSYS_DEVID_81XX_PTP   0XA20C
0018 #define PCI_SUBSYS_DEVID_83XX_PTP   0xA30C
0019 #define PCI_DEVICE_ID_CAVIUM_RST    0xA00E
0020
0021 #define PCI_PTP_BAR_NO  0
0022 #define PCI_RST_BAR_NO  0
0023
0024 #define PTP_CLOCK_CFG       0xF00ULL
0025 #define  PTP_CLOCK_CFG_PTP_EN   BIT(0)
0026 #define PTP_CLOCK_LO        0xF08ULL
0027 #define PTP_CLOCK_HI        0xF10ULL
0028 #define PTP_CLOCK_COMP      0xF18ULL
0029
0030 #define RST_BOOT    0x1600ULL
0031 #define CLOCK_BASE_RATE 50000000ULL
0032
0033 static u64 ptp_cavium_clock_get(void)
0034 {
0035     struct pci_dev *pdev;
0036     void __iomem *base;
0037     u64 ret = CLOCK_BASE_RATE * 16;
0038
0039     pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
0040                   PCI_DEVICE_ID_CAVIUM_RST, NULL);
0041     if (!pdev)
0042         goto error;
0043
0044     base = pci_ioremap_bar(pdev, PCI_RST_BAR_NO);
0045     if (!base)
0046         goto error_put_pdev;
0047
0048     ret = CLOCK_BASE_RATE * ((readq(base + RST_BOOT) >> 33) & 0x3f);
0049
0050     iounmap(base);
0051
0052 error_put_pdev:
0053     pci_dev_put(pdev);
0054
0055 error:
0056     return ret;
0057 }
0058
0059 struct cavium_ptp *cavium_ptp_get(void)
0060 {
0061     struct cavium_ptp *ptp;
0062     struct pci_dev *pdev;
0063
0064     pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
0065                   PCI_DEVICE_ID_CAVIUM_PTP, NULL);
0066     if (!pdev)
0067         return ERR_PTR(-ENODEV);
0068
0069     ptp = pci_get_drvdata(pdev);
0070     if (!ptp)
0071         ptp = ERR_PTR(-EPROBE_DEFER);
0072     if (IS_ERR(ptp))
0073         pci_dev_put(pdev);
0074
0075     return ptp;
0076 }
0077 EXPORT_SYMBOL(cavium_ptp_get);
0078
0079 void cavium_ptp_put(struct cavium_ptp *ptp)
0080 {
0081     if (!ptp)
0082         return;
0083     pci_dev_put(ptp->pdev);
0084 }
0085 EXPORT_SYMBOL(cavium_ptp_put);
0086
0087 /**
0088  * cavium_ptp_adjfine() - Adjust ptp frequency
0089  * @ptp_info: PTP clock info
0090  * @scaled_ppm: how much to adjust by, in parts per million, but with a
0091  *              16 bit binary fractional field
0092  */
0093 static int cavium_ptp_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
0094 {
0095     struct cavium_ptp *clock =
0096         container_of(ptp_info, struct cavium_ptp, ptp_info);
0097     unsigned long flags;
0098     u64 comp;
0099     u64 adj;
0100     bool neg_adj = false;
0101
0102     if (scaled_ppm < 0) {
0103         neg_adj = true;
0104         scaled_ppm = -scaled_ppm;
0105     }
0106
0107     /* The hardware adds the clock compensation value to the PTP clock
0108      * on every coprocessor clock cycle. Typical convention is that it
0109      * represent number of nanosecond betwen each cycle. In this
0110      * convention compensation value is in 64 bit fixed-point
0111      * representation where upper 32 bits are number of nanoseconds
0112      * and lower is fractions of nanosecond.
0113      * The scaled_ppm represent the ratio in "parts per bilion" by which the
0114      * compensation value should be corrected.
0115      * To calculate new compenstation value we use 64bit fixed point
0116      * arithmetic on following formula
0117      * comp = tbase + tbase * scaled_ppm / (1M * 2^16)
0118      * where tbase is the basic compensation value calculated initialy
0119      * in cavium_ptp_init() -> tbase = 1/Hz. Then we use endian
0120      * independent structure definition to write data to PTP register.
0121      */
0122     comp = ((u64)1000000000ull << 32) / clock->clock_rate;
0123     adj = comp * scaled_ppm;
0124     adj >>= 16;
0125     adj = div_u64(adj, 1000000ull);
0126     comp = neg_adj ? comp - adj : comp + adj;
0127
0128     spin_lock_irqsave(&clock->spin_lock, flags);
0129     writeq(comp, clock->reg_base + PTP_CLOCK_COMP);
0130     spin_unlock_irqrestore(&clock->spin_lock, flags);
0131
0132     return 0;
0133 }
0134
0135 /**
0136  * cavium_ptp_adjtime() - Adjust ptp time
0137  * @ptp_info:   PTP clock info
0138  * @delta: how much to adjust by, in nanosecs
0139  */
0140 static int cavium_ptp_adjtime(struct ptp_clock_info *ptp_info, s64 delta)
0141 {
0142     struct cavium_ptp *clock =
0143         container_of(ptp_info, struct cavium_ptp, ptp_info);
0144     unsigned long flags;
0145
0146     spin_lock_irqsave(&clock->spin_lock, flags);
0147     timecounter_adjtime(&clock->time_counter, delta);
0148     spin_unlock_irqrestore(&clock->spin_lock, flags);
0149
0150     /* Sync, for network driver to get latest value */
0151     smp_mb();
0152
0153     return 0;
0154 }
0155
0156 /**
0157  * cavium_ptp_gettime() - Get hardware clock time with adjustment
0158  * @ptp_info: PTP clock info
0159  * @ts:  timespec
0160  */
0161 static int cavium_ptp_gettime(struct ptp_clock_info *ptp_info,
0162                   struct timespec64 *ts)
0163 {
0164     struct cavium_ptp *clock =
0165         container_of(ptp_info, struct cavium_ptp, ptp_info);
0166     unsigned long flags;
0167     u64 nsec;
0168
0169     spin_lock_irqsave(&clock->spin_lock, flags);
0170     nsec = timecounter_read(&clock->time_counter);
0171     spin_unlock_irqrestore(&clock->spin_lock, flags);
0172
0173     *ts = ns_to_timespec64(nsec);
0174
0175     return 0;
0176 }
0177
0178 /**
0179  * cavium_ptp_settime() - Set hardware clock time. Reset adjustment
0180  * @ptp_info: PTP clock info
0181  * @ts:  timespec
0182  */
0183 static int cavium_ptp_settime(struct ptp_clock_info *ptp_info,
0184                   const struct timespec64 *ts)
0185 {
0186     struct cavium_ptp *clock =
0187         container_of(ptp_info, struct cavium_ptp, ptp_info);
0188     unsigned long flags;
0189     u64 nsec;
0190
0191     nsec = timespec64_to_ns(ts);
0192
0193     spin_lock_irqsave(&clock->spin_lock, flags);
0194     timecounter_init(&clock->time_counter, &clock->cycle_counter, nsec);
0195     spin_unlock_irqrestore(&clock->spin_lock, flags);
0196
0197     return 0;
0198 }
0199
0200 /**
0201  * cavium_ptp_enable() - Request to enable or disable an ancillary feature.
0202  * @ptp_info: PTP clock info
0203  * @rq:  request
0204  * @on:  is it on
0205  */
0206 static int cavium_ptp_enable(struct ptp_clock_info *ptp_info,
0207                  struct ptp_clock_request *rq, int on)
0208 {
0209     return -EOPNOTSUPP;
0210 }
0211
0212 static u64 cavium_ptp_cc_read(const struct cyclecounter *cc)
0213 {
0214     struct cavium_ptp *clock =
0215         container_of(cc, struct cavium_ptp, cycle_counter);
0216
0217     return readq(clock->reg_base + PTP_CLOCK_HI);
0218 }
0219
0220 static int cavium_ptp_probe(struct pci_dev *pdev,
0221                 const struct pci_device_id *ent)
0222 {
0223     struct device *dev = &pdev->dev;
0224     struct cavium_ptp *clock;
0225     struct cyclecounter *cc;
0226     u64 clock_cfg;
0227     u64 clock_comp;
0228     int err;
0229
0230     clock = devm_kzalloc(dev, sizeof(*clock), GFP_KERNEL);
0231     if (!clock) {
0232         err = -ENOMEM;
0233         goto error;
0234     }
0235
0236     clock->pdev = pdev;
0237
0238     err = pcim_enable_device(pdev);
0239     if (err)
0240         goto error_free;
0241
0242     err = pcim_iomap_regions(pdev, 1 << PCI_PTP_BAR_NO, pci_name(pdev));
0243     if (err)
0244         goto error_free;
0245
0246     clock->reg_base = pcim_iomap_table(pdev)[PCI_PTP_BAR_NO];
0247
0248     spin_lock_init(&clock->spin_lock);
0249
0250     cc = &clock->cycle_counter;
0251     cc->read = cavium_ptp_cc_read;
0252     cc->mask = CYCLECOUNTER_MASK(64);
0253     cc->mult = 1;
0254     cc->shift = 0;
0255
0256     timecounter_init(&clock->time_counter, &clock->cycle_counter,
0257              ktime_to_ns(ktime_get_real()));
0258
0259     clock->clock_rate = ptp_cavium_clock_get();
0260
0261     clock->ptp_info = (struct ptp_clock_info) {
0262         .owner      = THIS_MODULE,
0263         .name       = "ThunderX PTP",
0264         .max_adj    = 1000000000ull,
0265         .n_ext_ts   = 0,
0266         .n_pins     = 0,
0267         .pps        = 0,
0268         .adjfine    = cavium_ptp_adjfine,
0269         .adjtime    = cavium_ptp_adjtime,
0270         .gettime64  = cavium_ptp_gettime,
0271         .settime64  = cavium_ptp_settime,
0272         .enable     = cavium_ptp_enable,
0273     };
0274
0275     clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
0276     clock_cfg |= PTP_CLOCK_CFG_PTP_EN;
0277     writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
0278
0279     clock_comp = ((u64)1000000000ull << 32) / clock->clock_rate;
0280     writeq(clock_comp, clock->reg_base + PTP_CLOCK_COMP);
0281
0282     clock->ptp_clock = ptp_clock_register(&clock->ptp_info, dev);
0283     if (IS_ERR(clock->ptp_clock)) {
0284         err = PTR_ERR(clock->ptp_clock);
0285         goto error_stop;
0286     }
0287
0288     pci_set_drvdata(pdev, clock);
0289     return 0;
0290
0291 error_stop:
0292     clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
0293     clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN;
0294     writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
0295     pcim_iounmap_regions(pdev, 1 << PCI_PTP_BAR_NO);
0296
0297 error_free:
0298     devm_kfree(dev, clock);
0299
0300 error:
0301     /* For `cavium_ptp_get()` we need to differentiate between the case
0302      * when the core has not tried to probe this device and the case when
0303      * the probe failed.  In the later case we pretend that the
0304      * initialization was successful and keep the error in
0305      * `dev->driver_data`.
0306      */
0307     pci_set_drvdata(pdev, ERR_PTR(err));
0308     return 0;
0309 }
0310
0311 static void cavium_ptp_remove(struct pci_dev *pdev)
0312 {
0313     struct cavium_ptp *clock = pci_get_drvdata(pdev);
0314     u64 clock_cfg;
0315
0316     if (IS_ERR_OR_NULL(clock))
0317         return;
0318
0319     ptp_clock_unregister(clock->ptp_clock);
0320
0321     clock_cfg = readq(clock->reg_base + PTP_CLOCK_CFG);
0322     clock_cfg &= ~PTP_CLOCK_CFG_PTP_EN;
0323     writeq(clock_cfg, clock->reg_base + PTP_CLOCK_CFG);
0324 }
0325
0326 static const struct pci_device_id cavium_ptp_id_table[] = {
0327     { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP,
0328             PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_88XX_PTP) },
0329     { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP,
0330             PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_81XX_PTP) },
0331     { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_CAVIUM_PTP,
0332             PCI_VENDOR_ID_CAVIUM, PCI_SUBSYS_DEVID_83XX_PTP) },
0333     { 0, }
0334 };
0335
0336 static struct pci_driver cavium_ptp_driver = {
0337     .name = DRV_NAME,
0338     .id_table = cavium_ptp_id_table,
0339     .probe = cavium_ptp_probe,
0340     .remove = cavium_ptp_remove,
0341 };
0342
0343 module_pci_driver(cavium_ptp_driver);
0344
0345 MODULE_DESCRIPTION(DRV_NAME);
0346 MODULE_AUTHOR("Cavium Networks <support@cavium.com>");
0347 MODULE_LICENSE("GPL v2");
0348 MODULE_DEVICE_TABLE(pci, cavium_ptp_id_table);