brocade/bna/bna_hw_defs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Linux network driver for QLogic BR-series Converged Network Adapter.
0004  */
0005 /*
0006  * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
0007  * Copyright (c) 2014-2015 QLogic Corporation
0008  * All rights reserved
0009  * www.qlogic.com
0010  */
0011
0012 /* File for interrupt macros and functions */
0013
0014 #ifndef __BNA_HW_DEFS_H__
0015 #define __BNA_HW_DEFS_H__
0016
0017 #include "bfi_reg.h"
0018
0019 /* SW imposed limits */
0020
0021 #define BFI_ENET_DEF_TXQ        1
0022 #define BFI_ENET_DEF_RXP        1
0023 #define BFI_ENET_DEF_UCAM       1
0024 #define BFI_ENET_DEF_RITSZ      1
0025
0026 #define BFI_ENET_MAX_MCAM       256
0027
0028 #define BFI_INVALID_RID         -1
0029
0030 #define BFI_IBIDX_SIZE          4
0031
0032 #define BFI_VLAN_WORD_SHIFT     5   /* 32 bits */
0033 #define BFI_VLAN_WORD_MASK      0x1F
0034 #define BFI_VLAN_BLOCK_SHIFT        9   /* 512 bits */
0035 #define BFI_VLAN_BMASK_ALL      0xFF
0036
0037 #define BFI_COALESCING_TIMER_UNIT   5   /* 5us */
0038 #define BFI_MAX_COALESCING_TIMEO    0xFF    /* in 5us units */
0039 #define BFI_MAX_INTERPKT_COUNT      0xFF
0040 #define BFI_MAX_INTERPKT_TIMEO      0xF /* in 0.5us units */
0041 #define BFI_TX_COALESCING_TIMEO     20  /* 20 * 5 = 100us */
0042 #define BFI_TX_INTERPKT_COUNT       12  /* Pkt Cnt = 12 */
0043 #define BFI_TX_INTERPKT_TIMEO       15  /* 15 * 0.5 = 7.5us */
0044 #define BFI_RX_COALESCING_TIMEO     12  /* 12 * 5 = 60us */
0045 #define BFI_RX_INTERPKT_COUNT       6   /* Pkt Cnt = 6 */
0046 #define BFI_RX_INTERPKT_TIMEO       3   /* 3 * 0.5 = 1.5us */
0047
0048 #define BFI_TXQ_WI_SIZE         64  /* bytes */
0049 #define BFI_RXQ_WI_SIZE         8   /* bytes */
0050 #define BFI_CQ_WI_SIZE          16  /* bytes */
0051 #define BFI_TX_MAX_WRR_QUOTA        0xFFF
0052
0053 #define BFI_TX_MAX_VECTORS_PER_WI   4
0054 #define BFI_TX_MAX_VECTORS_PER_PKT  0xFF
0055 #define BFI_TX_MAX_DATA_PER_VECTOR  0xFFFF
0056 #define BFI_TX_MAX_DATA_PER_PKT     0xFFFFFF
0057
0058 /* Small Q buffer size */
0059 #define BFI_SMALL_RXBUF_SIZE        128
0060
0061 #define BFI_TX_MAX_PRIO         8
0062 #define BFI_TX_PRIO_MAP_ALL     0xFF
0063
0064 /*
0065  *
0066  * Register definitions and macros
0067  *
0068  */
0069
0070 #define BNA_PCI_REG_CT_ADDRSZ       (0x40000)
0071
0072 #define ct_reg_addr_init(_bna, _pcidev)                 \
0073 {                                   \
0074     struct bna_reg_offset reg_offset[] =                \
0075     {{HOSTFN0_INT_STATUS, HOSTFN0_INT_MSK},             \
0076      {HOSTFN1_INT_STATUS, HOSTFN1_INT_MSK},             \
0077      {HOSTFN2_INT_STATUS, HOSTFN2_INT_MSK},             \
0078      {HOSTFN3_INT_STATUS, HOSTFN3_INT_MSK} };           \
0079                                     \
0080     (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +       \
0081                 reg_offset[(_pcidev)->pci_func].fn_int_status;\
0082     (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +     \
0083                 reg_offset[(_pcidev)->pci_func].fn_int_mask;\
0084 }
0085
0086 #define ct_bit_defn_init(_bna, _pcidev)                 \
0087 {                                   \
0088     (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0 |      \
0089                     __HFN_INT_MBOX_LPU1);       \
0090     (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0 |        \
0091                     __HFN_INT_MBOX_LPU1);       \
0092     (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK);      \
0093     (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK);        \
0094     (_bna)->bits.halt_status_bits = __HFN_INT_LL_HALT;      \
0095     (_bna)->bits.halt_mask_bits = __HFN_INT_LL_HALT;        \
0096 }
0097
0098 #define ct2_reg_addr_init(_bna, _pcidev)                \
0099 {                                   \
0100     (_bna)->regs.fn_int_status = (_pcidev)->pci_bar_kva +       \
0101                 CT2_HOSTFN_INT_STATUS;          \
0102     (_bna)->regs.fn_int_mask = (_pcidev)->pci_bar_kva +     \
0103                 CT2_HOSTFN_INTR_MASK;           \
0104 }
0105
0106 #define ct2_bit_defn_init(_bna, _pcidev)                \
0107 {                                   \
0108     (_bna)->bits.mbox_status_bits = (__HFN_INT_MBOX_LPU0_CT2 |  \
0109                     __HFN_INT_MBOX_LPU1_CT2);   \
0110     (_bna)->bits.mbox_mask_bits = (__HFN_INT_MBOX_LPU0_CT2 |    \
0111                     __HFN_INT_MBOX_LPU1_CT2);   \
0112     (_bna)->bits.error_status_bits = (__HFN_INT_ERR_MASK_CT2);  \
0113     (_bna)->bits.error_mask_bits = (__HFN_INT_ERR_MASK_CT2);    \
0114     (_bna)->bits.halt_status_bits = __HFN_INT_CPQ_HALT_CT2;     \
0115     (_bna)->bits.halt_mask_bits = __HFN_INT_CPQ_HALT_CT2;       \
0116 }
0117
0118 #define bna_reg_addr_init(_bna, _pcidev)                \
0119 {                                   \
0120     switch ((_pcidev)->device_id) {                 \
0121     case PCI_DEVICE_ID_BROCADE_CT:                  \
0122         ct_reg_addr_init((_bna), (_pcidev));            \
0123         ct_bit_defn_init((_bna), (_pcidev));            \
0124         break;                          \
0125     case BFA_PCI_DEVICE_ID_CT2:                 \
0126         ct2_reg_addr_init((_bna), (_pcidev));           \
0127         ct2_bit_defn_init((_bna), (_pcidev));           \
0128         break;                          \
0129     }                               \
0130 }
0131
0132 #define bna_port_id_get(_bna) ((_bna)->ioceth.ioc.port_id)
0133
0134 /*  Interrupt related bits, flags and macros  */
0135
0136 #define IB_STATUS_BITS      0x0000ffff
0137
0138 #define BNA_IS_MBOX_INTR(_bna, _intr_status)                \
0139     ((_intr_status) & (_bna)->bits.mbox_status_bits)
0140
0141 #define BNA_IS_HALT_INTR(_bna, _intr_status)                \
0142     ((_intr_status) & (_bna)->bits.halt_status_bits)
0143
0144 #define BNA_IS_ERR_INTR(_bna, _intr_status) \
0145     ((_intr_status) & (_bna)->bits.error_status_bits)
0146
0147 #define BNA_IS_MBOX_ERR_INTR(_bna, _intr_status)    \
0148     (BNA_IS_MBOX_INTR(_bna, _intr_status) |     \
0149     BNA_IS_ERR_INTR(_bna, _intr_status))
0150
0151 #define BNA_IS_INTX_DATA_INTR(_intr_status)     \
0152         ((_intr_status) & IB_STATUS_BITS)
0153
0154 #define bna_halt_clear(_bna)                        \
0155 do {                                    \
0156     u32 init_halt;                      \
0157     init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
0158     init_halt &= ~__FW_INIT_HALT_P;                 \
0159     writel(init_halt, (_bna)->ioceth.ioc.ioc_regs.ll_halt); \
0160     init_halt = readl((_bna)->ioceth.ioc.ioc_regs.ll_halt); \
0161 } while (0)
0162
0163 #define bna_intx_disable(_bna, _cur_mask)               \
0164 {                                   \
0165     (_cur_mask) = readl((_bna)->regs.fn_int_mask);      \
0166     writel(0xffffffff, (_bna)->regs.fn_int_mask);       \
0167 }
0168
0169 #define bna_intx_enable(bna, new_mask)                  \
0170     writel((new_mask), (bna)->regs.fn_int_mask)
0171 #define bna_mbox_intr_disable(bna)                  \
0172 do {                                    \
0173     u32 mask;                           \
0174     mask = readl((bna)->regs.fn_int_mask);              \
0175     writel((mask | (bna)->bits.mbox_mask_bits |         \
0176         (bna)->bits.error_mask_bits), (bna)->regs.fn_int_mask); \
0177     mask = readl((bna)->regs.fn_int_mask);              \
0178 } while (0)
0179
0180 #define bna_mbox_intr_enable(bna)                   \
0181 do {                                    \
0182     u32 mask;                           \
0183     mask = readl((bna)->regs.fn_int_mask);              \
0184     writel((mask & ~((bna)->bits.mbox_mask_bits |           \
0185         (bna)->bits.error_mask_bits)), (bna)->regs.fn_int_mask);\
0186     mask = readl((bna)->regs.fn_int_mask);              \
0187 } while (0)
0188
0189 #define bna_intr_status_get(_bna, _status)              \
0190 {                                   \
0191     (_status) = readl((_bna)->regs.fn_int_status);          \
0192     if (_status) {                          \
0193         writel(((_status) & ~(_bna)->bits.mbox_status_bits),    \
0194             (_bna)->regs.fn_int_status);            \
0195     }                               \
0196 }
0197
0198 /*
0199  * MAX ACK EVENTS : No. of acks that can be accumulated in driver,
0200  * before acking to h/w. The no. of bits is 16 in the doorbell register,
0201  * however we keep this limited to 15 bits.
0202  * This is because around the edge of 64K boundary (16 bits), one
0203  * single poll can make the accumulated ACK counter cross the 64K boundary,
0204  * causing problems, when we try to ack with a value greater than 64K.
0205  * 15 bits (32K) should  be large enough to accumulate, anyways, and the max.
0206  * acked events to h/w can be (32K + max poll weight) (currently 64).
0207  */
0208 #define BNA_IB_MAX_ACK_EVENTS       BIT(15)
0209
0210 /* These macros build the data portion of the TxQ/RxQ doorbell */
0211 #define BNA_DOORBELL_Q_PRD_IDX(_pi) (0x80000000 | (_pi))
0212 #define BNA_DOORBELL_Q_STOP     (0x40000000)
0213
0214 /* These macros build the data portion of the IB doorbell */
0215 #define BNA_DOORBELL_IB_INT_ACK(_timeout, _events)          \
0216     (0x80000000 | ((_timeout) << 16) | (_events))
0217 #define BNA_DOORBELL_IB_INT_DISABLE (0x40000000)
0218
0219 /* Set the coalescing timer for the given ib */
0220 #define bna_ib_coalescing_timer_set(_i_dbell, _cls_timer)       \
0221     ((_i_dbell)->doorbell_ack = BNA_DOORBELL_IB_INT_ACK((_cls_timer), 0))
0222
0223 /* Acks 'events' # of events for a given ib while disabling interrupts */
0224 #define bna_ib_ack_disable_irq(_i_dbell, _events)           \
0225     (writel(BNA_DOORBELL_IB_INT_ACK(0, (_events)),          \
0226         (_i_dbell)->doorbell_addr))
0227
0228 /* Acks 'events' # of events for a given ib */
0229 #define bna_ib_ack(_i_dbell, _events)                   \
0230     (writel(((_i_dbell)->doorbell_ack | (_events)),     \
0231         (_i_dbell)->doorbell_addr))
0232
0233 #define bna_ib_start(_bna, _ib, _is_regular)                \
0234 {                                   \
0235     u32 intx_mask;                      \
0236     struct bna_ib *ib = _ib;                    \
0237     if ((ib->intr_type == BNA_INTR_T_INTX)) {           \
0238         bna_intx_disable((_bna), intx_mask);            \
0239         intx_mask &= ~(ib->intr_vector);            \
0240         bna_intx_enable((_bna), intx_mask);         \
0241     }                               \
0242     bna_ib_coalescing_timer_set(&ib->door_bell,         \
0243             ib->coalescing_timeo);              \
0244     if (_is_regular)                        \
0245         bna_ib_ack(&ib->door_bell, 0);              \
0246 }
0247
0248 #define bna_ib_stop(_bna, _ib)                      \
0249 {                                   \
0250     u32 intx_mask;                      \
0251     struct bna_ib *ib = _ib;                    \
0252     writel(BNA_DOORBELL_IB_INT_DISABLE,             \
0253         ib->door_bell.doorbell_addr);               \
0254     if (ib->intr_type == BNA_INTR_T_INTX) {             \
0255         bna_intx_disable((_bna), intx_mask);            \
0256         intx_mask |= ib->intr_vector;               \
0257         bna_intx_enable((_bna), intx_mask);         \
0258     }                               \
0259 }
0260
0261 #define bna_txq_prod_indx_doorbell(_tcb)                \
0262     (writel(BNA_DOORBELL_Q_PRD_IDX((_tcb)->producer_index),     \
0263         (_tcb)->q_dbell))
0264
0265 #define bna_rxq_prod_indx_doorbell(_rcb)                \
0266     (writel(BNA_DOORBELL_Q_PRD_IDX((_rcb)->producer_index),     \
0267         (_rcb)->q_dbell))
0268
0269 /* TxQ, RxQ, CQ related bits, offsets, macros */
0270
0271 /* TxQ Entry Opcodes */
0272 #define BNA_TXQ_WI_SEND         (0x402) /* Single Frame Transmission */
0273 #define BNA_TXQ_WI_SEND_LSO     (0x403) /* Multi-Frame Transmission */
0274 #define BNA_TXQ_WI_EXTENSION        (0x104) /* Extension WI */
0275
0276 /* TxQ Entry Control Flags */
0277 #define BNA_TXQ_WI_CF_FCOE_CRC      BIT(8)
0278 #define BNA_TXQ_WI_CF_IPID_MODE     BIT(5)
0279 #define BNA_TXQ_WI_CF_INS_PRIO      BIT(4)
0280 #define BNA_TXQ_WI_CF_INS_VLAN      BIT(3)
0281 #define BNA_TXQ_WI_CF_UDP_CKSUM     BIT(2)
0282 #define BNA_TXQ_WI_CF_TCP_CKSUM     BIT(1)
0283 #define BNA_TXQ_WI_CF_IP_CKSUM      BIT(0)
0284
0285 #define BNA_TXQ_WI_L4_HDR_N_OFFSET(_hdr_size, _offset) \
0286         (((_hdr_size) << 10) | ((_offset) & 0x3FF))
0287
0288 /*
0289  * Completion Q defines
0290  */
0291 /* CQ Entry Flags */
0292 #define BNA_CQ_EF_MAC_ERROR BIT(0)
0293 #define BNA_CQ_EF_FCS_ERROR BIT(1)
0294 #define BNA_CQ_EF_TOO_LONG  BIT(2)
0295 #define BNA_CQ_EF_FC_CRC_OK BIT(3)
0296
0297 #define BNA_CQ_EF_RSVD1     BIT(4)
0298 #define BNA_CQ_EF_L4_CKSUM_OK   BIT(5)
0299 #define BNA_CQ_EF_L3_CKSUM_OK   BIT(6)
0300 #define BNA_CQ_EF_HDS_HEADER    BIT(7)
0301
0302 #define BNA_CQ_EF_UDP       BIT(8)
0303 #define BNA_CQ_EF_TCP       BIT(9)
0304 #define BNA_CQ_EF_IP_OPTIONS    BIT(10)
0305 #define BNA_CQ_EF_IPV6      BIT(11)
0306
0307 #define BNA_CQ_EF_IPV4      BIT(12)
0308 #define BNA_CQ_EF_VLAN      BIT(13)
0309 #define BNA_CQ_EF_RSS       BIT(14)
0310 #define BNA_CQ_EF_RSVD2     BIT(15)
0311
0312 #define BNA_CQ_EF_MCAST_MATCH   BIT(16)
0313 #define BNA_CQ_EF_MCAST     BIT(17)
0314 #define BNA_CQ_EF_BCAST     BIT(18)
0315 #define BNA_CQ_EF_REMOTE    BIT(19)
0316
0317 #define BNA_CQ_EF_LOCAL     BIT(20)
0318 /* CAT2 ASIC does not use bit 21 as per the SPEC.
0319  * Bit 31 is set in every end of frame completion
0320  */
0321 #define BNA_CQ_EF_EOP       BIT(31)
0322
0323 /* Data structures */
0324
0325 struct bna_reg_offset {
0326     u32 fn_int_status;
0327     u32 fn_int_mask;
0328 };
0329
0330 struct bna_bit_defn {
0331     u32 mbox_status_bits;
0332     u32 mbox_mask_bits;
0333     u32 error_status_bits;
0334     u32 error_mask_bits;
0335     u32 halt_status_bits;
0336     u32 halt_mask_bits;
0337 };
0338
0339 struct bna_reg {
0340     void __iomem *fn_int_status;
0341     void __iomem *fn_int_mask;
0342 };
0343
0344 /* TxQ Vector (a.k.a. Tx-Buffer Descriptor) */
0345 struct bna_dma_addr {
0346     u32     msb;
0347     u32     lsb;
0348 };
0349
0350 struct bna_txq_wi_vector {
0351     u16     reserved;
0352     u16     length;     /* Only 14 LSB are valid */
0353     struct bna_dma_addr host_addr; /* Tx-Buf DMA addr */
0354 };
0355
0356 /*  TxQ Entry Structure
0357  *
0358  *  BEWARE:  Load values into this structure with correct endianness.
0359  */
0360 struct bna_txq_entry {
0361     union {
0362         struct {
0363             u8 reserved;
0364             u8 num_vectors; /* number of vectors present */
0365             u16 opcode; /* Either */
0366                             /* BNA_TXQ_WI_SEND or */
0367                             /* BNA_TXQ_WI_SEND_LSO */
0368             u16 flags; /* OR of all the flags */
0369             u16 l4_hdr_size_n_offset;
0370             u16 vlan_tag;
0371             u16 lso_mss;    /* Only 14 LSB are valid */
0372             u32 frame_length;   /* Only 24 LSB are valid */
0373         } wi;
0374
0375         struct {
0376             u16 reserved;
0377             u16 opcode; /* Must be */
0378                             /* BNA_TXQ_WI_EXTENSION */
0379             u32 reserved2[3];   /* Place holder for */
0380                         /* removed vector (12 bytes) */
0381         } wi_ext;
0382     } hdr;
0383     struct bna_txq_wi_vector vector[4];
0384 };
0385
0386 /* RxQ Entry Structure */
0387 struct bna_rxq_entry {      /* Rx-Buffer */
0388     struct bna_dma_addr host_addr; /* Rx-Buffer DMA address */
0389 };
0390
0391 /* CQ Entry Structure */
0392 struct bna_cq_entry {
0393     u32 flags;
0394     u16 vlan_tag;
0395     u16 length;
0396     u32 rss_hash;
0397     u8 valid;
0398     u8 reserved1;
0399     u8 reserved2;
0400     u8 rxq_id;
0401 };
0402
0403 #endif /* __BNA_HW_DEFS_H__ */