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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Linux network driver for QLogic BR-series Converged Network Adapter.
0004  */
0005 /*
0006  * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
0007  * Copyright (c) 2014-2015 QLogic Corporation
0008  * All rights reserved
0009  * www.qlogic.com
0010  */
0011 
0012 /*
0013  * bfi_reg.h ASIC register defines for all QLogic BR-series adapter ASICs
0014  */
0015 
0016 #ifndef __BFI_REG_H__
0017 #define __BFI_REG_H__
0018 
0019 #define HOSTFN0_INT_STATUS      0x00014000  /* cb/ct    */
0020 #define HOSTFN1_INT_STATUS      0x00014100  /* cb/ct    */
0021 #define HOSTFN2_INT_STATUS      0x00014300  /* ct       */
0022 #define HOSTFN3_INT_STATUS      0x00014400  /* ct       */
0023 #define HOSTFN0_INT_MSK         0x00014004  /* cb/ct    */
0024 #define HOSTFN1_INT_MSK         0x00014104  /* cb/ct    */
0025 #define HOSTFN2_INT_MSK         0x00014304  /* ct       */
0026 #define HOSTFN3_INT_MSK         0x00014404  /* ct       */
0027 
0028 #define HOST_PAGE_NUM_FN0       0x00014008  /* cb/ct    */
0029 #define HOST_PAGE_NUM_FN1       0x00014108  /* cb/ct    */
0030 #define HOST_PAGE_NUM_FN2       0x00014308  /* ct       */
0031 #define HOST_PAGE_NUM_FN3       0x00014408  /* ct       */
0032 
0033 #define APP_PLL_LCLK_CTL_REG        0x00014204  /* cb/ct    */
0034 #define __P_LCLK_PLL_LOCK       0x80000000
0035 #define __APP_PLL_LCLK_SRAM_USE_100MHZ  0x00100000
0036 #define __APP_PLL_LCLK_RESET_TIMER_MK   0x000e0000
0037 #define __APP_PLL_LCLK_RESET_TIMER_SH   17
0038 #define __APP_PLL_LCLK_RESET_TIMER(_v)  ((_v) << __APP_PLL_LCLK_RESET_TIMER_SH)
0039 #define __APP_PLL_LCLK_LOGIC_SOFT_RESET 0x00010000
0040 #define __APP_PLL_LCLK_CNTLMT0_1_MK 0x0000c000
0041 #define __APP_PLL_LCLK_CNTLMT0_1_SH 14
0042 #define __APP_PLL_LCLK_CNTLMT0_1(_v)    ((_v) << __APP_PLL_LCLK_CNTLMT0_1_SH)
0043 #define __APP_PLL_LCLK_JITLMT0_1_MK 0x00003000
0044 #define __APP_PLL_LCLK_JITLMT0_1_SH 12
0045 #define __APP_PLL_LCLK_JITLMT0_1(_v)    ((_v) << __APP_PLL_LCLK_JITLMT0_1_SH)
0046 #define __APP_PLL_LCLK_HREF     0x00000800
0047 #define __APP_PLL_LCLK_HDIV     0x00000400
0048 #define __APP_PLL_LCLK_P0_1_MK      0x00000300
0049 #define __APP_PLL_LCLK_P0_1_SH      8
0050 #define __APP_PLL_LCLK_P0_1(_v)     ((_v) << __APP_PLL_LCLK_P0_1_SH)
0051 #define __APP_PLL_LCLK_Z0_2_MK      0x000000e0
0052 #define __APP_PLL_LCLK_Z0_2_SH      5
0053 #define __APP_PLL_LCLK_Z0_2(_v)     ((_v) << __APP_PLL_LCLK_Z0_2_SH)
0054 #define __APP_PLL_LCLK_RSEL200500   0x00000010
0055 #define __APP_PLL_LCLK_ENARST       0x00000008
0056 #define __APP_PLL_LCLK_BYPASS       0x00000004
0057 #define __APP_PLL_LCLK_LRESETN      0x00000002
0058 #define __APP_PLL_LCLK_ENABLE       0x00000001
0059 #define APP_PLL_SCLK_CTL_REG        0x00014208  /* cb/ct    */
0060 #define __P_SCLK_PLL_LOCK       0x80000000
0061 #define __APP_PLL_SCLK_RESET_TIMER_MK   0x000e0000
0062 #define __APP_PLL_SCLK_RESET_TIMER_SH   17
0063 #define __APP_PLL_SCLK_RESET_TIMER(_v)  ((_v) << __APP_PLL_SCLK_RESET_TIMER_SH)
0064 #define __APP_PLL_SCLK_LOGIC_SOFT_RESET 0x00010000
0065 #define __APP_PLL_SCLK_CNTLMT0_1_MK 0x0000c000
0066 #define __APP_PLL_SCLK_CNTLMT0_1_SH 14
0067 #define __APP_PLL_SCLK_CNTLMT0_1(_v)    ((_v) << __APP_PLL_SCLK_CNTLMT0_1_SH)
0068 #define __APP_PLL_SCLK_JITLMT0_1_MK 0x00003000
0069 #define __APP_PLL_SCLK_JITLMT0_1_SH 12
0070 #define __APP_PLL_SCLK_JITLMT0_1(_v)    ((_v) << __APP_PLL_SCLK_JITLMT0_1_SH)
0071 #define __APP_PLL_SCLK_HREF     0x00000800
0072 #define __APP_PLL_SCLK_HDIV     0x00000400
0073 #define __APP_PLL_SCLK_P0_1_MK      0x00000300
0074 #define __APP_PLL_SCLK_P0_1_SH      8
0075 #define __APP_PLL_SCLK_P0_1(_v)     ((_v) << __APP_PLL_SCLK_P0_1_SH)
0076 #define __APP_PLL_SCLK_Z0_2_MK      0x000000e0
0077 #define __APP_PLL_SCLK_Z0_2_SH      5
0078 #define __APP_PLL_SCLK_Z0_2(_v)     ((_v) << __APP_PLL_SCLK_Z0_2_SH)
0079 #define __APP_PLL_SCLK_RSEL200500   0x00000010
0080 #define __APP_PLL_SCLK_ENARST       0x00000008
0081 #define __APP_PLL_SCLK_BYPASS       0x00000004
0082 #define __APP_PLL_SCLK_LRESETN      0x00000002
0083 #define __APP_PLL_SCLK_ENABLE       0x00000001
0084 #define __ENABLE_MAC_AHB_1      0x00800000  /* ct       */
0085 #define __ENABLE_MAC_AHB_0      0x00400000  /* ct       */
0086 #define __ENABLE_MAC_1          0x00200000  /* ct       */
0087 #define __ENABLE_MAC_0          0x00100000  /* ct       */
0088 
0089 #define HOST_SEM0_REG           0x00014230  /* cb/ct    */
0090 #define HOST_SEM1_REG           0x00014234  /* cb/ct    */
0091 #define HOST_SEM2_REG           0x00014238  /* cb/ct    */
0092 #define HOST_SEM3_REG           0x0001423c  /* cb/ct    */
0093 #define HOST_SEM4_REG           0x00014610  /* cb/ct    */
0094 #define HOST_SEM5_REG           0x00014614  /* cb/ct    */
0095 #define HOST_SEM6_REG           0x00014618  /* cb/ct    */
0096 #define HOST_SEM7_REG           0x0001461c  /* cb/ct    */
0097 #define HOST_SEM0_INFO_REG      0x00014240  /* cb/ct    */
0098 #define HOST_SEM1_INFO_REG      0x00014244  /* cb/ct    */
0099 #define HOST_SEM2_INFO_REG      0x00014248  /* cb/ct    */
0100 #define HOST_SEM3_INFO_REG      0x0001424c  /* cb/ct    */
0101 #define HOST_SEM4_INFO_REG      0x00014620  /* cb/ct    */
0102 #define HOST_SEM5_INFO_REG      0x00014624  /* cb/ct    */
0103 #define HOST_SEM6_INFO_REG      0x00014628  /* cb/ct    */
0104 #define HOST_SEM7_INFO_REG      0x0001462c  /* cb/ct    */
0105 
0106 #define HOSTFN0_LPU0_CMD_STAT       0x00019000  /* cb/ct    */
0107 #define HOSTFN0_LPU1_CMD_STAT       0x00019004  /* cb/ct    */
0108 #define HOSTFN1_LPU0_CMD_STAT       0x00019010  /* cb/ct    */
0109 #define HOSTFN1_LPU1_CMD_STAT       0x00019014  /* cb/ct    */
0110 #define HOSTFN2_LPU0_CMD_STAT       0x00019150  /* ct       */
0111 #define HOSTFN2_LPU1_CMD_STAT       0x00019154  /* ct       */
0112 #define HOSTFN3_LPU0_CMD_STAT       0x00019160  /* ct       */
0113 #define HOSTFN3_LPU1_CMD_STAT       0x00019164  /* ct       */
0114 #define LPU0_HOSTFN0_CMD_STAT       0x00019008  /* cb/ct    */
0115 #define LPU1_HOSTFN0_CMD_STAT       0x0001900c  /* cb/ct    */
0116 #define LPU0_HOSTFN1_CMD_STAT       0x00019018  /* cb/ct    */
0117 #define LPU1_HOSTFN1_CMD_STAT       0x0001901c  /* cb/ct    */
0118 #define LPU0_HOSTFN2_CMD_STAT       0x00019158  /* ct       */
0119 #define LPU1_HOSTFN2_CMD_STAT       0x0001915c  /* ct       */
0120 #define LPU0_HOSTFN3_CMD_STAT       0x00019168  /* ct       */
0121 #define LPU1_HOSTFN3_CMD_STAT       0x0001916c  /* ct       */
0122 
0123 #define PSS_CTL_REG         0x00018800  /* cb/ct    */
0124 #define __PSS_I2C_CLK_DIV_MK        0x007f0000
0125 #define __PSS_I2C_CLK_DIV_SH        16
0126 #define __PSS_I2C_CLK_DIV(_v)       ((_v) << __PSS_I2C_CLK_DIV_SH)
0127 #define __PSS_LMEM_INIT_DONE        0x00001000
0128 #define __PSS_LMEM_RESET        0x00000200
0129 #define __PSS_LMEM_INIT_EN      0x00000100
0130 #define __PSS_LPU1_RESET        0x00000002
0131 #define __PSS_LPU0_RESET        0x00000001
0132 #define PSS_ERR_STATUS_REG      0x00018810  /* cb/ct    */
0133 #define ERR_SET_REG         0x00018818  /* cb/ct    */
0134 #define PSS_GPIO_OUT_REG        0x000188c0  /* cb/ct    */
0135 #define __PSS_GPIO_OUT_REG      0x00000fff
0136 #define PSS_GPIO_OE_REG         0x000188c8  /* cb/ct    */
0137 #define __PSS_GPIO_OE_REG       0x000000ff
0138 
0139 #define HOSTFN0_LPU_MBOX0_0     0x00019200  /* cb/ct    */
0140 #define HOSTFN1_LPU_MBOX0_8     0x00019260  /* cb/ct    */
0141 #define LPU_HOSTFN0_MBOX0_0     0x00019280  /* cb/ct    */
0142 #define LPU_HOSTFN1_MBOX0_8     0x000192e0  /* cb/ct    */
0143 #define HOSTFN2_LPU_MBOX0_0     0x00019400  /* ct       */
0144 #define HOSTFN3_LPU_MBOX0_8     0x00019460  /* ct       */
0145 #define LPU_HOSTFN2_MBOX0_0     0x00019480  /* ct       */
0146 #define LPU_HOSTFN3_MBOX0_8     0x000194e0  /* ct       */
0147 
0148 #define HOST_MSIX_ERR_INDEX_FN0     0x0001400c  /* ct       */
0149 #define HOST_MSIX_ERR_INDEX_FN1     0x0001410c  /* ct       */
0150 #define HOST_MSIX_ERR_INDEX_FN2     0x0001430c  /* ct       */
0151 #define HOST_MSIX_ERR_INDEX_FN3     0x0001440c  /* ct       */
0152 
0153 #define MBIST_CTL_REG           0x00014220  /* ct       */
0154 #define __EDRAM_BISTR_START     0x00000004
0155 #define MBIST_STAT_REG          0x00014224  /* ct       */
0156 #define ETH_MAC_SER_REG         0x00014288  /* ct       */
0157 #define __APP_EMS_CKBUFAMPIN        0x00000020
0158 #define __APP_EMS_REFCLKSEL     0x00000010
0159 #define __APP_EMS_CMLCKSEL      0x00000008
0160 #define __APP_EMS_REFCKBUFEN2       0x00000004
0161 #define __APP_EMS_REFCKBUFEN1       0x00000002
0162 #define __APP_EMS_CHANNEL_SEL       0x00000001
0163 #define FNC_PERS_REG            0x00014604  /* ct       */
0164 #define __F3_FUNCTION_ACTIVE        0x80000000
0165 #define __F3_FUNCTION_MODE      0x40000000
0166 #define __F3_PORT_MAP_MK        0x30000000
0167 #define __F3_PORT_MAP_SH        28
0168 #define __F3_PORT_MAP(_v)       ((_v) << __F3_PORT_MAP_SH)
0169 #define __F3_VM_MODE            0x08000000
0170 #define __F3_INTX_STATUS_MK     0x07000000
0171 #define __F3_INTX_STATUS_SH     24
0172 #define __F3_INTX_STATUS(_v)        ((_v) << __F3_INTX_STATUS_SH)
0173 #define __F2_FUNCTION_ACTIVE        0x00800000
0174 #define __F2_FUNCTION_MODE      0x00400000
0175 #define __F2_PORT_MAP_MK        0x00300000
0176 #define __F2_PORT_MAP_SH        20
0177 #define __F2_PORT_MAP(_v)       ((_v) << __F2_PORT_MAP_SH)
0178 #define __F2_VM_MODE            0x00080000
0179 #define __F2_INTX_STATUS_MK     0x00070000
0180 #define __F2_INTX_STATUS_SH     16
0181 #define __F2_INTX_STATUS(_v)        ((_v) << __F2_INTX_STATUS_SH)
0182 #define __F1_FUNCTION_ACTIVE        0x00008000
0183 #define __F1_FUNCTION_MODE      0x00004000
0184 #define __F1_PORT_MAP_MK        0x00003000
0185 #define __F1_PORT_MAP_SH        12
0186 #define __F1_PORT_MAP(_v)       ((_v) << __F1_PORT_MAP_SH)
0187 #define __F1_VM_MODE            0x00000800
0188 #define __F1_INTX_STATUS_MK     0x00000700
0189 #define __F1_INTX_STATUS_SH     8
0190 #define __F1_INTX_STATUS(_v)        ((_v) << __F1_INTX_STATUS_SH)
0191 #define __F0_FUNCTION_ACTIVE        0x00000080
0192 #define __F0_FUNCTION_MODE      0x00000040
0193 #define __F0_PORT_MAP_MK        0x00000030
0194 #define __F0_PORT_MAP_SH        4
0195 #define __F0_PORT_MAP(_v)       ((_v) << __F0_PORT_MAP_SH)
0196 #define __F0_VM_MODE            0x00000008
0197 #define __F0_INTX_STATUS        0x00000007
0198 enum {
0199     __F0_INTX_STATUS_MSIX = 0x0,
0200     __F0_INTX_STATUS_INTA = 0x1,
0201     __F0_INTX_STATUS_INTB = 0x2,
0202     __F0_INTX_STATUS_INTC = 0x3,
0203     __F0_INTX_STATUS_INTD = 0x4,
0204 };
0205 
0206 #define OP_MODE             0x0001460c
0207 #define __APP_ETH_CLK_LOWSPEED      0x00000004
0208 #define __GLOBAL_CORECLK_HALFSPEED  0x00000002
0209 #define __GLOBAL_FCOE_MODE      0x00000001
0210 #define FW_INIT_HALT_P0         0x000191ac
0211 #define __FW_INIT_HALT_P        0x00000001
0212 #define FW_INIT_HALT_P1         0x000191bc
0213 #define PMM_1T_RESET_REG_P0     0x0002381c
0214 #define __PMM_1T_RESET_P        0x00000001
0215 #define PMM_1T_RESET_REG_P1     0x00023c1c
0216 
0217 /* QLogic BR-series 1860 Adapter specific defines */
0218 #define CT2_PCI_CPQ_BASE        0x00030000
0219 #define CT2_PCI_APP_BASE        0x00030100
0220 #define CT2_PCI_ETH_BASE        0x00030400
0221 
0222 /*
0223  * APP block registers
0224  */
0225 #define CT2_HOSTFN_INT_STATUS       (CT2_PCI_APP_BASE + 0x00)
0226 #define CT2_HOSTFN_INTR_MASK        (CT2_PCI_APP_BASE + 0x04)
0227 #define CT2_HOSTFN_PERSONALITY0     (CT2_PCI_APP_BASE + 0x08)
0228 #define __PME_STATUS_           0x00200000
0229 #define __PF_VF_BAR_SIZE_MODE__MK   0x00180000
0230 #define __PF_VF_BAR_SIZE_MODE__SH   19
0231 #define __PF_VF_BAR_SIZE_MODE_(_v)  ((_v) << __PF_VF_BAR_SIZE_MODE__SH)
0232 #define __FC_LL_PORT_MAP__MK        0x00060000
0233 #define __FC_LL_PORT_MAP__SH        17
0234 #define __FC_LL_PORT_MAP_(_v)       ((_v) << __FC_LL_PORT_MAP__SH)
0235 #define __PF_VF_ACTIVE_         0x00010000
0236 #define __PF_VF_CFG_RDY_        0x00008000
0237 #define __PF_VF_ENABLE_         0x00004000
0238 #define __PF_DRIVER_ACTIVE_     0x00002000
0239 #define __PF_PME_SEND_ENABLE_       0x00001000
0240 #define __PF_EXROM_OFFSET__MK       0x00000ff0
0241 #define __PF_EXROM_OFFSET__SH       4
0242 #define __PF_EXROM_OFFSET_(_v)      ((_v) << __PF_EXROM_OFFSET__SH)
0243 #define __FC_LL_MODE_           0x00000008
0244 #define __PF_INTX_PIN_          0x00000007
0245 #define CT2_HOSTFN_PERSONALITY1     (CT2_PCI_APP_BASE + 0x0C)
0246 #define __PF_NUM_QUEUES1__MK        0xff000000
0247 #define __PF_NUM_QUEUES1__SH        24
0248 #define __PF_NUM_QUEUES1_(_v)       ((_v) << __PF_NUM_QUEUES1__SH)
0249 #define __PF_VF_QUE_OFFSET1__MK     0x00ff0000
0250 #define __PF_VF_QUE_OFFSET1__SH     16
0251 #define __PF_VF_QUE_OFFSET1_(_v)    ((_v) << __PF_VF_QUE_OFFSET1__SH)
0252 #define __PF_VF_NUM_QUEUES__MK      0x0000ff00
0253 #define __PF_VF_NUM_QUEUES__SH      8
0254 #define __PF_VF_NUM_QUEUES_(_v)     ((_v) << __PF_VF_NUM_QUEUES__SH)
0255 #define __PF_VF_QUE_OFFSET_     0x000000ff
0256 #define CT2_HOSTFN_PAGE_NUM     (CT2_PCI_APP_BASE + 0x18)
0257 #define CT2_HOSTFN_MSIX_VT_INDEX_MBOX_ERR   (CT2_PCI_APP_BASE + 0x38)
0258 
0259 /*
0260  * QLogic BR-series 1860 adapter CPQ block registers
0261  */
0262 #define CT2_HOSTFN_LPU0_MBOX0       (CT2_PCI_CPQ_BASE + 0x00)
0263 #define CT2_HOSTFN_LPU1_MBOX0       (CT2_PCI_CPQ_BASE + 0x20)
0264 #define CT2_LPU0_HOSTFN_MBOX0       (CT2_PCI_CPQ_BASE + 0x40)
0265 #define CT2_LPU1_HOSTFN_MBOX0       (CT2_PCI_CPQ_BASE + 0x60)
0266 #define CT2_HOSTFN_LPU0_CMD_STAT    (CT2_PCI_CPQ_BASE + 0x80)
0267 #define CT2_HOSTFN_LPU1_CMD_STAT    (CT2_PCI_CPQ_BASE + 0x84)
0268 #define CT2_LPU0_HOSTFN_CMD_STAT    (CT2_PCI_CPQ_BASE + 0x88)
0269 #define CT2_LPU1_HOSTFN_CMD_STAT    (CT2_PCI_CPQ_BASE + 0x8c)
0270 #define CT2_HOSTFN_LPU0_READ_STAT   (CT2_PCI_CPQ_BASE + 0x90)
0271 #define CT2_HOSTFN_LPU1_READ_STAT   (CT2_PCI_CPQ_BASE + 0x94)
0272 #define CT2_LPU0_HOSTFN_MBOX0_MSK   (CT2_PCI_CPQ_BASE + 0x98)
0273 #define CT2_LPU1_HOSTFN_MBOX0_MSK   (CT2_PCI_CPQ_BASE + 0x9C)
0274 #define CT2_HOST_SEM0_REG       0x000148f0
0275 #define CT2_HOST_SEM1_REG       0x000148f4
0276 #define CT2_HOST_SEM2_REG       0x000148f8
0277 #define CT2_HOST_SEM3_REG       0x000148fc
0278 #define CT2_HOST_SEM4_REG       0x00014900
0279 #define CT2_HOST_SEM5_REG       0x00014904
0280 #define CT2_HOST_SEM6_REG       0x00014908
0281 #define CT2_HOST_SEM7_REG       0x0001490c
0282 #define CT2_HOST_SEM0_INFO_REG      0x000148b0
0283 #define CT2_HOST_SEM1_INFO_REG      0x000148b4
0284 #define CT2_HOST_SEM2_INFO_REG      0x000148b8
0285 #define CT2_HOST_SEM3_INFO_REG      0x000148bc
0286 #define CT2_HOST_SEM4_INFO_REG      0x000148c0
0287 #define CT2_HOST_SEM5_INFO_REG      0x000148c4
0288 #define CT2_HOST_SEM6_INFO_REG      0x000148c8
0289 #define CT2_HOST_SEM7_INFO_REG      0x000148cc
0290 
0291 #define CT2_APP_PLL_LCLK_CTL_REG    0x00014808
0292 #define __APP_LPUCLK_HALFSPEED      0x40000000
0293 #define __APP_PLL_LCLK_LOAD     0x20000000
0294 #define __APP_PLL_LCLK_FBCNT_MK     0x1fe00000
0295 #define __APP_PLL_LCLK_FBCNT_SH     21
0296 #define __APP_PLL_LCLK_FBCNT(_v)    ((_v) << __APP_PLL_SCLK_FBCNT_SH)
0297 enum {
0298     __APP_PLL_LCLK_FBCNT_425_MHZ = 6,
0299     __APP_PLL_LCLK_FBCNT_468_MHZ = 4,
0300 };
0301 #define __APP_PLL_LCLK_EXTFB        0x00000800
0302 #define __APP_PLL_LCLK_ENOUTS       0x00000400
0303 #define __APP_PLL_LCLK_RATE     0x00000010
0304 #define CT2_APP_PLL_SCLK_CTL_REG    0x0001480c
0305 #define __P_SCLK_PLL_LOCK       0x80000000
0306 #define __APP_PLL_SCLK_REFCLK_SEL   0x40000000
0307 #define __APP_PLL_SCLK_CLK_DIV2     0x20000000
0308 #define __APP_PLL_SCLK_LOAD     0x10000000
0309 #define __APP_PLL_SCLK_FBCNT_MK     0x0ff00000
0310 #define __APP_PLL_SCLK_FBCNT_SH     20
0311 #define __APP_PLL_SCLK_FBCNT(_v)    ((_v) << __APP_PLL_SCLK_FBCNT_SH)
0312 enum {
0313     __APP_PLL_SCLK_FBCNT_NORM = 6,
0314     __APP_PLL_SCLK_FBCNT_10G_FC = 10,
0315 };
0316 #define __APP_PLL_SCLK_EXTFB        0x00000800
0317 #define __APP_PLL_SCLK_ENOUTS       0x00000400
0318 #define __APP_PLL_SCLK_RATE     0x00000010
0319 #define CT2_PCIE_MISC_REG       0x00014804
0320 #define __ETH_CLK_ENABLE_PORT1      0x00000010
0321 #define CT2_CHIP_MISC_PRG       0x000148a4
0322 #define __ETH_CLK_ENABLE_PORT0      0x00004000
0323 #define __APP_LPU_SPEED         0x00000002
0324 #define CT2_MBIST_STAT_REG      0x00014818
0325 #define CT2_MBIST_CTL_REG       0x0001481c
0326 #define CT2_PMM_1T_CONTROL_REG_P0   0x0002381c
0327 #define __PMM_1T_PNDB_P         0x00000002
0328 #define CT2_PMM_1T_CONTROL_REG_P1   0x00023c1c
0329 #define CT2_WGN_STATUS          0x00014990
0330 #define __A2T_AHB_LOAD          0x00000800
0331 #define __WGN_READY         0x00000400
0332 #define __GLBL_PF_VF_CFG_RDY        0x00000200
0333 #define CT2_NFC_CSR_CLR_REG             0x00027420
0334 #define CT2_NFC_CSR_SET_REG     0x00027424
0335 #define __HALT_NFC_CONTROLLER       0x00000002
0336 #define __NFC_CONTROLLER_HALTED     0x00001000
0337 
0338 #define CT2_RSC_GPR15_REG       0x0002765c
0339 #define CT2_CSI_FW_CTL_REG              0x00027080
0340 #define __RESET_AND_START_SCLK_LCLK_PLLS 0x00010000
0341 #define CT2_CSI_FW_CTL_SET_REG          0x00027088
0342 
0343 #define CT2_CSI_MAC0_CONTROL_REG    0x000270d0
0344 #define __CSI_MAC_RESET         0x00000010
0345 #define __CSI_MAC_AHB_RESET     0x00000008
0346 #define CT2_CSI_MAC1_CONTROL_REG    0x000270d4
0347 #define CT2_CSI_MAC_CONTROL_REG(__n) \
0348     (CT2_CSI_MAC0_CONTROL_REG + \
0349     (__n) * (CT2_CSI_MAC1_CONTROL_REG - CT2_CSI_MAC0_CONTROL_REG))
0350 
0351 /*
0352  * Name semaphore registers based on usage
0353  */
0354 #define BFA_IOC0_HBEAT_REG      HOST_SEM0_INFO_REG
0355 #define BFA_IOC0_STATE_REG      HOST_SEM1_INFO_REG
0356 #define BFA_IOC1_HBEAT_REG      HOST_SEM2_INFO_REG
0357 #define BFA_IOC1_STATE_REG      HOST_SEM3_INFO_REG
0358 #define BFA_FW_USE_COUNT        HOST_SEM4_INFO_REG
0359 #define BFA_IOC_FAIL_SYNC       HOST_SEM5_INFO_REG
0360 
0361 /*
0362  * CT2 semaphore register locations changed
0363  */
0364 #define CT2_BFA_IOC0_HBEAT_REG      CT2_HOST_SEM0_INFO_REG
0365 #define CT2_BFA_IOC0_STATE_REG      CT2_HOST_SEM1_INFO_REG
0366 #define CT2_BFA_IOC1_HBEAT_REG      CT2_HOST_SEM2_INFO_REG
0367 #define CT2_BFA_IOC1_STATE_REG      CT2_HOST_SEM3_INFO_REG
0368 #define CT2_BFA_FW_USE_COUNT        CT2_HOST_SEM4_INFO_REG
0369 #define CT2_BFA_IOC_FAIL_SYNC       CT2_HOST_SEM5_INFO_REG
0370 
0371 #define CPE_Q_NUM(__fn, __q)    (((__fn) << 2) + (__q))
0372 #define RME_Q_NUM(__fn, __q)    (((__fn) << 2) + (__q))
0373 
0374 /*
0375  * And corresponding host interrupt status bit field defines
0376  */
0377 #define __HFN_INT_CPE_Q0    0x00000001U
0378 #define __HFN_INT_CPE_Q1    0x00000002U
0379 #define __HFN_INT_CPE_Q2    0x00000004U
0380 #define __HFN_INT_CPE_Q3    0x00000008U
0381 #define __HFN_INT_CPE_Q4    0x00000010U
0382 #define __HFN_INT_CPE_Q5    0x00000020U
0383 #define __HFN_INT_CPE_Q6    0x00000040U
0384 #define __HFN_INT_CPE_Q7    0x00000080U
0385 #define __HFN_INT_RME_Q0    0x00000100U
0386 #define __HFN_INT_RME_Q1    0x00000200U
0387 #define __HFN_INT_RME_Q2    0x00000400U
0388 #define __HFN_INT_RME_Q3    0x00000800U
0389 #define __HFN_INT_RME_Q4    0x00001000U
0390 #define __HFN_INT_RME_Q5    0x00002000U
0391 #define __HFN_INT_RME_Q6    0x00004000U
0392 #define __HFN_INT_RME_Q7    0x00008000U
0393 #define __HFN_INT_ERR_EMC   0x00010000U
0394 #define __HFN_INT_ERR_LPU0  0x00020000U
0395 #define __HFN_INT_ERR_LPU1  0x00040000U
0396 #define __HFN_INT_ERR_PSS   0x00080000U
0397 #define __HFN_INT_MBOX_LPU0 0x00100000U
0398 #define __HFN_INT_MBOX_LPU1 0x00200000U
0399 #define __HFN_INT_MBOX1_LPU0    0x00400000U
0400 #define __HFN_INT_MBOX1_LPU1    0x00800000U
0401 #define __HFN_INT_LL_HALT   0x01000000U
0402 #define __HFN_INT_CPE_MASK  0x000000ffU
0403 #define __HFN_INT_RME_MASK  0x0000ff00U
0404 #define __HFN_INT_ERR_MASK  \
0405     (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 | __HFN_INT_ERR_LPU1 | \
0406      __HFN_INT_ERR_PSS | __HFN_INT_LL_HALT)
0407 #define __HFN_INT_FN0_MASK  \
0408     (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \
0409      __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \
0410      __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0)
0411 #define __HFN_INT_FN1_MASK  \
0412     (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \
0413      __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \
0414      __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1)
0415 
0416 /*
0417  * Host interrupt status defines for 1860
0418  */
0419 #define __HFN_INT_MBOX_LPU0_CT2 0x00010000U
0420 #define __HFN_INT_MBOX_LPU1_CT2 0x00020000U
0421 #define __HFN_INT_ERR_PSS_CT2   0x00040000U
0422 #define __HFN_INT_ERR_LPU0_CT2  0x00080000U
0423 #define __HFN_INT_ERR_LPU1_CT2  0x00100000U
0424 #define __HFN_INT_CPQ_HALT_CT2  0x00200000U
0425 #define __HFN_INT_ERR_WGN_CT2   0x00400000U
0426 #define __HFN_INT_ERR_LEHRX_CT2 0x00800000U
0427 #define __HFN_INT_ERR_LEHTX_CT2 0x01000000U
0428 #define __HFN_INT_ERR_MASK_CT2  \
0429     (__HFN_INT_ERR_PSS_CT2 | __HFN_INT_ERR_LPU0_CT2 | \
0430      __HFN_INT_ERR_LPU1_CT2 | __HFN_INT_CPQ_HALT_CT2 | \
0431      __HFN_INT_ERR_WGN_CT2 | __HFN_INT_ERR_LEHRX_CT2 | \
0432      __HFN_INT_ERR_LEHTX_CT2)
0433 #define __HFN_INT_FN0_MASK_CT2  \
0434     (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 | __HFN_INT_CPE_Q2 | \
0435      __HFN_INT_CPE_Q3 | __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 | \
0436      __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 | __HFN_INT_MBOX_LPU0_CT2)
0437 #define __HFN_INT_FN1_MASK_CT2  \
0438     (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 | __HFN_INT_CPE_Q6 | \
0439      __HFN_INT_CPE_Q7 | __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 | \
0440      __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 | __HFN_INT_MBOX_LPU1_CT2)
0441 
0442 /*
0443  * asic memory map.
0444  */
0445 #define PSS_SMEM_PAGE_START     0x8000
0446 #define PSS_SMEM_PGNUM(_pg0, _ma)   ((_pg0) + ((_ma) >> 15))
0447 #define PSS_SMEM_PGOFF(_ma)     ((_ma) & 0x7fff)
0448 
0449 #endif /* __BFI_REG_H__ */
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