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0012 #ifndef __BFA_DEFS_H__
0013 #define __BFA_DEFS_H__
0014
0015 #include "cna.h"
0016 #include "bfa_defs_status.h"
0017 #include "bfa_defs_mfg_comm.h"
0018
0019 #define BFA_VERSION_LEN 64
0020
0021
0022
0023
0024 enum {
0025 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE),
0026
0027
0028
0029 BFA_ADAPTER_MODEL_NAME_LEN = 16,
0030 BFA_ADAPTER_MODEL_DESCR_LEN = 128,
0031 BFA_ADAPTER_MFG_NAME_LEN = 8,
0032 BFA_ADAPTER_SYM_NAME_LEN = 64,
0033 BFA_ADAPTER_OS_TYPE_LEN = 64,
0034 };
0035
0036 struct bfa_adapter_attr {
0037 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN];
0038 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
0039 u32 card_type;
0040 char model[BFA_ADAPTER_MODEL_NAME_LEN];
0041 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN];
0042 u64 pwwn;
0043 char node_symname[FC_SYMNAME_MAX];
0044 char hw_ver[BFA_VERSION_LEN];
0045 char fw_ver[BFA_VERSION_LEN];
0046 char optrom_ver[BFA_VERSION_LEN];
0047 char os_type[BFA_ADAPTER_OS_TYPE_LEN];
0048 struct bfa_mfg_vpd vpd;
0049 u8 mac[ETH_ALEN];
0050
0051 u8 nports;
0052 u8 max_speed;
0053 u8 prototype;
0054 char asic_rev;
0055
0056 u8 pcie_gen;
0057 u8 pcie_lanes_orig;
0058 u8 pcie_lanes;
0059 u8 cna_capable;
0060
0061 u8 is_mezz;
0062 u8 trunk_capable;
0063 };
0064
0065
0066
0067 enum {
0068 BFA_IOC_DRIVER_LEN = 16,
0069 BFA_IOC_CHIP_REV_LEN = 8,
0070 };
0071
0072
0073 struct bfa_ioc_driver_attr {
0074 char driver[BFA_IOC_DRIVER_LEN];
0075 char driver_ver[BFA_VERSION_LEN];
0076 char fw_ver[BFA_VERSION_LEN];
0077 char bios_ver[BFA_VERSION_LEN];
0078 char efi_ver[BFA_VERSION_LEN];
0079 char ob_ver[BFA_VERSION_LEN];
0080 };
0081
0082
0083 struct bfa_ioc_pci_attr {
0084 u16 vendor_id;
0085 u16 device_id;
0086 u16 ssid;
0087 u16 ssvid;
0088 u32 pcifn;
0089 u32 rsvd;
0090 char chip_rev[BFA_IOC_CHIP_REV_LEN];
0091 };
0092
0093
0094 enum bfa_ioc_state {
0095 BFA_IOC_UNINIT = 1,
0096 BFA_IOC_RESET = 2,
0097 BFA_IOC_SEMWAIT = 3,
0098 BFA_IOC_HWINIT = 4,
0099 BFA_IOC_GETATTR = 5,
0100 BFA_IOC_OPERATIONAL = 6,
0101 BFA_IOC_INITFAIL = 7,
0102 BFA_IOC_FAIL = 8,
0103 BFA_IOC_DISABLING = 9,
0104 BFA_IOC_DISABLED = 10,
0105 BFA_IOC_FWMISMATCH = 11,
0106 BFA_IOC_ENABLING = 12,
0107 BFA_IOC_HWFAIL = 13,
0108 };
0109
0110
0111 struct bfa_fw_ioc_stats {
0112 u32 enable_reqs;
0113 u32 disable_reqs;
0114 u32 get_attr_reqs;
0115 u32 dbg_sync;
0116 u32 dbg_dump;
0117 u32 unknown_reqs;
0118 };
0119
0120
0121 struct bfa_ioc_drv_stats {
0122 u32 ioc_isrs;
0123 u32 ioc_enables;
0124 u32 ioc_disables;
0125 u32 ioc_hbfails;
0126 u32 ioc_boots;
0127 u32 stats_tmos;
0128 u32 hb_count;
0129 u32 disable_reqs;
0130 u32 enable_reqs;
0131 u32 disable_replies;
0132 u32 enable_replies;
0133 u32 rsvd;
0134 };
0135
0136
0137 struct bfa_ioc_stats {
0138 struct bfa_ioc_drv_stats drv_stats;
0139 struct bfa_fw_ioc_stats fw_stats;
0140 };
0141
0142 enum bfa_ioc_type {
0143 BFA_IOC_TYPE_FC = 1,
0144 BFA_IOC_TYPE_FCoE = 2,
0145 BFA_IOC_TYPE_LL = 3,
0146 };
0147
0148
0149 struct bfa_ioc_attr {
0150 enum bfa_ioc_type ioc_type;
0151 enum bfa_ioc_state state;
0152 struct bfa_adapter_attr adapter_attr;
0153 struct bfa_ioc_driver_attr driver_attr;
0154 struct bfa_ioc_pci_attr pci_attr;
0155 u8 port_id;
0156 u8 port_mode;
0157 u8 cap_bm;
0158 u8 port_mode_cfg;
0159 u8 def_fn;
0160 u8 rsvd[3];
0161 };
0162
0163
0164 enum {
0165 BFA_CM_HBA = 0x01,
0166 BFA_CM_CNA = 0x02,
0167 BFA_CM_NIC = 0x04,
0168 };
0169
0170
0171
0172
0173 #define BFA_MFG_CHKSUM_SIZE 16
0174
0175 #define BFA_MFG_PARTNUM_SIZE 14
0176 #define BFA_MFG_SUPPLIER_ID_SIZE 10
0177 #define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20
0178 #define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20
0179 #define BFA_MFG_SUPPLIER_REVISION_SIZE 4
0180
0181
0182
0183
0184
0185 struct bfa_mfg_block {
0186 u8 version;
0187 u8 mfg_sig[3];
0188 u16 mfgsize;
0189 u16 u16_chksum;
0190 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
0191 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)];
0192 u8 mfg_day;
0193 u8 mfg_month;
0194 u16 mfg_year;
0195 u64 mfg_wwn;
0196 u8 num_wwn;
0197 u8 mfg_speeds;
0198 u8 rsv[2];
0199 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)];
0200 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)];
0201 char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)];
0202 char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)];
0203 u8 mfg_mac[ETH_ALEN];
0204 u8 num_mac;
0205 u8 rsv2;
0206 u32 card_type;
0207 char cap_nic;
0208 char cap_cna;
0209 char cap_hba;
0210 char cap_fc16g;
0211 char cap_sriov;
0212 char cap_mezz;
0213 u8 rsv3;
0214 u8 mfg_nports;
0215 char media[8];
0216 char initial_mode[8];
0217 u8 rsv4[84];
0218 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE];
0219 } __packed;
0220
0221
0222
0223
0224
0225
0226 enum {
0227 BFA_PCI_DEVICE_ID_CT2 = 0x22,
0228 };
0229
0230 #define bfa_asic_id_ct(device) \
0231 ((device) == PCI_DEVICE_ID_BROCADE_CT || \
0232 (device) == PCI_DEVICE_ID_BROCADE_CT_FC)
0233 #define bfa_asic_id_ct2(device) \
0234 ((device) == BFA_PCI_DEVICE_ID_CT2)
0235 #define bfa_asic_id_ctc(device) \
0236 (bfa_asic_id_ct(device) || bfa_asic_id_ct2(device))
0237
0238
0239 enum {
0240 BFA_PCI_FCOE_SSDEVICE_ID = 0x14,
0241 BFA_PCI_CT2_SSID_FCoE = 0x22,
0242 BFA_PCI_CT2_SSID_ETH = 0x23,
0243 BFA_PCI_CT2_SSID_FC = 0x24,
0244 };
0245
0246 enum bfa_mode {
0247 BFA_MODE_HBA = 1,
0248 BFA_MODE_CNA = 2,
0249 BFA_MODE_NIC = 3
0250 };
0251
0252
0253
0254
0255 #define BFA_FLASH_PART_ENTRY_SIZE 32
0256 #define BFA_FLASH_PART_MAX 32
0257 #define BFA_TOTAL_FLASH_SIZE 0x400000
0258 #define BFA_FLASH_PART_FWIMG 2
0259 #define BFA_FLASH_PART_MFG 7
0260
0261
0262
0263
0264 struct bfa_flash_part_attr {
0265 u32 part_type;
0266 u32 part_instance;
0267 u32 part_off;
0268 u32 part_size;
0269 u32 part_len;
0270 u32 part_status;
0271 char rsv[BFA_FLASH_PART_ENTRY_SIZE - 24];
0272 };
0273
0274
0275
0276
0277 struct bfa_flash_attr {
0278 u32 status;
0279 u32 npart;
0280 struct bfa_flash_part_attr part[BFA_FLASH_PART_MAX];
0281 };
0282
0283 #endif