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0013 #ifndef CNIC_H
0014 #define CNIC_H
0015
0016 #define HC_INDEX_ISCSI_EQ_CONS 6
0017
0018 #define HC_INDEX_FCOE_EQ_CONS 3
0019
0020 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
0021 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
0022
0023 #define KWQ_PAGE_CNT 4
0024 #define KCQ_PAGE_CNT 16
0025
0026 #define KWQ_CID 24
0027 #define KCQ_CID 25
0028
0029
0030
0031
0032 #define L5_KRNLQ_FLAGS 0x00000000
0033 #define L5_KRNLQ_SIZE 0x00000000
0034 #define L5_KRNLQ_TYPE 0x00000000
0035 #define KRNLQ_FLAGS_PG_SZ (0xf<<0)
0036 #define KRNLQ_FLAGS_PG_SZ_256 (0<<0)
0037 #define KRNLQ_FLAGS_PG_SZ_512 (1<<0)
0038 #define KRNLQ_FLAGS_PG_SZ_1K (2<<0)
0039 #define KRNLQ_FLAGS_PG_SZ_2K (3<<0)
0040 #define KRNLQ_FLAGS_PG_SZ_4K (4<<0)
0041 #define KRNLQ_FLAGS_PG_SZ_8K (5<<0)
0042 #define KRNLQ_FLAGS_PG_SZ_16K (6<<0)
0043 #define KRNLQ_FLAGS_PG_SZ_32K (7<<0)
0044 #define KRNLQ_FLAGS_PG_SZ_64K (8<<0)
0045 #define KRNLQ_FLAGS_PG_SZ_128K (9<<0)
0046 #define KRNLQ_FLAGS_PG_SZ_256K (10<<0)
0047 #define KRNLQ_FLAGS_PG_SZ_512K (11<<0)
0048 #define KRNLQ_FLAGS_PG_SZ_1M (12<<0)
0049 #define KRNLQ_FLAGS_PG_SZ_2M (13<<0)
0050 #define KRNLQ_FLAGS_QE_SELF_SEQ (1<<15)
0051 #define KRNLQ_SIZE_TYPE_SIZE ((((0x28 + 0x1f) & ~0x1f) / 0x20) << 16)
0052 #define KRNLQ_TYPE_TYPE (0xf<<28)
0053 #define KRNLQ_TYPE_TYPE_EMPTY (0<<28)
0054 #define KRNLQ_TYPE_TYPE_KRNLQ (6<<28)
0055
0056 #define L5_KRNLQ_HOST_QIDX 0x00000004
0057 #define L5_KRNLQ_HOST_FW_QIDX 0x00000008
0058 #define L5_KRNLQ_NX_QE_SELF_SEQ 0x0000000c
0059 #define L5_KRNLQ_QE_SELF_SEQ_MAX 0x0000000c
0060 #define L5_KRNLQ_NX_QE_HADDR_HI 0x00000010
0061 #define L5_KRNLQ_NX_QE_HADDR_LO 0x00000014
0062 #define L5_KRNLQ_PGTBL_PGIDX 0x00000018
0063 #define L5_KRNLQ_NX_PG_QIDX 0x00000018
0064 #define L5_KRNLQ_PGTBL_NPAGES 0x0000001c
0065 #define L5_KRNLQ_QIDX_INCR 0x0000001c
0066 #define L5_KRNLQ_PGTBL_HADDR_HI 0x00000020
0067 #define L5_KRNLQ_PGTBL_HADDR_LO 0x00000024
0068
0069 #define BNX2_PG_CTX_MAP 0x1a0034
0070 #define BNX2_ISCSI_CTX_MAP 0x1a0074
0071
0072 #define MAX_COMPLETED_KCQE 64
0073
0074 #define MAX_CNIC_L5_CONTEXT 256
0075
0076 #define MAX_CM_SK_TBL_SZ MAX_CNIC_L5_CONTEXT
0077
0078 #define MAX_ISCSI_TBL_SZ 256
0079
0080 #define CNIC_LOCAL_PORT_MIN 60000
0081 #define CNIC_LOCAL_PORT_MAX 61024
0082 #define CNIC_LOCAL_PORT_RANGE (CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN)
0083
0084 #define KWQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kwqe))
0085 #define KCQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kcqe))
0086 #define MAX_KWQE_CNT (KWQE_CNT - 1)
0087 #define MAX_KCQE_CNT (KCQE_CNT - 1)
0088
0089 #define MAX_KWQ_IDX ((KWQ_PAGE_CNT * KWQE_CNT) - 1)
0090 #define MAX_KCQ_IDX ((KCQ_PAGE_CNT * KCQE_CNT) - 1)
0091
0092 #define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BNX2_PAGE_BITS - 5))
0093 #define KWQ_IDX(x) ((x) & MAX_KWQE_CNT)
0094
0095 #define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BNX2_PAGE_BITS - 5))
0096 #define KCQ_IDX(x) ((x) & MAX_KCQE_CNT)
0097
0098 #define BNX2X_NEXT_KCQE(x) (((x) & (MAX_KCQE_CNT - 1)) == \
0099 (MAX_KCQE_CNT - 1)) ? \
0100 (x) + 2 : (x) + 1
0101
0102 #define BNX2X_KWQ_DATA_PG(cp, x) ((x) / (cp)->kwq_16_data_pp)
0103 #define BNX2X_KWQ_DATA_IDX(cp, x) ((x) % (cp)->kwq_16_data_pp)
0104 #define BNX2X_KWQ_DATA(cp, x) \
0105 &(cp)->kwq_16_data[BNX2X_KWQ_DATA_PG(cp, x)][BNX2X_KWQ_DATA_IDX(cp, x)]
0106
0107 #define DEF_IPID_START 0x8000
0108
0109 #define DEF_KA_TIMEOUT 10000
0110 #define DEF_KA_INTERVAL 300000
0111 #define DEF_KA_MAX_PROBE_COUNT 3
0112 #define DEF_TOS 0
0113 #define DEF_TTL 0xfe
0114 #define DEF_SND_SEQ_SCALE 0
0115 #define DEF_RCV_BUF 0xffff
0116 #define DEF_SND_BUF 0xffff
0117 #define DEF_SEED 0
0118 #define DEF_MAX_RT_TIME 500
0119 #define DEF_MAX_DA_COUNT 2
0120 #define DEF_SWS_TIMER 1000
0121 #define DEF_MAX_CWND 0xffff
0122
0123 struct cnic_ctx {
0124 u32 cid;
0125 void *ctx;
0126 dma_addr_t mapping;
0127 };
0128
0129 #define BNX2_MAX_CID 0x2000
0130
0131 struct cnic_dma {
0132 int num_pages;
0133 void **pg_arr;
0134 dma_addr_t *pg_map_arr;
0135 int pgtbl_size;
0136 u32 *pgtbl;
0137 dma_addr_t pgtbl_map;
0138 };
0139
0140 struct cnic_id_tbl {
0141 spinlock_t lock;
0142 u32 start;
0143 u32 max;
0144 u32 next;
0145 unsigned long *table;
0146 };
0147
0148 #define CNIC_KWQ16_DATA_SIZE 128
0149
0150 struct kwqe_16_data {
0151 u8 data[CNIC_KWQ16_DATA_SIZE];
0152 };
0153
0154 struct cnic_iscsi {
0155 struct cnic_dma task_array_info;
0156 struct cnic_dma r2tq_info;
0157 struct cnic_dma hq_info;
0158 };
0159
0160 struct cnic_context {
0161 u32 cid;
0162 struct kwqe_16_data *kwqe_data;
0163 dma_addr_t kwqe_data_mapping;
0164 wait_queue_head_t waitq;
0165 int wait_cond;
0166 unsigned long timestamp;
0167 unsigned long ctx_flags;
0168 #define CTX_FL_OFFLD_START 0
0169 #define CTX_FL_DELETE_WAIT 1
0170 #define CTX_FL_CID_ERROR 2
0171 u8 ulp_proto_id;
0172 union {
0173 struct cnic_iscsi *iscsi;
0174 } proto;
0175 };
0176
0177 struct kcq_info {
0178 struct cnic_dma dma;
0179 struct kcqe **kcq;
0180
0181 u16 *hw_prod_idx_ptr;
0182 u16 sw_prod_idx;
0183 u16 *status_idx_ptr;
0184 u32 io_addr;
0185
0186 u16 (*next_idx)(u16);
0187 u16 (*hw_idx)(u16);
0188 };
0189
0190 #define UIO_USE_TX_DOORBELL 0x017855DB
0191
0192 struct cnic_uio_dev {
0193 struct uio_info cnic_uinfo;
0194 u32 uio_dev;
0195
0196 int l2_ring_size;
0197 void *l2_ring;
0198 dma_addr_t l2_ring_map;
0199
0200 int l2_buf_size;
0201 void *l2_buf;
0202 dma_addr_t l2_buf_map;
0203
0204 struct cnic_dev *dev;
0205 struct pci_dev *pdev;
0206 struct list_head list;
0207 };
0208
0209 struct cnic_local {
0210
0211 spinlock_t cnic_ulp_lock;
0212 void *ulp_handle[MAX_CNIC_ULP_TYPE];
0213 unsigned long ulp_flags[MAX_CNIC_ULP_TYPE];
0214 #define ULP_F_INIT 0
0215 #define ULP_F_START 1
0216 #define ULP_F_CALL_PENDING 2
0217 struct cnic_ulp_ops __rcu *ulp_ops[MAX_CNIC_ULP_TYPE];
0218
0219 unsigned long cnic_local_flags;
0220 #define CNIC_LCL_FL_KWQ_INIT 0x0
0221 #define CNIC_LCL_FL_L2_WAIT 0x1
0222 #define CNIC_LCL_FL_RINGS_INITED 0x2
0223 #define CNIC_LCL_FL_STOP_ISCSI 0x4
0224
0225 struct cnic_dev *dev;
0226
0227 struct cnic_eth_dev *ethdev;
0228
0229 struct cnic_uio_dev *udev;
0230
0231 int l2_rx_ring_size;
0232 int l2_single_buf_size;
0233
0234 u16 *rx_cons_ptr;
0235 u16 *tx_cons_ptr;
0236 u16 rx_cons;
0237 u16 tx_cons;
0238
0239 struct cnic_dma kwq_info;
0240 struct kwqe **kwq;
0241
0242 struct cnic_dma kwq_16_data_info;
0243
0244 u16 max_kwq_idx;
0245
0246 u16 kwq_prod_idx;
0247 u32 kwq_io_addr;
0248
0249 u16 *kwq_con_idx_ptr;
0250 u16 kwq_con_idx;
0251
0252 struct kcq_info kcq1;
0253 struct kcq_info kcq2;
0254
0255 union {
0256 void *gen;
0257 struct status_block_msix *bnx2;
0258 struct host_hc_status_block_e1x *bnx2x_e1x;
0259
0260 #define SM_RX_ID 0
0261 #define SM_TX_ID 1
0262 } status_blk;
0263
0264 struct host_sp_status_block *bnx2x_def_status_blk;
0265
0266 u32 status_blk_num;
0267 u32 bnx2x_igu_sb_id;
0268 u32 int_num;
0269 u32 last_status_idx;
0270 struct tasklet_struct cnic_irq_task;
0271
0272 struct kcqe *completed_kcq[MAX_COMPLETED_KCQE];
0273
0274 struct cnic_sock *csk_tbl;
0275 struct cnic_id_tbl csk_port_tbl;
0276
0277 struct cnic_dma gbl_buf_info;
0278
0279 struct cnic_iscsi *iscsi_tbl;
0280 struct cnic_context *ctx_tbl;
0281 struct cnic_id_tbl cid_tbl;
0282 atomic_t iscsi_conn;
0283 u32 iscsi_start_cid;
0284
0285 u32 fcoe_init_cid;
0286 u32 fcoe_start_cid;
0287 struct cnic_id_tbl fcoe_cid_tbl;
0288
0289 u32 max_cid_space;
0290
0291
0292 int num_iscsi_tasks;
0293 int num_ccells;
0294 int task_array_size;
0295 int r2tq_size;
0296 int hq_size;
0297 int num_cqs;
0298
0299 struct delayed_work delete_task;
0300
0301 struct cnic_ctx *ctx_arr;
0302 int ctx_blks;
0303 int ctx_blk_size;
0304 unsigned long ctx_align;
0305 int cids_per_blk;
0306
0307 u32 chip_id;
0308 int func;
0309
0310 u32 shmem_base;
0311
0312 struct cnic_ops *cnic_ops;
0313 int (*start_hw)(struct cnic_dev *);
0314 void (*stop_hw)(struct cnic_dev *);
0315 void (*setup_pgtbl)(struct cnic_dev *,
0316 struct cnic_dma *);
0317 int (*alloc_resc)(struct cnic_dev *);
0318 void (*free_resc)(struct cnic_dev *);
0319 int (*start_cm)(struct cnic_dev *);
0320 void (*stop_cm)(struct cnic_dev *);
0321 void (*enable_int)(struct cnic_dev *);
0322 void (*disable_int_sync)(struct cnic_dev *);
0323 void (*ack_int)(struct cnic_dev *);
0324 void (*arm_int)(struct cnic_dev *, u32 index);
0325 void (*close_conn)(struct cnic_sock *, u32 opcode);
0326 };
0327
0328 struct bnx2x_bd_chain_next {
0329 u32 addr_lo;
0330 u32 addr_hi;
0331 u8 reserved[8];
0332 };
0333
0334 #define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
0335
0336 #define ISCSI_RAMROD_CMD_ID_UPDATE_CONN (ISCSI_KCQE_OPCODE_UPDATE_CONN)
0337 #define ISCSI_RAMROD_CMD_ID_INIT (ISCSI_KCQE_OPCODE_INIT)
0338
0339 #define CDU_REGION_NUMBER_XCM_AG 2
0340 #define CDU_REGION_NUMBER_UCM_AG 4
0341
0342 #define CDU_VALID_DATA(_cid, _region, _type) \
0343 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
0344
0345 #define CDU_CRC8(_cid, _region, _type) \
0346 (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
0347
0348 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
0349 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
0350
0351 #define BNX2X_CONTEXT_MEM_SIZE 1024
0352 #define BNX2X_FCOE_CID 16
0353
0354 #define BNX2X_ISCSI_START_CID 18
0355 #define BNX2X_ISCSI_NUM_CONNECTIONS 128
0356 #define BNX2X_ISCSI_TASK_CONTEXT_SIZE 128
0357 #define BNX2X_ISCSI_MAX_PENDING_R2TS 4
0358 #define BNX2X_ISCSI_R2TQE_SIZE 8
0359 #define BNX2X_ISCSI_HQ_BD_SIZE 64
0360 #define BNX2X_ISCSI_GLB_BUF_SIZE 64
0361 #define BNX2X_ISCSI_PBL_NOT_CACHED 0xff
0362 #define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff
0363
0364 #define BNX2X_FCOE_NUM_CONNECTIONS 1024
0365
0366 #define BNX2X_FCOE_L5_CID_BASE MAX_ISCSI_TBL_SZ
0367
0368 #define BNX2X_CHIP_IS_E2_PLUS(bp) (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
0369
0370 #define BNX2X_RX_DESC_CNT (BNX2_PAGE_SIZE / \
0371 sizeof(struct eth_rx_bd))
0372 #define BNX2X_MAX_RX_DESC_CNT (BNX2X_RX_DESC_CNT - 2)
0373 #define BNX2X_RCQ_DESC_CNT (BNX2_PAGE_SIZE / \
0374 sizeof(union eth_rx_cqe))
0375 #define BNX2X_MAX_RCQ_DESC_CNT (BNX2X_RCQ_DESC_CNT - 1)
0376
0377 #define BNX2X_NEXT_RCQE(x) (((x) & BNX2X_MAX_RCQ_DESC_CNT) == \
0378 (BNX2X_MAX_RCQ_DESC_CNT - 1)) ? \
0379 ((x) + 2) : ((x) + 1)
0380
0381 #define BNX2X_DEF_SB_ID HC_SP_SB_ID
0382
0383 #define BNX2X_SHMEM_MF_BLK_OFFSET 0x7e4
0384
0385 #define BNX2X_SHMEM_ADDR(base, field) (base + \
0386 offsetof(struct shmem_region, field))
0387
0388 #define BNX2X_SHMEM2_ADDR(base, field) (base + \
0389 offsetof(struct shmem2_region, field))
0390
0391 #define BNX2X_SHMEM2_HAS(base, field) \
0392 ((base) && \
0393 (CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \
0394 offsetof(struct shmem2_region, field)))
0395
0396 #define BNX2X_MF_CFG_ADDR(base, field) \
0397 ((base) + offsetof(struct mf_cfg, field))
0398
0399 #ifndef ETH_MAX_RX_CLIENTS_E2
0400 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
0401 #endif
0402
0403 #define CNIC_FUNC(cp) ((cp)->func)
0404
0405 #define BNX2X_HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
0406 (BP_VN(bp) << 17) | (x))
0407
0408 #define BNX2X_SW_CID(x) (x & 0x1ffff)
0409
0410 #define BNX2X_CL_QZONE_ID(bp, cli) \
0411 (BNX2X_CHIP_IS_E2_PLUS(bp) ? cli : \
0412 cli + (BP_PORT(bp) * ETH_MAX_RX_CLIENTS_E1H))
0413
0414 #ifndef MAX_STAT_COUNTER_ID
0415 #define MAX_STAT_COUNTER_ID \
0416 (CHIP_IS_E1H(bp) ? MAX_STAT_COUNTER_ID_E1H : \
0417 ((BNX2X_CHIP_IS_E2_PLUS(bp)) ? MAX_STAT_COUNTER_ID_E2 : \
0418 MAX_STAT_COUNTER_ID_E1))
0419 #endif
0420
0421 #define CNIC_SUPPORTS_FCOE(cp) \
0422 (BNX2X_CHIP_IS_E2_PLUS(bp) && !NO_FCOE(bp))
0423
0424 #define CNIC_RAMROD_TMO (HZ / 4)
0425
0426 #endif
0427