broadcom/bnxt/bnxt_ptp.h

0001 /* Broadcom NetXtreme-C/E network driver.
0002  *
0003  * Copyright (c) 2021 Broadcom Inc.
0004  *
0005  * This program is free software; you can redistribute it and/or modify
0006  * it under the terms of the GNU General Public License as published by
0007  * the Free Software Foundation.
0008  */
0009
0010 #ifndef BNXT_PTP_H
0011 #define BNXT_PTP_H
0012
0013 #include <linux/ptp_clock_kernel.h>
0014 #include <linux/timecounter.h>
0015
0016 #define BNXT_PTP_GRC_WIN    6
0017 #define BNXT_PTP_GRC_WIN_BASE   0x6000
0018
0019 #define BNXT_MAX_PHC_DRIFT  31000000
0020 #define BNXT_LO_TIMER_MASK  0x0000ffffffffUL
0021 #define BNXT_HI_TIMER_MASK  0xffff00000000UL
0022
0023 #define BNXT_PTP_QTS_TIMEOUT    1000
0024 #define BNXT_PTP_QTS_TX_ENABLES (PORT_TS_QUERY_REQ_ENABLES_PTP_SEQ_ID | \
0025                  PORT_TS_QUERY_REQ_ENABLES_TS_REQ_TIMEOUT | \
0026                  PORT_TS_QUERY_REQ_ENABLES_PTP_HDR_OFFSET)
0027
0028 struct pps_pin {
0029     u8 event;
0030     u8 usage;
0031     u8 state;
0032 };
0033
0034 #define TSIO_PIN_VALID(pin) ((pin) >= 0 && (pin) < (BNXT_MAX_TSIO_PINS))
0035
0036 #define EVENT_DATA2_PPS_EVENT_TYPE(data2)               \
0037     ((data2) & ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_EVENT_TYPE)
0038
0039 #define EVENT_DATA2_PPS_PIN_NUM(data2)                  \
0040     (((data2) &                         \
0041       ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_MASK) >>\
0042      ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PIN_NUMBER_SFT)
0043
0044 #define BNXT_DATA2_UPPER_MSK                        \
0045     ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_MASK
0046
0047 #define BNXT_DATA2_UPPER_SFT                        \
0048     (32 -                               \
0049      ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA2_PPS_TIMESTAMP_UPPER_SFT)
0050
0051 #define BNXT_DATA1_LOWER_MSK                        \
0052     ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_MASK
0053
0054 #define BNXT_DATA1_LOWER_SFT                        \
0055       ASYNC_EVENT_CMPL_PPS_TIMESTAMP_EVENT_DATA1_PPS_TIMESTAMP_LOWER_SFT
0056
0057 #define EVENT_PPS_TS(data2, data1)                  \
0058     (((u64)((data2) & BNXT_DATA2_UPPER_MSK) << BNXT_DATA2_UPPER_SFT) |\
0059      (((data1) & BNXT_DATA1_LOWER_MSK) >> BNXT_DATA1_LOWER_SFT))
0060
0061 #define BNXT_PPS_PIN_DISABLE    0
0062 #define BNXT_PPS_PIN_ENABLE 1
0063 #define BNXT_PPS_PIN_NONE   0
0064 #define BNXT_PPS_PIN_PPS_IN 1
0065 #define BNXT_PPS_PIN_PPS_OUT    2
0066 #define BNXT_PPS_PIN_SYNC_IN    3
0067 #define BNXT_PPS_PIN_SYNC_OUT   4
0068
0069 #define BNXT_PPS_EVENT_INTERNAL 1
0070 #define BNXT_PPS_EVENT_EXTERNAL 2
0071
0072 struct bnxt_pps {
0073     u8 num_pins;
0074 #define BNXT_MAX_TSIO_PINS  4
0075     struct pps_pin pins[BNXT_MAX_TSIO_PINS];
0076 };
0077
0078 struct bnxt_ptp_cfg {
0079     struct ptp_clock_info   ptp_info;
0080     struct ptp_clock    *ptp_clock;
0081     struct cyclecounter cc;
0082     struct timecounter  tc;
0083     struct bnxt_pps     pps_info;
0084     /* serialize timecounter access */
0085     spinlock_t      ptp_lock;
0086     struct sk_buff      *tx_skb;
0087     u64         current_time;
0088     u64         old_time;
0089     unsigned long       next_period;
0090     unsigned long       next_overflow_check;
0091     /* 48-bit PHC overflows in 78 hours.  Check overflow every 19 hours. */
0092     #define BNXT_PHC_OVERFLOW_PERIOD    (19 * 3600 * HZ)
0093
0094     u16         tx_seqid;
0095     u16         tx_hdr_off;
0096     struct bnxt     *bp;
0097     atomic_t        tx_avail;
0098 #define BNXT_MAX_TX_TS  1
0099     u16         rxctl;
0100 #define BNXT_PTP_MSG_SYNC           (1 << 0)
0101 #define BNXT_PTP_MSG_DELAY_REQ          (1 << 1)
0102 #define BNXT_PTP_MSG_PDELAY_REQ         (1 << 2)
0103 #define BNXT_PTP_MSG_PDELAY_RESP        (1 << 3)
0104 #define BNXT_PTP_MSG_FOLLOW_UP          (1 << 8)
0105 #define BNXT_PTP_MSG_DELAY_RESP         (1 << 9)
0106 #define BNXT_PTP_MSG_PDELAY_RESP_FOLLOW_UP  (1 << 10)
0107 #define BNXT_PTP_MSG_ANNOUNCE           (1 << 11)
0108 #define BNXT_PTP_MSG_SIGNALING          (1 << 12)
0109 #define BNXT_PTP_MSG_MANAGEMENT         (1 << 13)
0110 #define BNXT_PTP_MSG_EVENTS     (BNXT_PTP_MSG_SYNC |        \
0111                      BNXT_PTP_MSG_DELAY_REQ |   \
0112                      BNXT_PTP_MSG_PDELAY_REQ |  \
0113                      BNXT_PTP_MSG_PDELAY_RESP)
0114     u8          tx_tstamp_en:1;
0115     int         rx_filter;
0116     u32         tstamp_filters;
0117
0118     u32         refclk_regs[2];
0119     u32         refclk_mapped_regs[2];
0120 };
0121
0122 #if BITS_PER_LONG == 32
0123 #define BNXT_READ_TIME64(ptp, dst, src)     \
0124 do {                        \
0125     spin_lock_bh(&(ptp)->ptp_lock);     \
0126     (dst) = (src);              \
0127     spin_unlock_bh(&(ptp)->ptp_lock);   \
0128 } while (0)
0129 #else
0130 #define BNXT_READ_TIME64(ptp, dst, src)     \
0131     ((dst) = READ_ONCE(src))
0132 #endif
0133
0134 int bnxt_ptp_parse(struct sk_buff *skb, u16 *seq_id, u16 *hdr_off);
0135 void bnxt_ptp_update_current_time(struct bnxt *bp);
0136 void bnxt_ptp_pps_event(struct bnxt *bp, u32 data1, u32 data2);
0137 void bnxt_ptp_cfg_tstamp_filters(struct bnxt *bp);
0138 void bnxt_ptp_reapply_pps(struct bnxt *bp);
0139 int bnxt_hwtstamp_set(struct net_device *dev, struct ifreq *ifr);
0140 int bnxt_hwtstamp_get(struct net_device *dev, struct ifreq *ifr);
0141 int bnxt_get_tx_ts_p5(struct bnxt *bp, struct sk_buff *skb);
0142 int bnxt_get_rx_ts_p5(struct bnxt *bp, u64 *ts, u32 pkt_ts);
0143 void bnxt_ptp_rtc_timecounter_init(struct bnxt_ptp_cfg *ptp, u64 ns);
0144 int bnxt_ptp_init_rtc(struct bnxt *bp, bool phc_cfg);
0145 int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg);
0146 void bnxt_ptp_clear(struct bnxt *bp);
0147 #endif