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0001 /* bnx2x_sp.h: Qlogic Everest network driver.
0002  *
0003  * Copyright 2011-2013 Broadcom Corporation
0004  * Copyright (c) 2014 QLogic Corporation
0005  * All rights reserved
0006  *
0007  * Unless you and Qlogic execute a separate written software license
0008  * agreement governing use of this software, this software is licensed to you
0009  * under the terms of the GNU General Public License version 2, available
0010  * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
0011  *
0012  * Notwithstanding the above, under no circumstances may you combine this
0013  * software in any way with any other Qlogic software provided under a
0014  * license other than the GPL, without Qlogic's express prior written
0015  * consent.
0016  *
0017  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
0018  * Written by: Vladislav Zolotarov
0019  *
0020  */
0021 #ifndef BNX2X_SP_VERBS
0022 #define BNX2X_SP_VERBS
0023 
0024 struct bnx2x;
0025 struct eth_context;
0026 
0027 /* Bits representing general command's configuration */
0028 enum {
0029     RAMROD_TX,
0030     RAMROD_RX,
0031     /* Wait until all pending commands complete */
0032     RAMROD_COMP_WAIT,
0033     /* Don't send a ramrod, only update a registry */
0034     RAMROD_DRV_CLR_ONLY,
0035     /* Configure HW according to the current object state */
0036     RAMROD_RESTORE,
0037      /* Execute the next command now */
0038     RAMROD_EXEC,
0039     /* Don't add a new command and continue execution of postponed
0040      * commands. If not set a new command will be added to the
0041      * pending commands list.
0042      */
0043     RAMROD_CONT,
0044     /* If there is another pending ramrod, wait until it finishes and
0045      * re-try to submit this one. This flag can be set only in sleepable
0046      * context, and should not be set from the context that completes the
0047      * ramrods as deadlock will occur.
0048      */
0049     RAMROD_RETRY,
0050 };
0051 
0052 typedef enum {
0053     BNX2X_OBJ_TYPE_RX,
0054     BNX2X_OBJ_TYPE_TX,
0055     BNX2X_OBJ_TYPE_RX_TX,
0056 } bnx2x_obj_type;
0057 
0058 /* Public slow path states */
0059 enum {
0060     BNX2X_FILTER_MAC_PENDING,
0061     BNX2X_FILTER_VLAN_PENDING,
0062     BNX2X_FILTER_VLAN_MAC_PENDING,
0063     BNX2X_FILTER_RX_MODE_PENDING,
0064     BNX2X_FILTER_RX_MODE_SCHED,
0065     BNX2X_FILTER_ISCSI_ETH_START_SCHED,
0066     BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
0067     BNX2X_FILTER_FCOE_ETH_START_SCHED,
0068     BNX2X_FILTER_FCOE_ETH_STOP_SCHED,
0069     BNX2X_FILTER_MCAST_PENDING,
0070     BNX2X_FILTER_MCAST_SCHED,
0071     BNX2X_FILTER_RSS_CONF_PENDING,
0072     BNX2X_AFEX_FCOE_Q_UPDATE_PENDING,
0073     BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
0074 };
0075 
0076 struct bnx2x_raw_obj {
0077     u8      func_id;
0078 
0079     /* Queue params */
0080     u8      cl_id;
0081     u32     cid;
0082 
0083     /* Ramrod data buffer params */
0084     void        *rdata;
0085     dma_addr_t  rdata_mapping;
0086 
0087     /* Ramrod state params */
0088     int     state;   /* "ramrod is pending" state bit */
0089     unsigned long   *pstate; /* pointer to state buffer */
0090 
0091     bnx2x_obj_type  obj_type;
0092 
0093     int (*wait_comp)(struct bnx2x *bp,
0094              struct bnx2x_raw_obj *o);
0095 
0096     bool (*check_pending)(struct bnx2x_raw_obj *o);
0097     void (*clear_pending)(struct bnx2x_raw_obj *o);
0098     void (*set_pending)(struct bnx2x_raw_obj *o);
0099 };
0100 
0101 /************************* VLAN-MAC commands related parameters ***************/
0102 struct bnx2x_mac_ramrod_data {
0103     u8 mac[ETH_ALEN];
0104     u8 is_inner_mac;
0105 };
0106 
0107 struct bnx2x_vlan_ramrod_data {
0108     u16 vlan;
0109 };
0110 
0111 struct bnx2x_vlan_mac_ramrod_data {
0112     u8 mac[ETH_ALEN];
0113     u8 is_inner_mac;
0114     u16 vlan;
0115 };
0116 
0117 union bnx2x_classification_ramrod_data {
0118     struct bnx2x_mac_ramrod_data mac;
0119     struct bnx2x_vlan_ramrod_data vlan;
0120     struct bnx2x_vlan_mac_ramrod_data vlan_mac;
0121 };
0122 
0123 /* VLAN_MAC commands */
0124 enum bnx2x_vlan_mac_cmd {
0125     BNX2X_VLAN_MAC_ADD,
0126     BNX2X_VLAN_MAC_DEL,
0127     BNX2X_VLAN_MAC_MOVE,
0128 };
0129 
0130 struct bnx2x_vlan_mac_data {
0131     /* Requested command: BNX2X_VLAN_MAC_XX */
0132     enum bnx2x_vlan_mac_cmd cmd;
0133     /* used to contain the data related vlan_mac_flags bits from
0134      * ramrod parameters.
0135      */
0136     unsigned long vlan_mac_flags;
0137 
0138     /* Needed for MOVE command */
0139     struct bnx2x_vlan_mac_obj *target_obj;
0140 
0141     union bnx2x_classification_ramrod_data u;
0142 };
0143 
0144 /*************************** Exe Queue obj ************************************/
0145 union bnx2x_exe_queue_cmd_data {
0146     struct bnx2x_vlan_mac_data vlan_mac;
0147 
0148     struct {
0149         /* TODO */
0150     } mcast;
0151 };
0152 
0153 struct bnx2x_exeq_elem {
0154     struct list_head        link;
0155 
0156     /* Length of this element in the exe_chunk. */
0157     int             cmd_len;
0158 
0159     union bnx2x_exe_queue_cmd_data  cmd_data;
0160 };
0161 
0162 union bnx2x_qable_obj;
0163 
0164 union bnx2x_exeq_comp_elem {
0165     union event_ring_elem *elem;
0166 };
0167 
0168 struct bnx2x_exe_queue_obj;
0169 
0170 typedef int (*exe_q_validate)(struct bnx2x *bp,
0171                   union bnx2x_qable_obj *o,
0172                   struct bnx2x_exeq_elem *elem);
0173 
0174 typedef int (*exe_q_remove)(struct bnx2x *bp,
0175                 union bnx2x_qable_obj *o,
0176                 struct bnx2x_exeq_elem *elem);
0177 
0178 /* Return positive if entry was optimized, 0 - if not, negative
0179  * in case of an error.
0180  */
0181 typedef int (*exe_q_optimize)(struct bnx2x *bp,
0182                   union bnx2x_qable_obj *o,
0183                   struct bnx2x_exeq_elem *elem);
0184 typedef int (*exe_q_execute)(struct bnx2x *bp,
0185                  union bnx2x_qable_obj *o,
0186                  struct list_head *exe_chunk,
0187                  unsigned long *ramrod_flags);
0188 typedef struct bnx2x_exeq_elem *
0189             (*exe_q_get)(struct bnx2x_exe_queue_obj *o,
0190                      struct bnx2x_exeq_elem *elem);
0191 
0192 struct bnx2x_exe_queue_obj {
0193     /* Commands pending for an execution. */
0194     struct list_head    exe_queue;
0195 
0196     /* Commands pending for an completion. */
0197     struct list_head    pending_comp;
0198 
0199     spinlock_t      lock;
0200 
0201     /* Maximum length of commands' list for one execution */
0202     int         exe_chunk_len;
0203 
0204     union bnx2x_qable_obj   *owner;
0205 
0206     /****** Virtual functions ******/
0207     /**
0208      * Called before commands execution for commands that are really
0209      * going to be executed (after 'optimize').
0210      *
0211      * Must run under exe_queue->lock
0212      */
0213     exe_q_validate      validate;
0214 
0215     /**
0216      * Called before removing pending commands, cleaning allocated
0217      * resources (e.g., credits from validate)
0218      */
0219      exe_q_remove       remove;
0220 
0221     /**
0222      * This will try to cancel the current pending commands list
0223      * considering the new command.
0224      *
0225      * Returns the number of optimized commands or a negative error code
0226      *
0227      * Must run under exe_queue->lock
0228      */
0229     exe_q_optimize      optimize;
0230 
0231     /**
0232      * Run the next commands chunk (owner specific).
0233      */
0234     exe_q_execute       execute;
0235 
0236     /**
0237      * Return the exe_queue element containing the specific command
0238      * if any. Otherwise return NULL.
0239      */
0240     exe_q_get       get;
0241 };
0242 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
0243 /*
0244  * Element in the VLAN_MAC registry list having all currently configured
0245  * rules.
0246  */
0247 struct bnx2x_vlan_mac_registry_elem {
0248     struct list_head    link;
0249 
0250     /* Used to store the cam offset used for the mac/vlan/vlan-mac.
0251      * Relevant for 57710 and 57711 only. VLANs and MACs share the
0252      * same CAM for these chips.
0253      */
0254     int         cam_offset;
0255 
0256     /* Needed for DEL and RESTORE flows */
0257     unsigned long       vlan_mac_flags;
0258 
0259     union bnx2x_classification_ramrod_data u;
0260 };
0261 
0262 /* Bits representing VLAN_MAC commands specific flags */
0263 enum {
0264     BNX2X_UC_LIST_MAC,
0265     BNX2X_ETH_MAC,
0266     BNX2X_ISCSI_ETH_MAC,
0267     BNX2X_NETQ_ETH_MAC,
0268     BNX2X_VLAN,
0269     BNX2X_DONT_CONSUME_CAM_CREDIT,
0270     BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
0271 };
0272 /* When looking for matching filters, some flags are not interesting */
0273 #define BNX2X_VLAN_MAC_CMP_MASK (1 << BNX2X_UC_LIST_MAC | \
0274                  1 << BNX2X_ETH_MAC | \
0275                  1 << BNX2X_ISCSI_ETH_MAC | \
0276                  1 << BNX2X_NETQ_ETH_MAC | \
0277                  1 << BNX2X_VLAN)
0278 #define BNX2X_VLAN_MAC_CMP_FLAGS(flags) \
0279     ((flags) & BNX2X_VLAN_MAC_CMP_MASK)
0280 
0281 struct bnx2x_vlan_mac_ramrod_params {
0282     /* Object to run the command from */
0283     struct bnx2x_vlan_mac_obj *vlan_mac_obj;
0284 
0285     /* General command flags: COMP_WAIT, etc. */
0286     unsigned long ramrod_flags;
0287 
0288     /* Command specific configuration request */
0289     struct bnx2x_vlan_mac_data user_req;
0290 };
0291 
0292 struct bnx2x_vlan_mac_obj {
0293     struct bnx2x_raw_obj raw;
0294 
0295     /* Bookkeeping list: will prevent the addition of already existing
0296      * entries.
0297      */
0298     struct list_head        head;
0299     /* Implement a simple reader/writer lock on the head list.
0300      * all these fields should only be accessed under the exe_queue lock
0301      */
0302     u8      head_reader; /* Num. of readers accessing head list */
0303     bool        head_exe_request; /* Pending execution request. */
0304     unsigned long   saved_ramrod_flags; /* Ramrods of pending execution */
0305 
0306     /* TODO: Add it's initialization in the init functions */
0307     struct bnx2x_exe_queue_obj  exe_queue;
0308 
0309     /* MACs credit pool */
0310     struct bnx2x_credit_pool_obj    *macs_pool;
0311 
0312     /* VLANs credit pool */
0313     struct bnx2x_credit_pool_obj    *vlans_pool;
0314 
0315     /* RAMROD command to be used */
0316     int             ramrod_cmd;
0317 
0318     /* copy first n elements onto preallocated buffer
0319      *
0320      * @param n number of elements to get
0321      * @param buf buffer preallocated by caller into which elements
0322      *            will be copied. Note elements are 4-byte aligned
0323      *            so buffer size must be able to accommodate the
0324      *            aligned elements.
0325      *
0326      * @return number of copied bytes
0327      */
0328     int (*get_n_elements)(struct bnx2x *bp,
0329                   struct bnx2x_vlan_mac_obj *o, int n, u8 *base,
0330                   u8 stride, u8 size);
0331 
0332     /**
0333      * Checks if ADD-ramrod with the given params may be performed.
0334      *
0335      * @return zero if the element may be added
0336      */
0337 
0338     int (*check_add)(struct bnx2x *bp,
0339              struct bnx2x_vlan_mac_obj *o,
0340              union bnx2x_classification_ramrod_data *data);
0341 
0342     /**
0343      * Checks if DEL-ramrod with the given params may be performed.
0344      *
0345      * @return true if the element may be deleted
0346      */
0347     struct bnx2x_vlan_mac_registry_elem *
0348         (*check_del)(struct bnx2x *bp,
0349                  struct bnx2x_vlan_mac_obj *o,
0350                  union bnx2x_classification_ramrod_data *data);
0351 
0352     /**
0353      * Checks if DEL-ramrod with the given params may be performed.
0354      *
0355      * @return true if the element may be deleted
0356      */
0357     bool (*check_move)(struct bnx2x *bp,
0358                struct bnx2x_vlan_mac_obj *src_o,
0359                struct bnx2x_vlan_mac_obj *dst_o,
0360                union bnx2x_classification_ramrod_data *data);
0361 
0362     /**
0363      *  Update the relevant credit object(s) (consume/return
0364      *  correspondingly).
0365      */
0366     bool (*get_credit)(struct bnx2x_vlan_mac_obj *o);
0367     bool (*put_credit)(struct bnx2x_vlan_mac_obj *o);
0368     bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset);
0369     bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset);
0370 
0371     /**
0372      * Configures one rule in the ramrod data buffer.
0373      */
0374     void (*set_one_rule)(struct bnx2x *bp,
0375                  struct bnx2x_vlan_mac_obj *o,
0376                  struct bnx2x_exeq_elem *elem, int rule_idx,
0377                  int cam_offset);
0378 
0379     /**
0380     *  Delete all configured elements having the given
0381     *  vlan_mac_flags specification. Assumes no pending for
0382     *  execution commands. Will schedule all all currently
0383     *  configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
0384     *  specification for deletion and will use the given
0385     *  ramrod_flags for the last DEL operation.
0386      *
0387      * @param bp
0388      * @param o
0389      * @param ramrod_flags RAMROD_XX flags
0390      *
0391      * @return 0 if the last operation has completed successfully
0392      *         and there are no more elements left, positive value
0393      *         if there are pending for completion commands,
0394      *         negative value in case of failure.
0395      */
0396     int (*delete_all)(struct bnx2x *bp,
0397               struct bnx2x_vlan_mac_obj *o,
0398               unsigned long *vlan_mac_flags,
0399               unsigned long *ramrod_flags);
0400 
0401     /**
0402      * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
0403      * configured elements list.
0404      *
0405      * @param bp
0406      * @param p Command parameters (RAMROD_COMP_WAIT bit in
0407      *          ramrod_flags is only taken into an account)
0408      * @param ppos a pointer to the cookie that should be given back in the
0409      *        next call to make function handle the next element. If
0410      *        *ppos is set to NULL it will restart the iterator.
0411      *        If returned *ppos == NULL this means that the last
0412      *        element has been handled.
0413      *
0414      * @return int
0415      */
0416     int (*restore)(struct bnx2x *bp,
0417                struct bnx2x_vlan_mac_ramrod_params *p,
0418                struct bnx2x_vlan_mac_registry_elem **ppos);
0419 
0420     /**
0421      * Should be called on a completion arrival.
0422      *
0423      * @param bp
0424      * @param o
0425      * @param cqe Completion element we are handling
0426      * @param ramrod_flags if RAMROD_CONT is set the next bulk of
0427      *             pending commands will be executed.
0428      *             RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
0429      *             may also be set if needed.
0430      *
0431      * @return 0 if there are neither pending nor waiting for
0432      *         completion commands. Positive value if there are
0433      *         pending for execution or for completion commands.
0434      *         Negative value in case of an error (including an
0435      *         error in the cqe).
0436      */
0437     int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
0438             union event_ring_elem *cqe,
0439             unsigned long *ramrod_flags);
0440 
0441     /**
0442      * Wait for completion of all commands. Don't schedule new ones,
0443      * just wait. It assumes that the completion code will schedule
0444      * for new commands.
0445      */
0446     int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o);
0447 };
0448 
0449 enum {
0450     BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0,
0451     BNX2X_LLH_CAM_ETH_LINE,
0452     BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2
0453 };
0454 
0455 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
0456 
0457 /* RX_MODE ramrod special flags: set in rx_mode_flags field in
0458  * a bnx2x_rx_mode_ramrod_params.
0459  */
0460 enum {
0461     BNX2X_RX_MODE_FCOE_ETH,
0462     BNX2X_RX_MODE_ISCSI_ETH,
0463 };
0464 
0465 enum {
0466     BNX2X_ACCEPT_UNICAST,
0467     BNX2X_ACCEPT_MULTICAST,
0468     BNX2X_ACCEPT_ALL_UNICAST,
0469     BNX2X_ACCEPT_ALL_MULTICAST,
0470     BNX2X_ACCEPT_BROADCAST,
0471     BNX2X_ACCEPT_UNMATCHED,
0472     BNX2X_ACCEPT_ANY_VLAN
0473 };
0474 
0475 struct bnx2x_rx_mode_ramrod_params {
0476     struct bnx2x_rx_mode_obj *rx_mode_obj;
0477     unsigned long *pstate;
0478     int state;
0479     u8 cl_id;
0480     u32 cid;
0481     u8 func_id;
0482     unsigned long ramrod_flags;
0483     unsigned long rx_mode_flags;
0484 
0485     /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
0486      * a tstorm_eth_mac_filter_config (e1x).
0487      */
0488     void *rdata;
0489     dma_addr_t rdata_mapping;
0490 
0491     /* Rx mode settings */
0492     unsigned long rx_accept_flags;
0493 
0494     /* internal switching settings */
0495     unsigned long tx_accept_flags;
0496 };
0497 
0498 struct bnx2x_rx_mode_obj {
0499     int (*config_rx_mode)(struct bnx2x *bp,
0500                   struct bnx2x_rx_mode_ramrod_params *p);
0501 
0502     int (*wait_comp)(struct bnx2x *bp,
0503              struct bnx2x_rx_mode_ramrod_params *p);
0504 };
0505 
0506 /********************** Set multicast group ***********************************/
0507 
0508 struct bnx2x_mcast_list_elem {
0509     struct list_head link;
0510     u8 *mac;
0511 };
0512 
0513 union bnx2x_mcast_config_data {
0514     u8 *mac;
0515     u8 bin; /* used in a RESTORE flow */
0516 };
0517 
0518 struct bnx2x_mcast_ramrod_params {
0519     struct bnx2x_mcast_obj *mcast_obj;
0520 
0521     /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
0522     unsigned long ramrod_flags;
0523 
0524     struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */
0525     /** TODO:
0526      *      - rename it to macs_num.
0527      *      - Add a new command type for handling pending commands
0528      *        (remove "zero semantics").
0529      *
0530      *  Length of mcast_list. If zero and ADD_CONT command - post
0531      *  pending commands.
0532      */
0533     int mcast_list_len;
0534 };
0535 
0536 enum bnx2x_mcast_cmd {
0537     BNX2X_MCAST_CMD_ADD,
0538     BNX2X_MCAST_CMD_CONT,
0539     BNX2X_MCAST_CMD_DEL,
0540     BNX2X_MCAST_CMD_RESTORE,
0541 
0542     /* Following this, multicast configuration should equal to approx
0543      * the set of MACs provided [i.e., remove all else].
0544      * The two sub-commands are used internally to decide whether a given
0545      * bin is to be added or removed
0546      */
0547     BNX2X_MCAST_CMD_SET,
0548     BNX2X_MCAST_CMD_SET_ADD,
0549     BNX2X_MCAST_CMD_SET_DEL,
0550 };
0551 
0552 struct bnx2x_mcast_obj {
0553     struct bnx2x_raw_obj raw;
0554 
0555     union {
0556         struct {
0557         #define BNX2X_MCAST_BINS_NUM    256
0558         #define BNX2X_MCAST_VEC_SZ  (BNX2X_MCAST_BINS_NUM / 64)
0559             u64 vec[BNX2X_MCAST_VEC_SZ];
0560 
0561             /** Number of BINs to clear. Should be updated
0562              *  immediately when a command arrives in order to
0563              *  properly create DEL commands.
0564              */
0565             int num_bins_set;
0566         } aprox_match;
0567 
0568         struct {
0569             struct list_head macs;
0570             int num_macs_set;
0571         } exact_match;
0572     } registry;
0573 
0574     /* Pending commands */
0575     struct list_head pending_cmds_head;
0576 
0577     /* A state that is set in raw.pstate, when there are pending commands */
0578     int sched_state;
0579 
0580     /* Maximal number of mcast MACs configured in one command */
0581     int max_cmd_len;
0582 
0583     /* Total number of currently pending MACs to configure: both
0584      * in the pending commands list and in the current command.
0585      */
0586     int total_pending_num;
0587 
0588     u8 engine_id;
0589 
0590     /**
0591      * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above)
0592      */
0593     int (*config_mcast)(struct bnx2x *bp,
0594                 struct bnx2x_mcast_ramrod_params *p,
0595                 enum bnx2x_mcast_cmd cmd);
0596 
0597     /**
0598      * Fills the ramrod data during the RESTORE flow.
0599      *
0600      * @param bp
0601      * @param o
0602      * @param start_idx Registry index to start from
0603      * @param rdata_idx Index in the ramrod data to start from
0604      *
0605      * @return -1 if we handled the whole registry or index of the last
0606      *         handled registry element.
0607      */
0608     int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
0609                int start_bin, int *rdata_idx);
0610 
0611     int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
0612                struct bnx2x_mcast_ramrod_params *p,
0613                enum bnx2x_mcast_cmd cmd);
0614 
0615     void (*set_one_rule)(struct bnx2x *bp,
0616                  struct bnx2x_mcast_obj *o, int idx,
0617                  union bnx2x_mcast_config_data *cfg_data,
0618                  enum bnx2x_mcast_cmd cmd);
0619 
0620     /** Checks if there are more mcast MACs to be set or a previous
0621      *  command is still pending.
0622      */
0623     bool (*check_pending)(struct bnx2x_mcast_obj *o);
0624 
0625     /**
0626      * Set/Clear/Check SCHEDULED state of the object
0627      */
0628     void (*set_sched)(struct bnx2x_mcast_obj *o);
0629     void (*clear_sched)(struct bnx2x_mcast_obj *o);
0630     bool (*check_sched)(struct bnx2x_mcast_obj *o);
0631 
0632     /* Wait until all pending commands complete */
0633     int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o);
0634 
0635     /**
0636      * Handle the internal object counters needed for proper
0637      * commands handling. Checks that the provided parameters are
0638      * feasible.
0639      */
0640     int (*validate)(struct bnx2x *bp,
0641             struct bnx2x_mcast_ramrod_params *p,
0642             enum bnx2x_mcast_cmd cmd);
0643 
0644     /**
0645      * Restore the values of internal counters in case of a failure.
0646      */
0647     void (*revert)(struct bnx2x *bp,
0648                struct bnx2x_mcast_ramrod_params *p,
0649                int old_num_bins,
0650                enum bnx2x_mcast_cmd cmd);
0651 
0652     int (*get_registry_size)(struct bnx2x_mcast_obj *o);
0653     void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n);
0654 };
0655 
0656 /*************************** Credit handling **********************************/
0657 struct bnx2x_credit_pool_obj {
0658 
0659     /* Current amount of credit in the pool */
0660     atomic_t    credit;
0661 
0662     /* Maximum allowed credit. put() will check against it. */
0663     int     pool_sz;
0664 
0665     /* Allocate a pool table statically.
0666      *
0667      * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272)
0668      *
0669      * The set bit in the table will mean that the entry is available.
0670      */
0671 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
0672     u64     pool_mirror[BNX2X_POOL_VEC_SIZE];
0673 
0674     /* Base pool offset (initialized differently */
0675     int     base_pool_offset;
0676 
0677     /**
0678      * Get the next free pool entry.
0679      *
0680      * @return true if there was a free entry in the pool
0681      */
0682     bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry);
0683 
0684     /**
0685      * Return the entry back to the pool.
0686      *
0687      * @return true if entry is legal and has been successfully
0688      *         returned to the pool.
0689      */
0690     bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry);
0691 
0692     /**
0693      * Get the requested amount of credit from the pool.
0694      *
0695      * @param cnt Amount of requested credit
0696      * @return true if the operation is successful
0697      */
0698     bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt);
0699 
0700     /**
0701      * Returns the credit to the pool.
0702      *
0703      * @param cnt Amount of credit to return
0704      * @return true if the operation is successful
0705      */
0706     bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt);
0707 
0708     /**
0709      * Reads the current amount of credit.
0710      */
0711     int (*check)(struct bnx2x_credit_pool_obj *o);
0712 };
0713 
0714 /*************************** RSS configuration ********************************/
0715 enum {
0716     /* RSS_MODE bits are mutually exclusive */
0717     BNX2X_RSS_MODE_DISABLED,
0718     BNX2X_RSS_MODE_REGULAR,
0719 
0720     BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
0721 
0722     BNX2X_RSS_IPV4,
0723     BNX2X_RSS_IPV4_TCP,
0724     BNX2X_RSS_IPV4_UDP,
0725     BNX2X_RSS_IPV6,
0726     BNX2X_RSS_IPV6_TCP,
0727     BNX2X_RSS_IPV6_UDP,
0728 
0729     BNX2X_RSS_IPV4_VXLAN,
0730     BNX2X_RSS_IPV6_VXLAN,
0731     BNX2X_RSS_TUNN_INNER_HDRS,
0732 };
0733 
0734 struct bnx2x_config_rss_params {
0735     struct bnx2x_rss_config_obj *rss_obj;
0736 
0737     /* may have RAMROD_COMP_WAIT set only */
0738     unsigned long   ramrod_flags;
0739 
0740     /* BNX2X_RSS_X bits */
0741     unsigned long   rss_flags;
0742 
0743     /* Number hash bits to take into an account */
0744     u8      rss_result_mask;
0745 
0746     /* Indirection table */
0747     u8      ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
0748 
0749     /* RSS hash values */
0750     u32     rss_key[10];
0751 
0752     /* valid only iff BNX2X_RSS_UPDATE_TOE is set */
0753     u16     toe_rss_bitmap;
0754 };
0755 
0756 struct bnx2x_rss_config_obj {
0757     struct bnx2x_raw_obj    raw;
0758 
0759     /* RSS engine to use */
0760     u8          engine_id;
0761 
0762     /* Last configured indirection table */
0763     u8          ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
0764 
0765     /* flags for enabling 4-tupple hash on UDP */
0766     u8          udp_rss_v4;
0767     u8          udp_rss_v6;
0768 
0769     int (*config_rss)(struct bnx2x *bp,
0770               struct bnx2x_config_rss_params *p);
0771 };
0772 
0773 /*********************** Queue state update ***********************************/
0774 
0775 /* UPDATE command options */
0776 enum {
0777     BNX2X_Q_UPDATE_IN_VLAN_REM,
0778     BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
0779     BNX2X_Q_UPDATE_OUT_VLAN_REM,
0780     BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
0781     BNX2X_Q_UPDATE_ANTI_SPOOF,
0782     BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
0783     BNX2X_Q_UPDATE_ACTIVATE,
0784     BNX2X_Q_UPDATE_ACTIVATE_CHNG,
0785     BNX2X_Q_UPDATE_DEF_VLAN_EN,
0786     BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
0787     BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
0788     BNX2X_Q_UPDATE_SILENT_VLAN_REM,
0789     BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
0790     BNX2X_Q_UPDATE_TX_SWITCHING,
0791     BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
0792     BNX2X_Q_UPDATE_PTP_PKTS,
0793 };
0794 
0795 /* Allowed Queue states */
0796 enum bnx2x_q_state {
0797     BNX2X_Q_STATE_RESET,
0798     BNX2X_Q_STATE_INITIALIZED,
0799     BNX2X_Q_STATE_ACTIVE,
0800     BNX2X_Q_STATE_MULTI_COS,
0801     BNX2X_Q_STATE_MCOS_TERMINATED,
0802     BNX2X_Q_STATE_INACTIVE,
0803     BNX2X_Q_STATE_STOPPED,
0804     BNX2X_Q_STATE_TERMINATED,
0805     BNX2X_Q_STATE_FLRED,
0806     BNX2X_Q_STATE_MAX,
0807 };
0808 
0809 /* Allowed Queue states */
0810 enum bnx2x_q_logical_state {
0811     BNX2X_Q_LOGICAL_STATE_ACTIVE,
0812     BNX2X_Q_LOGICAL_STATE_STOPPED,
0813 };
0814 
0815 /* Allowed commands */
0816 enum bnx2x_queue_cmd {
0817     BNX2X_Q_CMD_INIT,
0818     BNX2X_Q_CMD_SETUP,
0819     BNX2X_Q_CMD_SETUP_TX_ONLY,
0820     BNX2X_Q_CMD_DEACTIVATE,
0821     BNX2X_Q_CMD_ACTIVATE,
0822     BNX2X_Q_CMD_UPDATE,
0823     BNX2X_Q_CMD_UPDATE_TPA,
0824     BNX2X_Q_CMD_HALT,
0825     BNX2X_Q_CMD_CFC_DEL,
0826     BNX2X_Q_CMD_TERMINATE,
0827     BNX2X_Q_CMD_EMPTY,
0828     BNX2X_Q_CMD_MAX,
0829 };
0830 
0831 /* queue SETUP + INIT flags */
0832 enum {
0833     BNX2X_Q_FLG_TPA,
0834     BNX2X_Q_FLG_TPA_IPV6,
0835     BNX2X_Q_FLG_TPA_GRO,
0836     BNX2X_Q_FLG_STATS,
0837     BNX2X_Q_FLG_ZERO_STATS,
0838     BNX2X_Q_FLG_ACTIVE,
0839     BNX2X_Q_FLG_OV,
0840     BNX2X_Q_FLG_VLAN,
0841     BNX2X_Q_FLG_COS,
0842     BNX2X_Q_FLG_HC,
0843     BNX2X_Q_FLG_HC_EN,
0844     BNX2X_Q_FLG_DHC,
0845     BNX2X_Q_FLG_FCOE,
0846     BNX2X_Q_FLG_LEADING_RSS,
0847     BNX2X_Q_FLG_MCAST,
0848     BNX2X_Q_FLG_DEF_VLAN,
0849     BNX2X_Q_FLG_TX_SWITCH,
0850     BNX2X_Q_FLG_TX_SEC,
0851     BNX2X_Q_FLG_ANTI_SPOOF,
0852     BNX2X_Q_FLG_SILENT_VLAN_REM,
0853     BNX2X_Q_FLG_FORCE_DEFAULT_PRI,
0854     BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN,
0855     BNX2X_Q_FLG_PCSUM_ON_PKT,
0856     BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
0857 };
0858 
0859 /* Queue type options: queue type may be a combination of below. */
0860 enum bnx2x_q_type {
0861     /** TODO: Consider moving both these flags into the init()
0862      *        ramrod params.
0863      */
0864     BNX2X_Q_TYPE_HAS_RX,
0865     BNX2X_Q_TYPE_HAS_TX,
0866 };
0867 
0868 #define BNX2X_PRIMARY_CID_INDEX         0
0869 #define BNX2X_MULTI_TX_COS_E1X          3 /* QM only */
0870 #define BNX2X_MULTI_TX_COS_E2_E3A0      2
0871 #define BNX2X_MULTI_TX_COS_E3B0         3
0872 #define BNX2X_MULTI_TX_COS          3 /* Maximum possible */
0873 
0874 #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
0875 /* DMAE channel to be used by FW for timesync workaroun. A driver that sends
0876  * timesync-related ramrods must not use this DMAE command ID.
0877  */
0878 #define FW_DMAE_CMD_ID 6
0879 
0880 struct bnx2x_queue_init_params {
0881     struct {
0882         unsigned long   flags;
0883         u16     hc_rate;
0884         u8      fw_sb_id;
0885         u8      sb_cq_index;
0886     } tx;
0887 
0888     struct {
0889         unsigned long   flags;
0890         u16     hc_rate;
0891         u8      fw_sb_id;
0892         u8      sb_cq_index;
0893     } rx;
0894 
0895     /* CID context in the host memory */
0896     struct eth_context *cxts[BNX2X_MULTI_TX_COS];
0897 
0898     /* maximum number of cos supported by hardware */
0899     u8 max_cos;
0900 };
0901 
0902 struct bnx2x_queue_terminate_params {
0903     /* index within the tx_only cids of this queue object */
0904     u8 cid_index;
0905 };
0906 
0907 struct bnx2x_queue_cfc_del_params {
0908     /* index within the tx_only cids of this queue object */
0909     u8 cid_index;
0910 };
0911 
0912 struct bnx2x_queue_update_params {
0913     unsigned long   update_flags; /* BNX2X_Q_UPDATE_XX bits */
0914     u16     def_vlan;
0915     u16     silent_removal_value;
0916     u16     silent_removal_mask;
0917 /* index within the tx_only cids of this queue object */
0918     u8      cid_index;
0919 };
0920 
0921 struct bnx2x_queue_update_tpa_params {
0922     dma_addr_t sge_map;
0923     u8 update_ipv4;
0924     u8 update_ipv6;
0925     u8 max_tpa_queues;
0926     u8 max_sges_pkt;
0927     u8 complete_on_both_clients;
0928     u8 dont_verify_thr;
0929     u8 tpa_mode;
0930     u8 _pad;
0931 
0932     u16 sge_buff_sz;
0933     u16 max_agg_sz;
0934 
0935     u16 sge_pause_thr_low;
0936     u16 sge_pause_thr_high;
0937 };
0938 
0939 struct rxq_pause_params {
0940     u16     bd_th_lo;
0941     u16     bd_th_hi;
0942     u16     rcq_th_lo;
0943     u16     rcq_th_hi;
0944     u16     sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */
0945     u16     sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */
0946     u16     pri_map;
0947 };
0948 
0949 /* general */
0950 struct bnx2x_general_setup_params {
0951     /* valid iff BNX2X_Q_FLG_STATS */
0952     u8      stat_id;
0953 
0954     u8      spcl_id;
0955     u16     mtu;
0956     u8      cos;
0957 
0958     u8      fp_hsi;
0959 };
0960 
0961 struct bnx2x_rxq_setup_params {
0962     /* dma */
0963     dma_addr_t  dscr_map;
0964     dma_addr_t  sge_map;
0965     dma_addr_t  rcq_map;
0966     dma_addr_t  rcq_np_map;
0967 
0968     u16     drop_flags;
0969     u16     buf_sz;
0970     u8      fw_sb_id;
0971     u8      cl_qzone_id;
0972 
0973     /* valid iff BNX2X_Q_FLG_TPA */
0974     u16     tpa_agg_sz;
0975     u16     sge_buf_sz;
0976     u8      max_sges_pkt;
0977     u8      max_tpa_queues;
0978     u8      rss_engine_id;
0979 
0980     /* valid iff BNX2X_Q_FLG_MCAST */
0981     u8      mcast_engine_id;
0982 
0983     u8      cache_line_log;
0984 
0985     u8      sb_cq_index;
0986 
0987     /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */
0988     u16 silent_removal_value;
0989     u16 silent_removal_mask;
0990 };
0991 
0992 struct bnx2x_txq_setup_params {
0993     /* dma */
0994     dma_addr_t  dscr_map;
0995 
0996     u8      fw_sb_id;
0997     u8      sb_cq_index;
0998     u8      cos;        /* valid iff BNX2X_Q_FLG_COS */
0999     u16     traffic_type;
1000     /* equals to the leading rss client id, used for TX classification*/
1001     u8      tss_leading_cl_id;
1002 
1003     /* valid iff BNX2X_Q_FLG_DEF_VLAN */
1004     u16     default_vlan;
1005 };
1006 
1007 struct bnx2x_queue_setup_params {
1008     struct bnx2x_general_setup_params gen_params;
1009     struct bnx2x_txq_setup_params txq_params;
1010     struct bnx2x_rxq_setup_params rxq_params;
1011     struct rxq_pause_params pause_params;
1012     unsigned long flags;
1013 };
1014 
1015 struct bnx2x_queue_setup_tx_only_params {
1016     struct bnx2x_general_setup_params   gen_params;
1017     struct bnx2x_txq_setup_params       txq_params;
1018     unsigned long               flags;
1019     /* index within the tx_only cids of this queue object */
1020     u8                  cid_index;
1021 };
1022 
1023 struct bnx2x_queue_state_params {
1024     struct bnx2x_queue_sp_obj *q_obj;
1025 
1026     /* Current command */
1027     enum bnx2x_queue_cmd cmd;
1028 
1029     /* may have RAMROD_COMP_WAIT set only */
1030     unsigned long ramrod_flags;
1031 
1032     /* Params according to the current command */
1033     union {
1034         struct bnx2x_queue_update_params    update;
1035         struct bnx2x_queue_update_tpa_params    update_tpa;
1036         struct bnx2x_queue_setup_params     setup;
1037         struct bnx2x_queue_init_params      init;
1038         struct bnx2x_queue_setup_tx_only_params tx_only;
1039         struct bnx2x_queue_terminate_params terminate;
1040         struct bnx2x_queue_cfc_del_params   cfc_del;
1041     } params;
1042 };
1043 
1044 struct bnx2x_viflist_params {
1045     u8 echo_res;
1046     u8 func_bit_map_res;
1047 };
1048 
1049 struct bnx2x_queue_sp_obj {
1050     u32     cids[BNX2X_MULTI_TX_COS];
1051     u8      cl_id;
1052     u8      func_id;
1053 
1054     /* number of traffic classes supported by queue.
1055      * The primary connection of the queue supports the first traffic
1056      * class. Any further traffic class is supported by a tx-only
1057      * connection.
1058      *
1059      * Therefore max_cos is also a number of valid entries in the cids
1060      * array.
1061      */
1062     u8 max_cos;
1063     u8 num_tx_only, next_tx_only;
1064 
1065     enum bnx2x_q_state state, next_state;
1066 
1067     /* bits from enum bnx2x_q_type */
1068     unsigned long   type;
1069 
1070     /* BNX2X_Q_CMD_XX bits. This object implements "one
1071      * pending" paradigm but for debug and tracing purposes it's
1072      * more convenient to have different bits for different
1073      * commands.
1074      */
1075     unsigned long   pending;
1076 
1077     /* Buffer to use as a ramrod data and its mapping */
1078     void        *rdata;
1079     dma_addr_t  rdata_mapping;
1080 
1081     /**
1082      * Performs one state change according to the given parameters.
1083      *
1084      * @return 0 in case of success and negative value otherwise.
1085      */
1086     int (*send_cmd)(struct bnx2x *bp,
1087             struct bnx2x_queue_state_params *params);
1088 
1089     /**
1090      * Sets the pending bit according to the requested transition.
1091      */
1092     int (*set_pending)(struct bnx2x_queue_sp_obj *o,
1093                struct bnx2x_queue_state_params *params);
1094 
1095     /**
1096      * Checks that the requested state transition is legal.
1097      */
1098     int (*check_transition)(struct bnx2x *bp,
1099                 struct bnx2x_queue_sp_obj *o,
1100                 struct bnx2x_queue_state_params *params);
1101 
1102     /**
1103      * Completes the pending command.
1104      */
1105     int (*complete_cmd)(struct bnx2x *bp,
1106                 struct bnx2x_queue_sp_obj *o,
1107                 enum bnx2x_queue_cmd);
1108 
1109     int (*wait_comp)(struct bnx2x *bp,
1110              struct bnx2x_queue_sp_obj *o,
1111              enum bnx2x_queue_cmd cmd);
1112 };
1113 
1114 /********************** Function state update *********************************/
1115 
1116 /* UPDATE command options */
1117 enum {
1118     BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
1119     BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
1120     BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG,
1121     BNX2X_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG,
1122     BNX2X_F_UPDATE_VLAN_FORCE_PRIO_CHNG,
1123     BNX2X_F_UPDATE_VLAN_FORCE_PRIO_FLAG,
1124     BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
1125     BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE,
1126     BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN,
1127     BNX2X_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE,
1128     BNX2X_F_UPDATE_TUNNEL_INNER_RSS,
1129 };
1130 
1131 /* Allowed Function states */
1132 enum bnx2x_func_state {
1133     BNX2X_F_STATE_RESET,
1134     BNX2X_F_STATE_INITIALIZED,
1135     BNX2X_F_STATE_STARTED,
1136     BNX2X_F_STATE_TX_STOPPED,
1137     BNX2X_F_STATE_MAX,
1138 };
1139 
1140 /* Allowed Function commands */
1141 enum bnx2x_func_cmd {
1142     BNX2X_F_CMD_HW_INIT,
1143     BNX2X_F_CMD_START,
1144     BNX2X_F_CMD_STOP,
1145     BNX2X_F_CMD_HW_RESET,
1146     BNX2X_F_CMD_AFEX_UPDATE,
1147     BNX2X_F_CMD_AFEX_VIFLISTS,
1148     BNX2X_F_CMD_TX_STOP,
1149     BNX2X_F_CMD_TX_START,
1150     BNX2X_F_CMD_SWITCH_UPDATE,
1151     BNX2X_F_CMD_SET_TIMESYNC,
1152     BNX2X_F_CMD_MAX,
1153 };
1154 
1155 struct bnx2x_func_hw_init_params {
1156     /* A load phase returned by MCP.
1157      *
1158      * May be:
1159      *      FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1160      *      FW_MSG_CODE_DRV_LOAD_COMMON
1161      *      FW_MSG_CODE_DRV_LOAD_PORT
1162      *      FW_MSG_CODE_DRV_LOAD_FUNCTION
1163      */
1164     u32 load_phase;
1165 };
1166 
1167 struct bnx2x_func_hw_reset_params {
1168     /* A load phase returned by MCP.
1169      *
1170      * May be:
1171      *      FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1172      *      FW_MSG_CODE_DRV_LOAD_COMMON
1173      *      FW_MSG_CODE_DRV_LOAD_PORT
1174      *      FW_MSG_CODE_DRV_LOAD_FUNCTION
1175      */
1176     u32 reset_phase;
1177 };
1178 
1179 struct bnx2x_func_start_params {
1180     /* Multi Function mode:
1181      *  - Single Function
1182      *  - Switch Dependent
1183      *  - Switch Independent
1184      */
1185     u16 mf_mode;
1186 
1187     /* Switch Dependent mode outer VLAN tag */
1188     u16 sd_vlan_tag;
1189 
1190     /* Function cos mode */
1191     u8 network_cos_mode;
1192 
1193     /* UDP dest port for VXLAN */
1194     u16 vxlan_dst_port;
1195 
1196     /* UDP dest port for Geneve */
1197     u16 geneve_dst_port;
1198 
1199     /* Enable inner Rx classifications for L2GRE packets */
1200     u8 inner_clss_l2gre;
1201 
1202     /* Enable inner Rx classifications for L2-Geneve packets */
1203     u8 inner_clss_l2geneve;
1204 
1205     /* Enable inner Rx classification for vxlan packets */
1206     u8 inner_clss_vxlan;
1207 
1208     /* Enable RSS according to inner header */
1209     u8 inner_rss;
1210 
1211     /* Allows accepting of packets failing MF classification, possibly
1212      * only matching a given ethertype
1213      */
1214     u8 class_fail;
1215     u16 class_fail_ethtype;
1216 
1217     /* Override priority of output packets */
1218     u8 sd_vlan_force_pri;
1219     u8 sd_vlan_force_pri_val;
1220 
1221     /* Replace vlan's ethertype */
1222     u16 sd_vlan_eth_type;
1223 
1224     /* Prevent inner vlans from being added by FW */
1225     u8 no_added_tags;
1226 
1227     /* Inner-to-Outer vlan priority mapping */
1228     u8 c2s_pri[MAX_VLAN_PRIORITIES];
1229     u8 c2s_pri_default;
1230     u8 c2s_pri_valid;
1231 };
1232 
1233 struct bnx2x_func_switch_update_params {
1234     unsigned long changes; /* BNX2X_F_UPDATE_XX bits */
1235     u16 vlan;
1236     u16 vlan_eth_type;
1237     u8 vlan_force_prio;
1238     u16 vxlan_dst_port;
1239     u16 geneve_dst_port;
1240 };
1241 
1242 struct bnx2x_func_afex_update_params {
1243     u16 vif_id;
1244     u16 afex_default_vlan;
1245     u8 allowed_priorities;
1246 };
1247 
1248 struct bnx2x_func_afex_viflists_params {
1249     u16 vif_list_index;
1250     u8 func_bit_map;
1251     u8 afex_vif_list_command;
1252     u8 func_to_clear;
1253 };
1254 
1255 struct bnx2x_func_tx_start_params {
1256     struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1257     u8 dcb_enabled;
1258     u8 dcb_version;
1259     u8 dont_add_pri_0_en;
1260     u8 dcb_outer_pri[MAX_TRAFFIC_TYPES];
1261 };
1262 
1263 struct bnx2x_func_set_timesync_params {
1264     /* Reset, set or keep the current drift value */
1265     u8 drift_adjust_cmd;
1266 
1267     /* Dec, inc or keep the current offset */
1268     u8 offset_cmd;
1269 
1270     /* Drift value direction */
1271     u8 add_sub_drift_adjust_value;
1272 
1273     /* Drift, period and offset values to be used according to the commands
1274      * above.
1275      */
1276     u8 drift_adjust_value;
1277     u32 drift_adjust_period;
1278     u64 offset_delta;
1279 };
1280 
1281 struct bnx2x_func_state_params {
1282     struct bnx2x_func_sp_obj *f_obj;
1283 
1284     /* Current command */
1285     enum bnx2x_func_cmd cmd;
1286 
1287     /* may have RAMROD_COMP_WAIT set only */
1288     unsigned long   ramrod_flags;
1289 
1290     /* Params according to the current command */
1291     union {
1292         struct bnx2x_func_hw_init_params hw_init;
1293         struct bnx2x_func_hw_reset_params hw_reset;
1294         struct bnx2x_func_start_params start;
1295         struct bnx2x_func_switch_update_params switch_update;
1296         struct bnx2x_func_afex_update_params afex_update;
1297         struct bnx2x_func_afex_viflists_params afex_viflists;
1298         struct bnx2x_func_tx_start_params tx_start;
1299         struct bnx2x_func_set_timesync_params set_timesync;
1300     } params;
1301 };
1302 
1303 struct bnx2x_func_sp_drv_ops {
1304     /* Init tool + runtime initialization:
1305      *      - Common Chip
1306      *      - Common (per Path)
1307      *      - Port
1308      *      - Function phases
1309      */
1310     int (*init_hw_cmn_chip)(struct bnx2x *bp);
1311     int (*init_hw_cmn)(struct bnx2x *bp);
1312     int (*init_hw_port)(struct bnx2x *bp);
1313     int (*init_hw_func)(struct bnx2x *bp);
1314 
1315     /* Reset Function HW: Common, Port, Function phases. */
1316     void (*reset_hw_cmn)(struct bnx2x *bp);
1317     void (*reset_hw_port)(struct bnx2x *bp);
1318     void (*reset_hw_func)(struct bnx2x *bp);
1319 
1320     /* Init/Free GUNZIP resources */
1321     int (*gunzip_init)(struct bnx2x *bp);
1322     void (*gunzip_end)(struct bnx2x *bp);
1323 
1324     /* Prepare/Release FW resources */
1325     int (*init_fw)(struct bnx2x *bp);
1326     void (*release_fw)(struct bnx2x *bp);
1327 };
1328 
1329 struct bnx2x_func_sp_obj {
1330     enum bnx2x_func_state   state, next_state;
1331 
1332     /* BNX2X_FUNC_CMD_XX bits. This object implements "one
1333      * pending" paradigm but for debug and tracing purposes it's
1334      * more convenient to have different bits for different
1335      * commands.
1336      */
1337     unsigned long       pending;
1338 
1339     /* Buffer to use as a ramrod data and its mapping */
1340     void            *rdata;
1341     dma_addr_t      rdata_mapping;
1342 
1343     /* Buffer to use as a afex ramrod data and its mapping.
1344      * This can't be same rdata as above because afex ramrod requests
1345      * can arrive to the object in parallel to other ramrod requests.
1346      */
1347     void            *afex_rdata;
1348     dma_addr_t      afex_rdata_mapping;
1349 
1350     /* this mutex validates that when pending flag is taken, the next
1351      * ramrod to be sent will be the one set the pending bit
1352      */
1353     struct mutex        one_pending_mutex;
1354 
1355     /* Driver interface */
1356     struct bnx2x_func_sp_drv_ops    *drv;
1357 
1358     /**
1359      * Performs one state change according to the given parameters.
1360      *
1361      * @return 0 in case of success and negative value otherwise.
1362      */
1363     int (*send_cmd)(struct bnx2x *bp,
1364             struct bnx2x_func_state_params *params);
1365 
1366     /**
1367      * Checks that the requested state transition is legal.
1368      */
1369     int (*check_transition)(struct bnx2x *bp,
1370                 struct bnx2x_func_sp_obj *o,
1371                 struct bnx2x_func_state_params *params);
1372 
1373     /**
1374      * Completes the pending command.
1375      */
1376     int (*complete_cmd)(struct bnx2x *bp,
1377                 struct bnx2x_func_sp_obj *o,
1378                 enum bnx2x_func_cmd cmd);
1379 
1380     int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o,
1381              enum bnx2x_func_cmd cmd);
1382 };
1383 
1384 /********************** Interfaces ********************************************/
1385 /* Queueable objects set */
1386 union bnx2x_qable_obj {
1387     struct bnx2x_vlan_mac_obj vlan_mac;
1388 };
1389 /************** Function state update *********/
1390 void bnx2x_init_func_obj(struct bnx2x *bp,
1391              struct bnx2x_func_sp_obj *obj,
1392              void *rdata, dma_addr_t rdata_mapping,
1393              void *afex_rdata, dma_addr_t afex_rdata_mapping,
1394              struct bnx2x_func_sp_drv_ops *drv_iface);
1395 
1396 int bnx2x_func_state_change(struct bnx2x *bp,
1397                 struct bnx2x_func_state_params *params);
1398 
1399 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
1400                        struct bnx2x_func_sp_obj *o);
1401 /******************* Queue State **************/
1402 void bnx2x_init_queue_obj(struct bnx2x *bp,
1403               struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids,
1404               u8 cid_cnt, u8 func_id, void *rdata,
1405               dma_addr_t rdata_mapping, unsigned long type);
1406 
1407 int bnx2x_queue_state_change(struct bnx2x *bp,
1408                  struct bnx2x_queue_state_params *params);
1409 
1410 int bnx2x_get_q_logical_state(struct bnx2x *bp,
1411                    struct bnx2x_queue_sp_obj *obj);
1412 
1413 /********************* VLAN-MAC ****************/
1414 void bnx2x_init_mac_obj(struct bnx2x *bp,
1415             struct bnx2x_vlan_mac_obj *mac_obj,
1416             u8 cl_id, u32 cid, u8 func_id, void *rdata,
1417             dma_addr_t rdata_mapping, int state,
1418             unsigned long *pstate, bnx2x_obj_type type,
1419             struct bnx2x_credit_pool_obj *macs_pool);
1420 
1421 void bnx2x_init_vlan_obj(struct bnx2x *bp,
1422              struct bnx2x_vlan_mac_obj *vlan_obj,
1423              u8 cl_id, u32 cid, u8 func_id, void *rdata,
1424              dma_addr_t rdata_mapping, int state,
1425              unsigned long *pstate, bnx2x_obj_type type,
1426              struct bnx2x_credit_pool_obj *vlans_pool);
1427 
1428 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
1429                  struct bnx2x_vlan_mac_obj *vlan_mac_obj,
1430                  u8 cl_id, u32 cid, u8 func_id, void *rdata,
1431                  dma_addr_t rdata_mapping, int state,
1432                  unsigned long *pstate, bnx2x_obj_type type,
1433                  struct bnx2x_credit_pool_obj *macs_pool,
1434                  struct bnx2x_credit_pool_obj *vlans_pool);
1435 
1436 int bnx2x_vlan_mac_h_read_lock(struct bnx2x *bp,
1437                     struct bnx2x_vlan_mac_obj *o);
1438 void bnx2x_vlan_mac_h_read_unlock(struct bnx2x *bp,
1439                   struct bnx2x_vlan_mac_obj *o);
1440 int bnx2x_vlan_mac_h_write_lock(struct bnx2x *bp,
1441                 struct bnx2x_vlan_mac_obj *o);
1442 int bnx2x_config_vlan_mac(struct bnx2x *bp,
1443                struct bnx2x_vlan_mac_ramrod_params *p);
1444 
1445 int bnx2x_vlan_mac_move(struct bnx2x *bp,
1446             struct bnx2x_vlan_mac_ramrod_params *p,
1447             struct bnx2x_vlan_mac_obj *dest_o);
1448 
1449 /********************* RX MODE ****************/
1450 
1451 void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
1452                 struct bnx2x_rx_mode_obj *o);
1453 
1454 /**
1455  * bnx2x_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters.
1456  *
1457  * @p: Command parameters
1458  *
1459  * Return: 0 - if operation was successful and there is no pending completions,
1460  *         positive number - if there are pending completions,
1461  *         negative - if there were errors
1462  */
1463 int bnx2x_config_rx_mode(struct bnx2x *bp,
1464              struct bnx2x_rx_mode_ramrod_params *p);
1465 
1466 /****************** MULTICASTS ****************/
1467 
1468 void bnx2x_init_mcast_obj(struct bnx2x *bp,
1469               struct bnx2x_mcast_obj *mcast_obj,
1470               u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
1471               u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
1472               int state, unsigned long *pstate,
1473               bnx2x_obj_type type);
1474 
1475 /**
1476  * bnx2x_config_mcast - Configure multicast MACs list.
1477  *
1478  * @cmd: command to execute: BNX2X_MCAST_CMD_X
1479  *
1480  * May configure a new list
1481  * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up
1482  * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current
1483  * configuration, continue to execute the pending commands
1484  * (BNX2X_MCAST_CMD_CONT).
1485  *
1486  * If previous command is still pending or if number of MACs to
1487  * configure is more that maximum number of MACs in one command,
1488  * the current command will be enqueued to the tail of the
1489  * pending commands list.
1490  *
1491  * Return: 0 is operation was successful and there are no pending completions,
1492  *         negative if there were errors, positive if there are pending
1493  *         completions.
1494  */
1495 int bnx2x_config_mcast(struct bnx2x *bp,
1496                struct bnx2x_mcast_ramrod_params *p,
1497                enum bnx2x_mcast_cmd cmd);
1498 
1499 /****************** CREDIT POOL ****************/
1500 void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
1501                 struct bnx2x_credit_pool_obj *p, u8 func_id,
1502                 u8 func_num);
1503 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
1504                  struct bnx2x_credit_pool_obj *p, u8 func_id,
1505                  u8 func_num);
1506 void bnx2x_init_credit_pool(struct bnx2x_credit_pool_obj *p,
1507                 int base, int credit);
1508 
1509 /****************** RSS CONFIGURATION ****************/
1510 void bnx2x_init_rss_config_obj(struct bnx2x *bp,
1511                    struct bnx2x_rss_config_obj *rss_obj,
1512                    u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
1513                    void *rdata, dma_addr_t rdata_mapping,
1514                    int state, unsigned long *pstate,
1515                    bnx2x_obj_type type);
1516 
1517 /**
1518  * bnx2x_config_rss - Updates RSS configuration according to provided parameters
1519  *
1520  * Return: 0 in case of success
1521  */
1522 int bnx2x_config_rss(struct bnx2x *bp,
1523              struct bnx2x_config_rss_params *p);
1524 
1525 /**
1526  * bnx2x_get_rss_ind_table - Return the current ind_table configuration.
1527  *
1528  * @ind_table: buffer to fill with the current indirection
1529  *                  table content. Should be at least
1530  *                  T_ETH_INDIRECTION_TABLE_SIZE bytes long.
1531  */
1532 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
1533                  u8 *ind_table);
1534 
1535 #define PF_MAC_CREDIT_E2(bp, func_num)                  \
1536     ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(bp) * VF_MAC_CREDIT_CNT) / \
1537      func_num + GET_NUM_VFS_PER_PF(bp) * VF_MAC_CREDIT_CNT)
1538 
1539 #define BNX2X_VFS_VLAN_CREDIT(bp)   \
1540     (GET_NUM_VFS_PER_PATH(bp) * VF_VLAN_CREDIT_CNT)
1541 
1542 #define PF_VLAN_CREDIT_E2(bp, func_num)                  \
1543     ((MAX_VLAN_CREDIT_E2 - 1 - BNX2X_VFS_VLAN_CREDIT(bp)) / \
1544      func_num + GET_NUM_VFS_PER_PF(bp) * VF_VLAN_CREDIT_CNT)
1545 
1546 #endif /* BNX2X_SP_VERBS */
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