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0001 /* bnx2x_init_ops.h: Qlogic Everest network driver.
0002  *               Static functions needed during the initialization.
0003  *               This file is "included" in bnx2x_main.c.
0004  *
0005  * Copyright (c) 2007-2013 Broadcom Corporation
0006  * Copyright (c) 2014 QLogic Corporation
0007  All rights reserved
0008  *
0009  * This program is free software; you can redistribute it and/or modify
0010  * it under the terms of the GNU General Public License as published by
0011  * the Free Software Foundation.
0012  *
0013  * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
0014  * Written by: Vladislav Zolotarov
0015  */
0016 
0017 #ifndef BNX2X_INIT_OPS_H
0018 #define BNX2X_INIT_OPS_H
0019 
0020 
0021 #ifndef BP_ILT
0022 #define BP_ILT(bp)  NULL
0023 #endif
0024 
0025 #ifndef BP_FUNC
0026 #define BP_FUNC(bp) 0
0027 #endif
0028 
0029 #ifndef BP_PORT
0030 #define BP_PORT(bp) 0
0031 #endif
0032 
0033 #ifndef BNX2X_ILT_FREE
0034 #define BNX2X_ILT_FREE(x, y, sz)
0035 #endif
0036 
0037 #ifndef BNX2X_ILT_ZALLOC
0038 #define BNX2X_ILT_ZALLOC(x, y, sz)
0039 #endif
0040 
0041 #ifndef ILOG2
0042 #define ILOG2(x)    x
0043 #endif
0044 
0045 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len);
0046 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val);
0047 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp,
0048                       dma_addr_t phys_addr, u32 addr,
0049                       u32 len);
0050 
0051 static void bnx2x_init_str_wr(struct bnx2x *bp, u32 addr,
0052                   const u32 *data, u32 len)
0053 {
0054     u32 i;
0055 
0056     for (i = 0; i < len; i++)
0057         REG_WR(bp, addr + i*4, data[i]);
0058 }
0059 
0060 static void bnx2x_init_ind_wr(struct bnx2x *bp, u32 addr,
0061                   const u32 *data, u32 len)
0062 {
0063     u32 i;
0064 
0065     for (i = 0; i < len; i++)
0066         bnx2x_reg_wr_ind(bp, addr + i*4, data[i]);
0067 }
0068 
0069 static void bnx2x_write_big_buf(struct bnx2x *bp, u32 addr, u32 len,
0070                 u8 wb)
0071 {
0072     if (bp->dmae_ready)
0073         bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
0074 
0075     /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
0076     else if (wb && CHIP_IS_E1(bp))
0077         bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
0078 
0079     /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
0080     else
0081         bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
0082 }
0083 
0084 static void bnx2x_init_fill(struct bnx2x *bp, u32 addr, int fill,
0085                 u32 len, u8 wb)
0086 {
0087     u32 buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
0088     u32 buf_len32 = buf_len/4;
0089     u32 i;
0090 
0091     memset(GUNZIP_BUF(bp), (u8)fill, buf_len);
0092 
0093     for (i = 0; i < len; i += buf_len32) {
0094         u32 cur_len = min(buf_len32, len - i);
0095 
0096         bnx2x_write_big_buf(bp, addr + i*4, cur_len, wb);
0097     }
0098 }
0099 
0100 static void bnx2x_write_big_buf_wb(struct bnx2x *bp, u32 addr, u32 len)
0101 {
0102     if (bp->dmae_ready)
0103         bnx2x_write_dmae_phys_len(bp, GUNZIP_PHYS(bp), addr, len);
0104 
0105     /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
0106     else if (CHIP_IS_E1(bp))
0107         bnx2x_init_ind_wr(bp, addr, GUNZIP_BUF(bp), len);
0108 
0109     /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
0110     else
0111         bnx2x_init_str_wr(bp, addr, GUNZIP_BUF(bp), len);
0112 }
0113 
0114 static void bnx2x_init_wr_64(struct bnx2x *bp, u32 addr,
0115                  const u32 *data, u32 len64)
0116 {
0117     u32 buf_len32 = FW_BUF_SIZE/4;
0118     u32 len = len64*2;
0119     u64 data64 = 0;
0120     u32 i;
0121 
0122     /* 64 bit value is in a blob: first low DWORD, then high DWORD */
0123     data64 = HILO_U64((*(data + 1)), (*data));
0124 
0125     len64 = min((u32)(FW_BUF_SIZE/8), len64);
0126     for (i = 0; i < len64; i++) {
0127         u64 *pdata = ((u64 *)(GUNZIP_BUF(bp))) + i;
0128 
0129         *pdata = data64;
0130     }
0131 
0132     for (i = 0; i < len; i += buf_len32) {
0133         u32 cur_len = min(buf_len32, len - i);
0134 
0135         bnx2x_write_big_buf_wb(bp, addr + i*4, cur_len);
0136     }
0137 }
0138 
0139 /*********************************************************
0140    There are different blobs for each PRAM section.
0141    In addition, each blob write operation is divided into a few operations
0142    in order to decrease the amount of phys. contiguous buffer needed.
0143    Thus, when we select a blob the address may be with some offset
0144    from the beginning of PRAM section.
0145    The same holds for the INT_TABLE sections.
0146 **********************************************************/
0147 #define IF_IS_INT_TABLE_ADDR(base, addr) \
0148             if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
0149 
0150 #define IF_IS_PRAM_ADDR(base, addr) \
0151             if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
0152 
0153 static const u8 *bnx2x_sel_blob(struct bnx2x *bp, u32 addr,
0154                 const u8 *data)
0155 {
0156     IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
0157         data = INIT_TSEM_INT_TABLE_DATA(bp);
0158     else
0159         IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
0160             data = INIT_CSEM_INT_TABLE_DATA(bp);
0161     else
0162         IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
0163             data = INIT_USEM_INT_TABLE_DATA(bp);
0164     else
0165         IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
0166             data = INIT_XSEM_INT_TABLE_DATA(bp);
0167     else
0168         IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
0169             data = INIT_TSEM_PRAM_DATA(bp);
0170     else
0171         IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
0172             data = INIT_CSEM_PRAM_DATA(bp);
0173     else
0174         IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
0175             data = INIT_USEM_PRAM_DATA(bp);
0176     else
0177         IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
0178             data = INIT_XSEM_PRAM_DATA(bp);
0179 
0180     return data;
0181 }
0182 
0183 static void bnx2x_init_wr_wb(struct bnx2x *bp, u32 addr,
0184                  const u32 *data, u32 len)
0185 {
0186     if (bp->dmae_ready)
0187         VIRT_WR_DMAE_LEN(bp, data, addr, len, 0);
0188 
0189     /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
0190     else if (CHIP_IS_E1(bp))
0191         bnx2x_init_ind_wr(bp, addr, data, len);
0192 
0193     /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
0194     else
0195         bnx2x_init_str_wr(bp, addr, data, len);
0196 }
0197 
0198 static void bnx2x_wr_64(struct bnx2x *bp, u32 reg, u32 val_lo,
0199             u32 val_hi)
0200 {
0201     u32 wb_write[2];
0202 
0203     wb_write[0] = val_lo;
0204     wb_write[1] = val_hi;
0205     REG_WR_DMAE_LEN(bp, reg, wb_write, 2);
0206 }
0207 static void bnx2x_init_wr_zp(struct bnx2x *bp, u32 addr, u32 len,
0208                  u32 blob_off)
0209 {
0210     const u8 *data = NULL;
0211     int rc;
0212     u32 i;
0213 
0214     data = bnx2x_sel_blob(bp, addr, data) + blob_off*4;
0215 
0216     rc = bnx2x_gunzip(bp, data, len);
0217     if (rc)
0218         return;
0219 
0220     /* gunzip_outlen is in dwords */
0221     len = GUNZIP_OUTLEN(bp);
0222     for (i = 0; i < len; i++)
0223         ((u32 *)GUNZIP_BUF(bp))[i] = (__force u32)
0224                 cpu_to_le32(((u32 *)GUNZIP_BUF(bp))[i]);
0225 
0226     bnx2x_write_big_buf_wb(bp, addr, len);
0227 }
0228 
0229 static void bnx2x_init_block(struct bnx2x *bp, u32 block, u32 stage)
0230 {
0231     u16 op_start =
0232         INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
0233                              STAGE_START)];
0234     u16 op_end =
0235         INIT_OPS_OFFSETS(bp)[BLOCK_OPS_IDX(block, stage,
0236                              STAGE_END)];
0237     const union init_op *op;
0238     u32 op_idx, op_type, addr, len;
0239     const u32 *data, *data_base;
0240 
0241     /* If empty block */
0242     if (op_start == op_end)
0243         return;
0244 
0245     data_base = INIT_DATA(bp);
0246 
0247     for (op_idx = op_start; op_idx < op_end; op_idx++) {
0248 
0249         op = (const union init_op *)&(INIT_OPS(bp)[op_idx]);
0250         /* Get generic data */
0251         op_type = op->raw.op;
0252         addr = op->raw.offset;
0253         /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
0254          * OP_WR64 (we assume that op_arr_write and op_write have the
0255          * same structure).
0256          */
0257         len = op->arr_wr.data_len;
0258         data = data_base + op->arr_wr.data_off;
0259 
0260         switch (op_type) {
0261         case OP_RD:
0262             REG_RD(bp, addr);
0263             break;
0264         case OP_WR:
0265             REG_WR(bp, addr, op->write.val);
0266             break;
0267         case OP_SW:
0268             bnx2x_init_str_wr(bp, addr, data, len);
0269             break;
0270         case OP_WB:
0271             bnx2x_init_wr_wb(bp, addr, data, len);
0272             break;
0273         case OP_ZR:
0274             bnx2x_init_fill(bp, addr, 0, op->zero.len, 0);
0275             break;
0276         case OP_WB_ZR:
0277             bnx2x_init_fill(bp, addr, 0, op->zero.len, 1);
0278             break;
0279         case OP_ZP:
0280             bnx2x_init_wr_zp(bp, addr, len,
0281                      op->arr_wr.data_off);
0282             break;
0283         case OP_WR_64:
0284             bnx2x_init_wr_64(bp, addr, data, len);
0285             break;
0286         case OP_IF_MODE_AND:
0287             /* if any of the flags doesn't match, skip the
0288              * conditional block.
0289              */
0290             if ((INIT_MODE_FLAGS(bp) &
0291                 op->if_mode.mode_bit_map) !=
0292                 op->if_mode.mode_bit_map)
0293                 op_idx += op->if_mode.cmd_offset;
0294             break;
0295         case OP_IF_MODE_OR:
0296             /* if all the flags don't match, skip the conditional
0297              * block.
0298              */
0299             if ((INIT_MODE_FLAGS(bp) &
0300                 op->if_mode.mode_bit_map) == 0)
0301                 op_idx += op->if_mode.cmd_offset;
0302             break;
0303         default:
0304             /* Should never get here! */
0305 
0306             break;
0307         }
0308     }
0309 }
0310 
0311 
0312 /****************************************************************************
0313 * PXP Arbiter
0314 ****************************************************************************/
0315 /*
0316  * This code configures the PCI read/write arbiter
0317  * which implements a weighted round robin
0318  * between the virtual queues in the chip.
0319  *
0320  * The values were derived for each PCI max payload and max request size.
0321  * since max payload and max request size are only known at run time,
0322  * this is done as a separate init stage.
0323  */
0324 
0325 #define NUM_WR_Q            13
0326 #define NUM_RD_Q            29
0327 #define MAX_RD_ORD          3
0328 #define MAX_WR_ORD          2
0329 
0330 /* configuration for one arbiter queue */
0331 struct arb_line {
0332     int l;
0333     int add;
0334     int ubound;
0335 };
0336 
0337 /* derived configuration for each read queue for each max request size */
0338 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
0339 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
0340     { {4, 8,  4},  {4,  8,  4},  {4,  8,  4},  {4,  8,  4}  },
0341     { {4, 3,  3},  {4,  3,  3},  {4,  3,  3},  {4,  3,  3}  },
0342     { {8, 3,  6},  {16, 3,  11}, {16, 3,  11}, {16, 3,  11} },
0343     { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
0344     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
0345     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
0346     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
0347     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {64, 3,  41} },
0348 /* 10 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0349     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0350     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0351     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0352     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0353     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0354     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0355     { {8, 64, 6},  {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
0356     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0357     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0358 /* 20 */{ {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0359     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0360     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0361     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0362     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0363     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0364     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0365     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0366     { {8, 3,  6},  {16, 3,  11}, {32, 3,  21}, {32, 3,  21} },
0367     { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
0368 };
0369 
0370 /* derived configuration for each write queue for each max request size */
0371 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
0372 /* 1 */ { {4, 6,  3},  {4,  6,  3},  {4,  6,  3} },
0373     { {4, 2,  3},  {4,  2,  3},  {4,  2,  3} },
0374     { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
0375     { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
0376     { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
0377     { {8, 2,  6},  {16, 2,  11}, {32, 2,  21} },
0378     { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
0379     { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
0380     { {8, 2,  6},  {16, 2,  11}, {16, 2,  11} },
0381 /* 10 */{ {8, 9,  6},  {16, 9,  11}, {32, 9,  21} },
0382     { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
0383     { {8, 9,  6},  {16, 9,  11}, {16, 9,  11} },
0384     { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
0385 };
0386 
0387 /* register addresses for read queues */
0388 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
0389 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
0390         PXP2_REG_RQ_BW_RD_UBOUND0},
0391     {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
0392         PXP2_REG_PSWRQ_BW_UB1},
0393     {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
0394         PXP2_REG_PSWRQ_BW_UB2},
0395     {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
0396         PXP2_REG_PSWRQ_BW_UB3},
0397     {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
0398         PXP2_REG_RQ_BW_RD_UBOUND4},
0399     {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
0400         PXP2_REG_RQ_BW_RD_UBOUND5},
0401     {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
0402         PXP2_REG_PSWRQ_BW_UB6},
0403     {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
0404         PXP2_REG_PSWRQ_BW_UB7},
0405     {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
0406         PXP2_REG_PSWRQ_BW_UB8},
0407 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
0408         PXP2_REG_PSWRQ_BW_UB9},
0409     {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
0410         PXP2_REG_PSWRQ_BW_UB10},
0411     {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
0412         PXP2_REG_PSWRQ_BW_UB11},
0413     {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
0414         PXP2_REG_RQ_BW_RD_UBOUND12},
0415     {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
0416         PXP2_REG_RQ_BW_RD_UBOUND13},
0417     {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
0418         PXP2_REG_RQ_BW_RD_UBOUND14},
0419     {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
0420         PXP2_REG_RQ_BW_RD_UBOUND15},
0421     {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
0422         PXP2_REG_RQ_BW_RD_UBOUND16},
0423     {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
0424         PXP2_REG_RQ_BW_RD_UBOUND17},
0425     {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
0426         PXP2_REG_RQ_BW_RD_UBOUND18},
0427 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
0428         PXP2_REG_RQ_BW_RD_UBOUND19},
0429     {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
0430         PXP2_REG_RQ_BW_RD_UBOUND20},
0431     {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
0432         PXP2_REG_RQ_BW_RD_UBOUND22},
0433     {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
0434         PXP2_REG_RQ_BW_RD_UBOUND23},
0435     {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
0436         PXP2_REG_RQ_BW_RD_UBOUND24},
0437     {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
0438         PXP2_REG_RQ_BW_RD_UBOUND25},
0439     {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
0440         PXP2_REG_RQ_BW_RD_UBOUND26},
0441     {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
0442         PXP2_REG_RQ_BW_RD_UBOUND27},
0443     {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
0444         PXP2_REG_PSWRQ_BW_UB28}
0445 };
0446 
0447 /* register addresses for write queues */
0448 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
0449 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
0450         PXP2_REG_PSWRQ_BW_UB1},
0451     {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
0452         PXP2_REG_PSWRQ_BW_UB2},
0453     {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
0454         PXP2_REG_PSWRQ_BW_UB3},
0455     {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
0456         PXP2_REG_PSWRQ_BW_UB6},
0457     {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
0458         PXP2_REG_PSWRQ_BW_UB7},
0459     {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
0460         PXP2_REG_PSWRQ_BW_UB8},
0461     {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
0462         PXP2_REG_PSWRQ_BW_UB9},
0463     {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
0464         PXP2_REG_PSWRQ_BW_UB10},
0465     {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
0466         PXP2_REG_PSWRQ_BW_UB11},
0467 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
0468         PXP2_REG_PSWRQ_BW_UB28},
0469     {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
0470         PXP2_REG_RQ_BW_WR_UBOUND29},
0471     {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
0472         PXP2_REG_RQ_BW_WR_UBOUND30}
0473 };
0474 
0475 static void bnx2x_init_pxp_arb(struct bnx2x *bp, int r_order,
0476                    int w_order)
0477 {
0478     u32 val, i;
0479 
0480     if (r_order > MAX_RD_ORD) {
0481         DP(NETIF_MSG_HW, "read order of %d  order adjusted to %d\n",
0482            r_order, MAX_RD_ORD);
0483         r_order = MAX_RD_ORD;
0484     }
0485     if (w_order > MAX_WR_ORD) {
0486         DP(NETIF_MSG_HW, "write order of %d  order adjusted to %d\n",
0487            w_order, MAX_WR_ORD);
0488         w_order = MAX_WR_ORD;
0489     }
0490     if (CHIP_REV_IS_FPGA(bp)) {
0491         DP(NETIF_MSG_HW, "write order adjusted to 1 for FPGA\n");
0492         w_order = 0;
0493     }
0494     DP(NETIF_MSG_HW, "read order %d  write order %d\n", r_order, w_order);
0495 
0496     for (i = 0; i < NUM_RD_Q-1; i++) {
0497         REG_WR(bp, read_arb_addr[i].l, read_arb_data[i][r_order].l);
0498         REG_WR(bp, read_arb_addr[i].add,
0499                read_arb_data[i][r_order].add);
0500         REG_WR(bp, read_arb_addr[i].ubound,
0501                read_arb_data[i][r_order].ubound);
0502     }
0503 
0504     for (i = 0; i < NUM_WR_Q-1; i++) {
0505         if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
0506             (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
0507 
0508             REG_WR(bp, write_arb_addr[i].l,
0509                    write_arb_data[i][w_order].l);
0510 
0511             REG_WR(bp, write_arb_addr[i].add,
0512                    write_arb_data[i][w_order].add);
0513 
0514             REG_WR(bp, write_arb_addr[i].ubound,
0515                    write_arb_data[i][w_order].ubound);
0516         } else {
0517 
0518             val = REG_RD(bp, write_arb_addr[i].l);
0519             REG_WR(bp, write_arb_addr[i].l,
0520                    val | (write_arb_data[i][w_order].l << 10));
0521 
0522             val = REG_RD(bp, write_arb_addr[i].add);
0523             REG_WR(bp, write_arb_addr[i].add,
0524                    val | (write_arb_data[i][w_order].add << 10));
0525 
0526             val = REG_RD(bp, write_arb_addr[i].ubound);
0527             REG_WR(bp, write_arb_addr[i].ubound,
0528                    val | (write_arb_data[i][w_order].ubound << 7));
0529         }
0530     }
0531 
0532     val =  write_arb_data[NUM_WR_Q-1][w_order].add;
0533     val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
0534     val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
0535     REG_WR(bp, PXP2_REG_PSWRQ_BW_RD, val);
0536 
0537     val =  read_arb_data[NUM_RD_Q-1][r_order].add;
0538     val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
0539     val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
0540     REG_WR(bp, PXP2_REG_PSWRQ_BW_WR, val);
0541 
0542     REG_WR(bp, PXP2_REG_RQ_WR_MBS0, w_order);
0543     REG_WR(bp, PXP2_REG_RQ_WR_MBS1, w_order);
0544     REG_WR(bp, PXP2_REG_RQ_RD_MBS0, r_order);
0545     REG_WR(bp, PXP2_REG_RQ_RD_MBS1, r_order);
0546 
0547     if ((CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) && (r_order == MAX_RD_ORD))
0548         REG_WR(bp, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
0549 
0550     if (CHIP_IS_E3(bp))
0551         REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
0552     else if (CHIP_IS_E2(bp))
0553         REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
0554     else
0555         REG_WR(bp, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
0556 
0557     if (!CHIP_IS_E1(bp)) {
0558         /*    MPS      w_order     optimal TH      presently TH
0559          *    128         0             0               2
0560          *    256         1             1               3
0561          *    >=512       2             2               3
0562          */
0563         /* DMAE is special */
0564         if (!CHIP_IS_E1H(bp)) {
0565             /* E2 can use optimal TH */
0566             val = w_order;
0567             REG_WR(bp, PXP2_REG_WR_DMAE_MPS, val);
0568         } else {
0569             val = ((w_order == 0) ? 2 : 3);
0570             REG_WR(bp, PXP2_REG_WR_DMAE_MPS, 2);
0571         }
0572 
0573         REG_WR(bp, PXP2_REG_WR_HC_MPS, val);
0574         REG_WR(bp, PXP2_REG_WR_USDM_MPS, val);
0575         REG_WR(bp, PXP2_REG_WR_CSDM_MPS, val);
0576         REG_WR(bp, PXP2_REG_WR_TSDM_MPS, val);
0577         REG_WR(bp, PXP2_REG_WR_XSDM_MPS, val);
0578         REG_WR(bp, PXP2_REG_WR_QM_MPS, val);
0579         REG_WR(bp, PXP2_REG_WR_TM_MPS, val);
0580         REG_WR(bp, PXP2_REG_WR_SRC_MPS, val);
0581         REG_WR(bp, PXP2_REG_WR_DBG_MPS, val);
0582         REG_WR(bp, PXP2_REG_WR_CDU_MPS, val);
0583     }
0584 
0585     /* Validate number of tags suppoted by device */
0586 #define PCIE_REG_PCIER_TL_HDR_FC_ST     0x2980
0587     val = REG_RD(bp, PCIE_REG_PCIER_TL_HDR_FC_ST);
0588     val &= 0xFF;
0589     if (val <= 0x20)
0590         REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
0591 }
0592 
0593 /****************************************************************************
0594 * ILT management
0595 ****************************************************************************/
0596 /*
0597  * This codes hides the low level HW interaction for ILT management and
0598  * configuration. The API consists of a shadow ILT table which is set by the
0599  * driver and a set of routines to use it to configure the HW.
0600  *
0601  */
0602 
0603 /* ILT HW init operations */
0604 
0605 /* ILT memory management operations */
0606 #define ILT_MEMOP_ALLOC     0
0607 #define ILT_MEMOP_FREE      1
0608 
0609 /* the phys address is shifted right 12 bits and has an added
0610  * 1=valid bit added to the 53rd bit
0611  * then since this is a wide register(TM)
0612  * we split it into two 32 bit writes
0613  */
0614 #define ILT_ADDR1(x)        ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
0615 #define ILT_ADDR2(x)        ((u32)((1 << 20) | ((u64)x >> 44)))
0616 #define ILT_RANGE(f, l)     (((l) << 10) | f)
0617 
0618 static int bnx2x_ilt_line_mem_op(struct bnx2x *bp,
0619                  struct ilt_line *line, u32 size, u8 memop)
0620 {
0621     if (memop == ILT_MEMOP_FREE) {
0622         BNX2X_ILT_FREE(line->page, line->page_mapping, line->size);
0623         return 0;
0624     }
0625     BNX2X_ILT_ZALLOC(line->page, &line->page_mapping, size);
0626     if (!line->page)
0627         return -1;
0628     line->size = size;
0629     return 0;
0630 }
0631 
0632 
0633 static int bnx2x_ilt_client_mem_op(struct bnx2x *bp, int cli_num,
0634                    u8 memop)
0635 {
0636     int i, rc;
0637     struct bnx2x_ilt *ilt = BP_ILT(bp);
0638     struct ilt_client_info *ilt_cli;
0639 
0640     if (!ilt || !ilt->lines)
0641         return -1;
0642 
0643     ilt_cli = &ilt->clients[cli_num];
0644 
0645     if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
0646         return 0;
0647 
0648     for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
0649         rc = bnx2x_ilt_line_mem_op(bp, &ilt->lines[i],
0650                        ilt_cli->page_size, memop);
0651     }
0652     return rc;
0653 }
0654 
0655 static int bnx2x_ilt_mem_op_cnic(struct bnx2x *bp, u8 memop)
0656 {
0657     int rc = 0;
0658 
0659     if (CONFIGURE_NIC_MODE(bp))
0660         rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
0661     if (!rc)
0662         rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_TM, memop);
0663 
0664     return rc;
0665 }
0666 
0667 static int bnx2x_ilt_mem_op(struct bnx2x *bp, u8 memop)
0668 {
0669     int rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_CDU, memop);
0670     if (!rc)
0671         rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_QM, memop);
0672     if (!rc && CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp))
0673         rc = bnx2x_ilt_client_mem_op(bp, ILT_CLIENT_SRC, memop);
0674 
0675     return rc;
0676 }
0677 
0678 static void bnx2x_ilt_line_wr(struct bnx2x *bp, int abs_idx,
0679                   dma_addr_t page_mapping)
0680 {
0681     u32 reg;
0682 
0683     if (CHIP_IS_E1(bp))
0684         reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
0685     else
0686         reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
0687 
0688     bnx2x_wr_64(bp, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
0689 }
0690 
0691 static void bnx2x_ilt_line_init_op(struct bnx2x *bp,
0692                    struct bnx2x_ilt *ilt, int idx, u8 initop)
0693 {
0694     dma_addr_t  null_mapping;
0695     int abs_idx = ilt->start_line + idx;
0696 
0697 
0698     switch (initop) {
0699     case INITOP_INIT:
0700         /* set in the init-value array */
0701     case INITOP_SET:
0702         bnx2x_ilt_line_wr(bp, abs_idx, ilt->lines[idx].page_mapping);
0703         break;
0704     case INITOP_CLEAR:
0705         null_mapping = 0;
0706         bnx2x_ilt_line_wr(bp, abs_idx, null_mapping);
0707         break;
0708     }
0709 }
0710 
0711 static void bnx2x_ilt_boundry_init_op(struct bnx2x *bp,
0712                       struct ilt_client_info *ilt_cli,
0713                       u32 ilt_start, u8 initop)
0714 {
0715     u32 start_reg = 0;
0716     u32 end_reg = 0;
0717 
0718     /* The boundary is either SET or INIT,
0719        CLEAR => SET and for now SET ~~ INIT */
0720 
0721     /* find the appropriate regs */
0722     if (CHIP_IS_E1(bp)) {
0723         switch (ilt_cli->client_num) {
0724         case ILT_CLIENT_CDU:
0725             start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
0726             break;
0727         case ILT_CLIENT_QM:
0728             start_reg = PXP2_REG_PSWRQ_QM0_L2P;
0729             break;
0730         case ILT_CLIENT_SRC:
0731             start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
0732             break;
0733         case ILT_CLIENT_TM:
0734             start_reg = PXP2_REG_PSWRQ_TM0_L2P;
0735             break;
0736         }
0737         REG_WR(bp, start_reg + BP_FUNC(bp)*4,
0738                ILT_RANGE((ilt_start + ilt_cli->start),
0739                  (ilt_start + ilt_cli->end)));
0740     } else {
0741         switch (ilt_cli->client_num) {
0742         case ILT_CLIENT_CDU:
0743             start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
0744             end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
0745             break;
0746         case ILT_CLIENT_QM:
0747             start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
0748             end_reg = PXP2_REG_RQ_QM_LAST_ILT;
0749             break;
0750         case ILT_CLIENT_SRC:
0751             start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
0752             end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
0753             break;
0754         case ILT_CLIENT_TM:
0755             start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
0756             end_reg = PXP2_REG_RQ_TM_LAST_ILT;
0757             break;
0758         }
0759         REG_WR(bp, start_reg, (ilt_start + ilt_cli->start));
0760         REG_WR(bp, end_reg, (ilt_start + ilt_cli->end));
0761     }
0762 }
0763 
0764 static void bnx2x_ilt_client_init_op_ilt(struct bnx2x *bp,
0765                      struct bnx2x_ilt *ilt,
0766                      struct ilt_client_info *ilt_cli,
0767                      u8 initop)
0768 {
0769     int i;
0770 
0771     if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
0772         return;
0773 
0774     for (i = ilt_cli->start; i <= ilt_cli->end; i++)
0775         bnx2x_ilt_line_init_op(bp, ilt, i, initop);
0776 
0777     /* init/clear the ILT boundries */
0778     bnx2x_ilt_boundry_init_op(bp, ilt_cli, ilt->start_line, initop);
0779 }
0780 
0781 static void bnx2x_ilt_client_init_op(struct bnx2x *bp,
0782                      struct ilt_client_info *ilt_cli, u8 initop)
0783 {
0784     struct bnx2x_ilt *ilt = BP_ILT(bp);
0785 
0786     bnx2x_ilt_client_init_op_ilt(bp, ilt, ilt_cli, initop);
0787 }
0788 
0789 static void bnx2x_ilt_client_id_init_op(struct bnx2x *bp,
0790                     int cli_num, u8 initop)
0791 {
0792     struct bnx2x_ilt *ilt = BP_ILT(bp);
0793     struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
0794 
0795     bnx2x_ilt_client_init_op(bp, ilt_cli, initop);
0796 }
0797 
0798 static void bnx2x_ilt_init_op_cnic(struct bnx2x *bp, u8 initop)
0799 {
0800     if (CONFIGURE_NIC_MODE(bp))
0801         bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
0802     bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_TM, initop);
0803 }
0804 
0805 static void bnx2x_ilt_init_op(struct bnx2x *bp, u8 initop)
0806 {
0807     bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_CDU, initop);
0808     bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_QM, initop);
0809     if (CNIC_SUPPORT(bp) && !CONFIGURE_NIC_MODE(bp))
0810         bnx2x_ilt_client_id_init_op(bp, ILT_CLIENT_SRC, initop);
0811 }
0812 
0813 static void bnx2x_ilt_init_client_psz(struct bnx2x *bp, int cli_num,
0814                       u32 psz_reg, u8 initop)
0815 {
0816     struct bnx2x_ilt *ilt = BP_ILT(bp);
0817     struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
0818 
0819     if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
0820         return;
0821 
0822     switch (initop) {
0823     case INITOP_INIT:
0824         /* set in the init-value array */
0825     case INITOP_SET:
0826         REG_WR(bp, psz_reg, ILOG2(ilt_cli->page_size >> 12));
0827         break;
0828     case INITOP_CLEAR:
0829         break;
0830     }
0831 }
0832 
0833 /*
0834  * called during init common stage, ilt clients should be initialized
0835  * prioir to calling this function
0836  */
0837 static void bnx2x_ilt_init_page_size(struct bnx2x *bp, u8 initop)
0838 {
0839     bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_CDU,
0840                   PXP2_REG_RQ_CDU_P_SIZE, initop);
0841     bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_QM,
0842                   PXP2_REG_RQ_QM_P_SIZE, initop);
0843     bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_SRC,
0844                   PXP2_REG_RQ_SRC_P_SIZE, initop);
0845     bnx2x_ilt_init_client_psz(bp, ILT_CLIENT_TM,
0846                   PXP2_REG_RQ_TM_P_SIZE, initop);
0847 }
0848 
0849 /****************************************************************************
0850 * QM initializations
0851 ****************************************************************************/
0852 #define QM_QUEUES_PER_FUNC  16 /* E1 has 32, but only 16 are used */
0853 #define QM_INIT_MIN_CID_COUNT   31
0854 #define QM_INIT(cid_cnt)    (cid_cnt > QM_INIT_MIN_CID_COUNT)
0855 
0856 /* called during init port stage */
0857 static void bnx2x_qm_init_cid_count(struct bnx2x *bp, int qm_cid_count,
0858                     u8 initop)
0859 {
0860     int port = BP_PORT(bp);
0861 
0862     if (QM_INIT(qm_cid_count)) {
0863         switch (initop) {
0864         case INITOP_INIT:
0865             /* set in the init-value array */
0866         case INITOP_SET:
0867             REG_WR(bp, QM_REG_CONNNUM_0 + port*4,
0868                    qm_cid_count/16 - 1);
0869             break;
0870         case INITOP_CLEAR:
0871             break;
0872         }
0873     }
0874 }
0875 
0876 static void bnx2x_qm_set_ptr_table(struct bnx2x *bp, int qm_cid_count,
0877                    u32 base_reg, u32 reg)
0878 {
0879     int i;
0880     u32 wb_data[2] = {0, 0};
0881     for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
0882         REG_WR(bp, base_reg + i*4,
0883                qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
0884         bnx2x_init_wr_wb(bp, reg + i*8,  wb_data, 2);
0885     }
0886 }
0887 
0888 /* called during init common stage */
0889 static void bnx2x_qm_init_ptr_table(struct bnx2x *bp, int qm_cid_count,
0890                     u8 initop)
0891 {
0892     if (!QM_INIT(qm_cid_count))
0893         return;
0894 
0895     switch (initop) {
0896     case INITOP_INIT:
0897         /* set in the init-value array */
0898     case INITOP_SET:
0899         bnx2x_qm_set_ptr_table(bp, qm_cid_count,
0900                        QM_REG_BASEADDR, QM_REG_PTRTBL);
0901         if (CHIP_IS_E1H(bp))
0902             bnx2x_qm_set_ptr_table(bp, qm_cid_count,
0903                            QM_REG_BASEADDR_EXT_A,
0904                            QM_REG_PTRTBL_EXT_A);
0905         break;
0906     case INITOP_CLEAR:
0907         break;
0908     }
0909 }
0910 
0911 /****************************************************************************
0912 * SRC initializations
0913 ****************************************************************************/
0914 /* called during init func stage */
0915 static void bnx2x_src_init_t2(struct bnx2x *bp, struct src_ent *t2,
0916                   dma_addr_t t2_mapping, int src_cid_count)
0917 {
0918     int i;
0919     int port = BP_PORT(bp);
0920 
0921     /* Initialize T2 */
0922     for (i = 0; i < src_cid_count-1; i++)
0923         t2[i].next = (u64)(t2_mapping +
0924                  (i+1)*sizeof(struct src_ent));
0925 
0926     /* tell the searcher where the T2 table is */
0927     REG_WR(bp, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
0928 
0929     bnx2x_wr_64(bp, SRC_REG_FIRSTFREE0 + port*16,
0930             U64_LO(t2_mapping), U64_HI(t2_mapping));
0931 
0932     bnx2x_wr_64(bp, SRC_REG_LASTFREE0 + port*16,
0933             U64_LO((u64)t2_mapping +
0934                (src_cid_count-1) * sizeof(struct src_ent)),
0935             U64_HI((u64)t2_mapping +
0936                (src_cid_count-1) * sizeof(struct src_ent)));
0937 }
0938 #endif /* BNX2X_INIT_OPS_H */
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