broadcom/bnx2x/bnx2x_fw_defs.h

0001 /* bnx2x_fw_defs.h: Qlogic Everest network driver.
0002  *
0003  * Copyright (c) 2007-2013 Broadcom Corporation
0004  * Copyright (c) 2014 QLogic Corporation
0005  * All rights reserved
0006  *
0007  * This program is free software; you can redistribute it and/or modify
0008  * it under the terms of the GNU General Public License as published by
0009  * the Free Software Foundation.
0010  */
0011
0012 #ifndef BNX2X_FW_DEFS_H
0013 #define BNX2X_FW_DEFS_H
0014
0015 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
0016 #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
0017     (IRO[151].base + ((assertListEntry) * IRO[151].m1))
0018 #define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
0019     (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
0020     IRO[157].m2))
0021 #define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
0022     (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
0023     IRO[158].m2))
0024 #define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
0025     (IRO[163].base + ((funcId) * IRO[163].m1))
0026 #define CSTORM_FUNC_EN_OFFSET(funcId) \
0027     (IRO[153].base + ((funcId) * IRO[153].m1))
0028 #define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \
0029     (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
0030 #define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \
0031     (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
0032     * IRO[142].m2) + ((sbId) * IRO[142].m3))
0033 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
0034 #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
0035     (IRO[324].base + ((pfId) * IRO[324].m1))
0036 #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
0037     (IRO[325].base + ((pfId) * IRO[325].m1))
0038 #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
0039     (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
0040 #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
0041     (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
0042 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
0043     (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
0044 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
0045     (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
0046 #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
0047     (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
0048 #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
0049     (IRO[322].base + ((pfId) * IRO[322].m1) + ((iscsiEqId) * IRO[322].m2))
0050 #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
0051     (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
0052 #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
0053     (IRO[323].base + ((pfId) * IRO[323].m1))
0054 #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
0055     (IRO[315].base + ((pfId) * IRO[315].m1))
0056 #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
0057     (IRO[314].base + ((pfId) * IRO[314].m1))
0058 #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
0059     (IRO[313].base + ((pfId) * IRO[313].m1))
0060 #define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
0061     (IRO[155].base + ((funcId) * IRO[155].m1))
0062 #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
0063     (IRO[146].base + ((pfId) * IRO[146].m1))
0064 #define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
0065     (IRO[147].base + ((pfId) * IRO[147].m1))
0066 #define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
0067     (IRO[145].base + ((pfId) * IRO[145].m1))
0068 #define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size)
0069 #define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
0070     (IRO[148].base + ((pfId) * IRO[148].m1))
0071 #define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size)
0072 #define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
0073     (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
0074 #define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
0075     (IRO[137].base + ((sbId) * IRO[137].m1))
0076 #define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
0077     (IRO[138].base + ((sbId) * IRO[138].m1))
0078 #define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
0079     (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
0080 #define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
0081     (IRO[136].base + ((sbId) * IRO[136].m1))
0082 #define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size)
0083 #define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
0084     (IRO[141].base + ((sbId) * IRO[141].m1))
0085 #define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size)
0086 #define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
0087     (IRO[159].base + ((vfId) * IRO[159].m1))
0088 #define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
0089     (IRO[160].base + ((vfId) * IRO[160].m1))
0090 #define CSTORM_VF_TO_PF_OFFSET(funcId) \
0091     (IRO[154].base + ((funcId) * IRO[154].m1))
0092 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
0093     (IRO[207].base + ((pfId) * IRO[207].m1))
0094 #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
0095 #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
0096     (IRO[101].base + ((assertListEntry) * IRO[101].m1))
0097 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
0098     (IRO[205].base + ((pfId) * IRO[205].m1))
0099 #define TSTORM_FUNC_EN_OFFSET(funcId) \
0100     (IRO[107].base + ((funcId) * IRO[107].m1))
0101 #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
0102     (IRO[279].base + ((pfId) * IRO[279].m1))
0103 #define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
0104     (IRO[280].base + ((pfId) * IRO[280].m1))
0105 #define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \
0106     (IRO[281].base + ((pfId) * IRO[281].m1))
0107 #define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \
0108     (IRO[282].base + ((pfId) * IRO[282].m1))
0109 #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
0110     (IRO[278].base + ((pfId) * IRO[278].m1))
0111 #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
0112     (IRO[277].base + ((pfId) * IRO[277].m1))
0113 #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
0114     (IRO[276].base + ((pfId) * IRO[276].m1))
0115 #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
0116     (IRO[275].base + ((pfId) * IRO[275].m1))
0117 #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
0118     (IRO[285].base + ((pfId) * IRO[285].m1))
0119 #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
0120     (IRO[271].base + ((pfId) * IRO[271].m1))
0121 #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
0122     (IRO[272].base + ((pfId) * IRO[272].m1))
0123 #define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
0124     (IRO[273].base + ((pfId) * IRO[273].m1))
0125 #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
0126     (IRO[274].base + ((pfId) * IRO[274].m1))
0127 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
0128     (IRO[206].base + ((pfId) * IRO[206].m1))
0129 #define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
0130     (IRO[109].base + ((funcId) * IRO[109].m1))
0131 #define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
0132     (IRO[224].base + ((pfId) * IRO[224].m1))
0133 #define TSTORM_VF_TO_PF_OFFSET(funcId) \
0134     (IRO[108].base + ((funcId) * IRO[108].m1))
0135 #define USTORM_AGG_DATA_OFFSET (IRO[213].base)
0136 #define USTORM_AGG_DATA_SIZE (IRO[213].size)
0137 #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
0138 #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
0139     (IRO[180].base + ((assertListEntry) * IRO[180].m1))
0140 #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
0141     (IRO[187].base + ((portId) * IRO[187].m1))
0142 #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
0143     (IRO[326].base + ((pfId) * IRO[326].m1))
0144 #define USTORM_FUNC_EN_OFFSET(funcId) \
0145     (IRO[182].base + ((funcId) * IRO[182].m1))
0146 #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
0147     (IRO[290].base + ((pfId) * IRO[290].m1))
0148 #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
0149     (IRO[291].base + ((pfId) * IRO[291].m1))
0150 #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
0151     (IRO[295].base + ((pfId) * IRO[295].m1))
0152 #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
0153     (IRO[292].base + ((pfId) * IRO[292].m1))
0154 #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
0155     (IRO[288].base + ((pfId) * IRO[288].m1))
0156 #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
0157     (IRO[287].base + ((pfId) * IRO[287].m1))
0158 #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
0159     (IRO[286].base + ((pfId) * IRO[286].m1))
0160 #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
0161     (IRO[289].base + ((pfId) * IRO[289].m1))
0162 #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
0163     (IRO[293].base + ((pfId) * IRO[293].m1))
0164 #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
0165     (IRO[294].base + ((pfId) * IRO[294].m1))
0166 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
0167     (IRO[186].base + ((pfId) * IRO[186].m1))
0168 #define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
0169     (IRO[184].base + ((funcId) * IRO[184].m1))
0170 #define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
0171     (IRO[216].base + ((portId) * IRO[216].m1) + ((clientId) * \
0172     IRO[216].m2))
0173 #define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
0174     (IRO[217].base + ((qzoneId) * IRO[217].m1))
0175 #define USTORM_TPA_BTR_OFFSET (IRO[214].base)
0176 #define USTORM_TPA_BTR_SIZE (IRO[214].size)
0177 #define USTORM_VF_TO_PF_OFFSET(funcId) \
0178     (IRO[183].base + ((funcId) * IRO[183].m1))
0179 #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
0180 #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
0181 #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
0182 #define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
0183     (IRO[50].base + ((assertListEntry) * IRO[50].m1))
0184 #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \
0185     (IRO[43].base + ((portId) * IRO[43].m1))
0186 #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \
0187     (IRO[45].base + ((pfId) * IRO[45].m1))
0188 #define XSTORM_FUNC_EN_OFFSET(funcId) \
0189     (IRO[47].base + ((funcId) * IRO[47].m1))
0190 #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
0191     (IRO[303].base + ((pfId) * IRO[303].m1))
0192 #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
0193     (IRO[306].base + ((pfId) * IRO[306].m1))
0194 #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
0195     (IRO[307].base + ((pfId) * IRO[307].m1))
0196 #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
0197     (IRO[308].base + ((pfId) * IRO[308].m1))
0198 #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
0199     (IRO[309].base + ((pfId) * IRO[309].m1))
0200 #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
0201     (IRO[310].base + ((pfId) * IRO[310].m1))
0202 #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
0203     (IRO[311].base + ((pfId) * IRO[311].m1))
0204 #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
0205     (IRO[312].base + ((pfId) * IRO[312].m1))
0206 #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
0207     (IRO[302].base + ((pfId) * IRO[302].m1))
0208 #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
0209     (IRO[301].base + ((pfId) * IRO[301].m1))
0210 #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
0211     (IRO[300].base + ((pfId) * IRO[300].m1))
0212 #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
0213     (IRO[305].base + ((pfId) * IRO[305].m1))
0214 #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
0215     (IRO[304].base + ((pfId) * IRO[304].m1))
0216 #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
0217     (IRO[299].base + ((pfId) * IRO[299].m1))
0218 #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
0219     (IRO[298].base + ((pfId) * IRO[298].m1))
0220 #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
0221     (IRO[297].base + ((pfId) * IRO[297].m1))
0222 #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
0223     (IRO[296].base + ((pfId) * IRO[296].m1))
0224 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
0225     (IRO[44].base + ((pfId) * IRO[44].m1))
0226 #define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
0227     (IRO[49].base + ((funcId) * IRO[49].m1))
0228 #define XSTORM_SPQ_DATA_OFFSET(funcId) \
0229     (IRO[32].base + ((funcId) * IRO[32].m1))
0230 #define XSTORM_SPQ_DATA_SIZE (IRO[32].size)
0231 #define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \
0232     (IRO[30].base + ((funcId) * IRO[30].m1))
0233 #define XSTORM_SPQ_PROD_OFFSET(funcId) \
0234     (IRO[31].base + ((funcId) * IRO[31].m1))
0235 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
0236     (IRO[218].base + ((portId) * IRO[218].m1))
0237 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
0238     (IRO[219].base + ((portId) * IRO[219].m1))
0239 #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
0240     (IRO[221].base + (((pfId)>>1) * IRO[221].m1) + (((pfId)&1) * \
0241     IRO[221].m2))
0242 #define XSTORM_VF_TO_PF_OFFSET(funcId) \
0243     (IRO[48].base + ((funcId) * IRO[48].m1))
0244 #define XSTORM_ETH_FUNCTION_INFO_FP_HSI_VALID_E2_OFFSET(fid)    \
0245     (IRO[386].base + ((fid) * IRO[386].m1))
0246 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
0247
0248 /* eth hsi version */
0249 #define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2)
0250
0251 /* Ethernet Ring parameters */
0252 #define X_ETH_LOCAL_RING_SIZE 13
0253 #define FIRST_BD_IN_PKT 0
0254 #define PARSE_BD_INDEX 1
0255 #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8))
0256 #define U_ETH_NUM_OF_SGES_TO_FETCH 8
0257 #define U_ETH_MAX_SGES_FOR_PACKET 3
0258
0259 /* Rx ring params */
0260 #define U_ETH_LOCAL_BD_RING_SIZE 8
0261 #define U_ETH_LOCAL_SGE_RING_SIZE 10
0262 #define U_ETH_SGL_SIZE 8
0263     /* The fw will padd the buffer with this value, so the IP header \
0264     will be align to 4 Byte */
0265 #define IP_HEADER_ALIGNMENT_PADDING 2
0266
0267 #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \
0268     (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1))
0269
0270 #define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8))
0271 #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8))
0272 #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8))
0273
0274 #define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1)
0275 #define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1)
0276 #define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1)
0277
0278 #define U_ETH_UNDEFINED_Q 0xFF
0279
0280 #define T_ETH_INDIRECTION_TABLE_SIZE 128
0281 #define T_ETH_RSS_KEY 10
0282 #define ETH_NUM_OF_RSS_ENGINES_E2 72
0283
0284 #define FILTER_RULES_COUNT 16
0285 #define MULTICAST_RULES_COUNT 16
0286 #define CLASSIFY_RULES_COUNT 16
0287
0288 /*The CRC32 seed, that is used for the hash(reduction) multicast address */
0289 #define ETH_CRC32_HASH_SEED 0x00000000
0290
0291 #define ETH_CRC32_HASH_BIT_SIZE (8)
0292 #define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1)
0293
0294 /* Maximal L2 clients supported */
0295 #define ETH_MAX_RX_CLIENTS_E1 18
0296 #define ETH_MAX_RX_CLIENTS_E1H 28
0297 #define ETH_MAX_RX_CLIENTS_E2 152
0298
0299 /* Maximal statistics client Ids */
0300 #define MAX_STAT_COUNTER_ID_E1 36
0301 #define MAX_STAT_COUNTER_ID_E1H 56
0302 #define MAX_STAT_COUNTER_ID_E2 140
0303
0304 #define MAX_MAC_CREDIT_E1 192 /* Per Chip */
0305 #define MAX_MAC_CREDIT_E1H 256 /* Per Chip */
0306 #define MAX_MAC_CREDIT_E2 272 /* Per Path */
0307 #define MAX_VLAN_CREDIT_E1 0 /* Per Chip */
0308 #define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */
0309 #define MAX_VLAN_CREDIT_E2 272 /* Per Path */
0310
0311 /* Maximal aggregation queues supported */
0312 #define ETH_MAX_AGGREGATION_QUEUES_E1 32
0313 #define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64
0314
0315 #define ETH_NUM_OF_MCAST_BINS 256
0316 #define ETH_NUM_OF_MCAST_ENGINES_E2 72
0317
0318 #define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3)
0319 #define ETH_MIN_RX_CQES_WITH_TPA_E1 \
0320     (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA)
0321 #define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \
0322     (ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA)
0323
0324 #define DISABLE_STATISTIC_COUNTER_ID_VALUE 0
0325
0326
0327 /* This file defines HSI constants common to all microcode flows */
0328
0329 #define PROTOCOL_STATE_BIT_OFFSET 6
0330
0331 #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
0332 #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
0333 #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET)
0334
0335 /* microcode fixed page page size 4K (chains and ring segments) */
0336 #define MC_PAGE_SIZE 4096
0337
0338 /* Number of indices per slow-path SB */
0339 #define HC_SP_SB_MAX_INDICES 16
0340
0341 /* Number of indices per SB */
0342 #define HC_SB_MAX_INDICES_E1X 8
0343 #define HC_SB_MAX_INDICES_E2 8
0344
0345 #define HC_SB_MAX_SB_E1X 32
0346 #define HC_SB_MAX_SB_E2 136
0347
0348 #define HC_SP_SB_ID 0xde
0349
0350 #define HC_SB_MAX_SM 2
0351
0352 #define HC_SB_MAX_DYNAMIC_INDICES 4
0353
0354 /* max number of slow path commands per port */
0355 #define MAX_RAMRODS_PER_PORT 8
0356
0357 /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
0358
0359 #define TIMERS_TICK_SIZE_CHIP (1e-3)
0360
0361 #define TSEMI_CLK1_RESUL_CHIP (1e-3)
0362
0363 #define XSEMI_CLK1_RESUL_CHIP (1e-3)
0364
0365 #define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
0366 #define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))
0367
0368 /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
0369
0370 #define XSTORM_IP_ID_ROLL_HALF 0x8000
0371 #define XSTORM_IP_ID_ROLL_ALL 0
0372
0373 #define FW_LOG_LIST_SIZE 50
0374
0375 #define NUM_OF_SAFC_BITS 16
0376 #define MAX_COS_NUMBER 4
0377 #define MAX_TRAFFIC_TYPES 8
0378 #define MAX_PFC_PRIORITIES 8
0379 #define MAX_VLAN_PRIORITIES 8
0380     /* used by array traffic_type_to_priority[] to mark traffic type \
0381     that is not mapped to priority*/
0382 #define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
0383
0384 #define C_ERES_PER_PAGE \
0385     (PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem)))
0386 #define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1)
0387
0388 #define STATS_QUERY_CMD_COUNT 16
0389
0390 #define AFEX_LIST_TABLE_SIZE 4096
0391
0392 #define INVALID_VNIC_ID 0xFF
0393
0394 #define UNDEF_IRO 0x80000000
0395
0396 /* used for defining the amount of FCoE tasks supported for PF */
0397 #define MAX_FCOE_FUNCS_PER_ENGINE 2
0398 #define MAX_NUM_FCOE_TASKS_PER_ENGINE 4096
0399
0400 #endif /* BNX2X_FW_DEFS_H */