ethernet/broadcom/bnx2_fw.h

0001 /* bnx2_fw.h: QLogic bnx2 network driver.
0002  *
0003  * Copyright (c) 2004, 2005, 2006, 2007 Broadcom Corporation
0004  * Copyright (c) 2014-2015 QLogic Corporation
0005  *
0006  * This program is free software; you can redistribute it and/or modify
0007  * it under the terms of the GNU General Public License as published by
0008  * the Free Software Foundation.
0009  */
0010
0011 /* Initialized Values for the Completion Processor. */
0012 static const struct cpu_reg cpu_reg_com = {
0013     .mode = BNX2_COM_CPU_MODE,
0014     .mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT,
0015     .mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA,
0016     .state = BNX2_COM_CPU_STATE,
0017     .state_value_clear = 0xffffff,
0018     .gpr0 = BNX2_COM_CPU_REG_FILE,
0019     .evmask = BNX2_COM_CPU_EVENT_MASK,
0020     .pc = BNX2_COM_CPU_PROGRAM_COUNTER,
0021     .inst = BNX2_COM_CPU_INSTRUCTION,
0022     .bp = BNX2_COM_CPU_HW_BREAKPOINT,
0023     .spad_base = BNX2_COM_SCRATCH,
0024     .mips_view_base = 0x8000000,
0025 };
0026
0027 /* Initialized Values the Command Processor. */
0028 static const struct cpu_reg cpu_reg_cp = {
0029     .mode = BNX2_CP_CPU_MODE,
0030     .mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT,
0031     .mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA,
0032     .state = BNX2_CP_CPU_STATE,
0033     .state_value_clear = 0xffffff,
0034     .gpr0 = BNX2_CP_CPU_REG_FILE,
0035     .evmask = BNX2_CP_CPU_EVENT_MASK,
0036     .pc = BNX2_CP_CPU_PROGRAM_COUNTER,
0037     .inst = BNX2_CP_CPU_INSTRUCTION,
0038     .bp = BNX2_CP_CPU_HW_BREAKPOINT,
0039     .spad_base = BNX2_CP_SCRATCH,
0040     .mips_view_base = 0x8000000,
0041 };
0042
0043 /* Initialized Values for the RX Processor. */
0044 static const struct cpu_reg cpu_reg_rxp = {
0045     .mode = BNX2_RXP_CPU_MODE,
0046     .mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT,
0047     .mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA,
0048     .state = BNX2_RXP_CPU_STATE,
0049     .state_value_clear = 0xffffff,
0050     .gpr0 = BNX2_RXP_CPU_REG_FILE,
0051     .evmask = BNX2_RXP_CPU_EVENT_MASK,
0052     .pc = BNX2_RXP_CPU_PROGRAM_COUNTER,
0053     .inst = BNX2_RXP_CPU_INSTRUCTION,
0054     .bp = BNX2_RXP_CPU_HW_BREAKPOINT,
0055     .spad_base = BNX2_RXP_SCRATCH,
0056     .mips_view_base = 0x8000000,
0057 };
0058
0059 /* Initialized Values for the TX Patch-up Processor. */
0060 static const struct cpu_reg cpu_reg_tpat = {
0061     .mode = BNX2_TPAT_CPU_MODE,
0062     .mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT,
0063     .mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA,
0064     .state = BNX2_TPAT_CPU_STATE,
0065     .state_value_clear = 0xffffff,
0066     .gpr0 = BNX2_TPAT_CPU_REG_FILE,
0067     .evmask = BNX2_TPAT_CPU_EVENT_MASK,
0068     .pc = BNX2_TPAT_CPU_PROGRAM_COUNTER,
0069     .inst = BNX2_TPAT_CPU_INSTRUCTION,
0070     .bp = BNX2_TPAT_CPU_HW_BREAKPOINT,
0071     .spad_base = BNX2_TPAT_SCRATCH,
0072     .mips_view_base = 0x8000000,
0073 };
0074
0075 /* Initialized Values for the TX Processor. */
0076 static const struct cpu_reg cpu_reg_txp = {
0077     .mode = BNX2_TXP_CPU_MODE,
0078     .mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT,
0079     .mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA,
0080     .state = BNX2_TXP_CPU_STATE,
0081     .state_value_clear = 0xffffff,
0082     .gpr0 = BNX2_TXP_CPU_REG_FILE,
0083     .evmask = BNX2_TXP_CPU_EVENT_MASK,
0084     .pc = BNX2_TXP_CPU_PROGRAM_COUNTER,
0085     .inst = BNX2_TXP_CPU_INSTRUCTION,
0086     .bp = BNX2_TXP_CPU_HW_BREAKPOINT,
0087     .spad_base = BNX2_TXP_SCRATCH,
0088     .mips_view_base = 0x8000000,
0089 };