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0001 /*
0002  * Driver for (BCM4706)? GBit MAC core on BCMA bus.
0003  *
0004  * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
0005  *
0006  * Licensed under the GNU/GPL. See COPYING for details.
0007  */
0008 
0009 
0010 #define pr_fmt(fmt)     KBUILD_MODNAME ": " fmt
0011 
0012 #include <linux/bcma/bcma.h>
0013 #include <linux/etherdevice.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/bcm47xx_nvram.h>
0016 #include <linux/phy.h>
0017 #include <linux/phy_fixed.h>
0018 #include <net/dsa.h>
0019 #include "bgmac.h"
0020 
0021 static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask,
0022                  u32 value, int timeout)
0023 {
0024     u32 val;
0025     int i;
0026 
0027     for (i = 0; i < timeout / 10; i++) {
0028         val = bgmac_read(bgmac, reg);
0029         if ((val & mask) == value)
0030             return true;
0031         udelay(10);
0032     }
0033     dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg);
0034     return false;
0035 }
0036 
0037 /**************************************************
0038  * DMA
0039  **************************************************/
0040 
0041 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
0042 {
0043     u32 val;
0044     int i;
0045 
0046     if (!ring->mmio_base)
0047         return;
0048 
0049     /* Suspend DMA TX ring first.
0050      * bgmac_wait_value doesn't support waiting for any of few values, so
0051      * implement whole loop here.
0052      */
0053     bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
0054             BGMAC_DMA_TX_SUSPEND);
0055     for (i = 0; i < 10000 / 10; i++) {
0056         val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
0057         val &= BGMAC_DMA_TX_STAT;
0058         if (val == BGMAC_DMA_TX_STAT_DISABLED ||
0059             val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
0060             val == BGMAC_DMA_TX_STAT_STOPPED) {
0061             i = 0;
0062             break;
0063         }
0064         udelay(10);
0065     }
0066     if (i)
0067         dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
0068             ring->mmio_base, val);
0069 
0070     /* Remove SUSPEND bit */
0071     bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
0072     if (!bgmac_wait_value(bgmac,
0073                   ring->mmio_base + BGMAC_DMA_TX_STATUS,
0074                   BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
0075                   10000)) {
0076         dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
0077              ring->mmio_base);
0078         udelay(300);
0079         val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
0080         if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
0081             dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n",
0082                 ring->mmio_base);
0083     }
0084 }
0085 
0086 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
0087                 struct bgmac_dma_ring *ring)
0088 {
0089     u32 ctl;
0090 
0091     ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
0092     if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
0093         ctl &= ~BGMAC_DMA_TX_BL_MASK;
0094         ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
0095 
0096         ctl &= ~BGMAC_DMA_TX_MR_MASK;
0097         ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
0098 
0099         ctl &= ~BGMAC_DMA_TX_PC_MASK;
0100         ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
0101 
0102         ctl &= ~BGMAC_DMA_TX_PT_MASK;
0103         ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
0104     }
0105     ctl |= BGMAC_DMA_TX_ENABLE;
0106     ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
0107     bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
0108 }
0109 
0110 static void
0111 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
0112              int i, int len, u32 ctl0)
0113 {
0114     struct bgmac_slot_info *slot;
0115     struct bgmac_dma_desc *dma_desc;
0116     u32 ctl1;
0117 
0118     if (i == BGMAC_TX_RING_SLOTS - 1)
0119         ctl0 |= BGMAC_DESC_CTL0_EOT;
0120 
0121     ctl1 = len & BGMAC_DESC_CTL1_LEN;
0122 
0123     slot = &ring->slots[i];
0124     dma_desc = &ring->cpu_base[i];
0125     dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
0126     dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
0127     dma_desc->ctl0 = cpu_to_le32(ctl0);
0128     dma_desc->ctl1 = cpu_to_le32(ctl1);
0129 }
0130 
0131 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
0132                     struct bgmac_dma_ring *ring,
0133                     struct sk_buff *skb)
0134 {
0135     struct device *dma_dev = bgmac->dma_dev;
0136     struct net_device *net_dev = bgmac->net_dev;
0137     int index = ring->end % BGMAC_TX_RING_SLOTS;
0138     struct bgmac_slot_info *slot = &ring->slots[index];
0139     int nr_frags;
0140     u32 flags;
0141     int i;
0142 
0143     if (skb->len > BGMAC_DESC_CTL1_LEN) {
0144         netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len);
0145         goto err_drop;
0146     }
0147 
0148     if (skb->ip_summed == CHECKSUM_PARTIAL)
0149         skb_checksum_help(skb);
0150 
0151     nr_frags = skb_shinfo(skb)->nr_frags;
0152 
0153     /* ring->end - ring->start will return the number of valid slots,
0154      * even when ring->end overflows
0155      */
0156     if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
0157         netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n");
0158         netif_stop_queue(net_dev);
0159         return NETDEV_TX_BUSY;
0160     }
0161 
0162     slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
0163                     DMA_TO_DEVICE);
0164     if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
0165         goto err_dma_head;
0166 
0167     flags = BGMAC_DESC_CTL0_SOF;
0168     if (!nr_frags)
0169         flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
0170 
0171     bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
0172     flags = 0;
0173 
0174     for (i = 0; i < nr_frags; i++) {
0175         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0176         int len = skb_frag_size(frag);
0177 
0178         index = (index + 1) % BGMAC_TX_RING_SLOTS;
0179         slot = &ring->slots[index];
0180         slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
0181                           len, DMA_TO_DEVICE);
0182         if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
0183             goto err_dma;
0184 
0185         if (i == nr_frags - 1)
0186             flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
0187 
0188         bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
0189     }
0190 
0191     slot->skb = skb;
0192     netdev_sent_queue(net_dev, skb->len);
0193     ring->end += nr_frags + 1;
0194 
0195     wmb();
0196 
0197     /* Increase ring->end to point empty slot. We tell hardware the first
0198      * slot it should *not* read.
0199      */
0200     bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
0201             ring->index_base +
0202             (ring->end % BGMAC_TX_RING_SLOTS) *
0203             sizeof(struct bgmac_dma_desc));
0204 
0205     if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
0206         netif_stop_queue(net_dev);
0207 
0208     return NETDEV_TX_OK;
0209 
0210 err_dma:
0211     dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
0212              DMA_TO_DEVICE);
0213 
0214     while (i-- > 0) {
0215         int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
0216         struct bgmac_slot_info *slot = &ring->slots[index];
0217         u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
0218         int len = ctl1 & BGMAC_DESC_CTL1_LEN;
0219 
0220         dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
0221     }
0222 
0223 err_dma_head:
0224     netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n",
0225            ring->mmio_base);
0226 
0227 err_drop:
0228     dev_kfree_skb(skb);
0229     net_dev->stats.tx_dropped++;
0230     net_dev->stats.tx_errors++;
0231     return NETDEV_TX_OK;
0232 }
0233 
0234 /* Free transmitted packets */
0235 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
0236 {
0237     struct device *dma_dev = bgmac->dma_dev;
0238     int empty_slot;
0239     unsigned bytes_compl = 0, pkts_compl = 0;
0240 
0241     /* The last slot that hardware didn't consume yet */
0242     empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
0243     empty_slot &= BGMAC_DMA_TX_STATDPTR;
0244     empty_slot -= ring->index_base;
0245     empty_slot &= BGMAC_DMA_TX_STATDPTR;
0246     empty_slot /= sizeof(struct bgmac_dma_desc);
0247 
0248     while (ring->start != ring->end) {
0249         int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
0250         struct bgmac_slot_info *slot = &ring->slots[slot_idx];
0251         u32 ctl0, ctl1;
0252         int len;
0253 
0254         if (slot_idx == empty_slot)
0255             break;
0256 
0257         ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
0258         ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
0259         len = ctl1 & BGMAC_DESC_CTL1_LEN;
0260         if (ctl0 & BGMAC_DESC_CTL0_SOF)
0261             /* Unmap no longer used buffer */
0262             dma_unmap_single(dma_dev, slot->dma_addr, len,
0263                      DMA_TO_DEVICE);
0264         else
0265             dma_unmap_page(dma_dev, slot->dma_addr, len,
0266                        DMA_TO_DEVICE);
0267 
0268         if (slot->skb) {
0269             bgmac->net_dev->stats.tx_bytes += slot->skb->len;
0270             bgmac->net_dev->stats.tx_packets++;
0271             bytes_compl += slot->skb->len;
0272             pkts_compl++;
0273 
0274             /* Free memory! :) */
0275             dev_kfree_skb(slot->skb);
0276             slot->skb = NULL;
0277         }
0278 
0279         slot->dma_addr = 0;
0280         ring->start++;
0281     }
0282 
0283     if (!pkts_compl)
0284         return;
0285 
0286     netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
0287 
0288     if (netif_queue_stopped(bgmac->net_dev))
0289         netif_wake_queue(bgmac->net_dev);
0290 }
0291 
0292 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
0293 {
0294     if (!ring->mmio_base)
0295         return;
0296 
0297     bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
0298     if (!bgmac_wait_value(bgmac,
0299                   ring->mmio_base + BGMAC_DMA_RX_STATUS,
0300                   BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
0301                   10000))
0302         dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n",
0303             ring->mmio_base);
0304 }
0305 
0306 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
0307                 struct bgmac_dma_ring *ring)
0308 {
0309     u32 ctl;
0310 
0311     ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
0312 
0313     /* preserve ONLY bits 16-17 from current hardware value */
0314     ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
0315 
0316     if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
0317         ctl &= ~BGMAC_DMA_RX_BL_MASK;
0318         ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
0319 
0320         ctl &= ~BGMAC_DMA_RX_PC_MASK;
0321         ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
0322 
0323         ctl &= ~BGMAC_DMA_RX_PT_MASK;
0324         ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
0325     }
0326     ctl |= BGMAC_DMA_RX_ENABLE;
0327     ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
0328     ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
0329     ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
0330     bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
0331 }
0332 
0333 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
0334                      struct bgmac_slot_info *slot)
0335 {
0336     struct device *dma_dev = bgmac->dma_dev;
0337     dma_addr_t dma_addr;
0338     struct bgmac_rx_header *rx;
0339     void *buf;
0340 
0341     /* Alloc skb */
0342     buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
0343     if (!buf)
0344         return -ENOMEM;
0345 
0346     /* Poison - if everything goes fine, hardware will overwrite it */
0347     rx = buf + BGMAC_RX_BUF_OFFSET;
0348     rx->len = cpu_to_le16(0xdead);
0349     rx->flags = cpu_to_le16(0xbeef);
0350 
0351     /* Map skb for the DMA */
0352     dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
0353                   BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
0354     if (dma_mapping_error(dma_dev, dma_addr)) {
0355         netdev_err(bgmac->net_dev, "DMA mapping error\n");
0356         put_page(virt_to_head_page(buf));
0357         return -ENOMEM;
0358     }
0359 
0360     /* Update the slot */
0361     slot->buf = buf;
0362     slot->dma_addr = dma_addr;
0363 
0364     return 0;
0365 }
0366 
0367 static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
0368                       struct bgmac_dma_ring *ring)
0369 {
0370     dma_wmb();
0371 
0372     bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
0373             ring->index_base +
0374             ring->end * sizeof(struct bgmac_dma_desc));
0375 }
0376 
0377 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
0378                     struct bgmac_dma_ring *ring, int desc_idx)
0379 {
0380     struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
0381     u32 ctl0 = 0, ctl1 = 0;
0382 
0383     if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
0384         ctl0 |= BGMAC_DESC_CTL0_EOT;
0385     ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
0386     /* Is there any BGMAC device that requires extension? */
0387     /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
0388      * B43_DMA64_DCTL1_ADDREXT_MASK;
0389      */
0390 
0391     dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
0392     dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
0393     dma_desc->ctl0 = cpu_to_le32(ctl0);
0394     dma_desc->ctl1 = cpu_to_le32(ctl1);
0395 
0396     ring->end = desc_idx;
0397 }
0398 
0399 static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
0400                     struct bgmac_slot_info *slot)
0401 {
0402     struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
0403 
0404     dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
0405                 DMA_FROM_DEVICE);
0406     rx->len = cpu_to_le16(0xdead);
0407     rx->flags = cpu_to_le16(0xbeef);
0408     dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
0409                    DMA_FROM_DEVICE);
0410 }
0411 
0412 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
0413                  int weight)
0414 {
0415     u32 end_slot;
0416     int handled = 0;
0417 
0418     end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
0419     end_slot &= BGMAC_DMA_RX_STATDPTR;
0420     end_slot -= ring->index_base;
0421     end_slot &= BGMAC_DMA_RX_STATDPTR;
0422     end_slot /= sizeof(struct bgmac_dma_desc);
0423 
0424     while (ring->start != end_slot) {
0425         struct device *dma_dev = bgmac->dma_dev;
0426         struct bgmac_slot_info *slot = &ring->slots[ring->start];
0427         struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
0428         struct sk_buff *skb;
0429         void *buf = slot->buf;
0430         dma_addr_t dma_addr = slot->dma_addr;
0431         u16 len, flags;
0432 
0433         do {
0434             /* Prepare new skb as replacement */
0435             if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
0436                 bgmac_dma_rx_poison_buf(dma_dev, slot);
0437                 break;
0438             }
0439 
0440             /* Unmap buffer to make it accessible to the CPU */
0441             dma_unmap_single(dma_dev, dma_addr,
0442                      BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
0443 
0444             /* Get info from the header */
0445             len = le16_to_cpu(rx->len);
0446             flags = le16_to_cpu(rx->flags);
0447 
0448             /* Check for poison and drop or pass the packet */
0449             if (len == 0xdead && flags == 0xbeef) {
0450                 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n",
0451                        ring->start);
0452                 put_page(virt_to_head_page(buf));
0453                 bgmac->net_dev->stats.rx_errors++;
0454                 break;
0455             }
0456 
0457             if (len > BGMAC_RX_ALLOC_SIZE) {
0458                 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n",
0459                        ring->start);
0460                 put_page(virt_to_head_page(buf));
0461                 bgmac->net_dev->stats.rx_length_errors++;
0462                 bgmac->net_dev->stats.rx_errors++;
0463                 break;
0464             }
0465 
0466             /* Omit CRC. */
0467             len -= ETH_FCS_LEN;
0468 
0469             skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
0470             if (unlikely(!skb)) {
0471                 netdev_err(bgmac->net_dev, "build_skb failed\n");
0472                 put_page(virt_to_head_page(buf));
0473                 bgmac->net_dev->stats.rx_errors++;
0474                 break;
0475             }
0476             skb_put(skb, BGMAC_RX_FRAME_OFFSET +
0477                 BGMAC_RX_BUF_OFFSET + len);
0478             skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
0479                  BGMAC_RX_BUF_OFFSET);
0480 
0481             skb_checksum_none_assert(skb);
0482             skb->protocol = eth_type_trans(skb, bgmac->net_dev);
0483             bgmac->net_dev->stats.rx_bytes += len;
0484             bgmac->net_dev->stats.rx_packets++;
0485             napi_gro_receive(&bgmac->napi, skb);
0486             handled++;
0487         } while (0);
0488 
0489         bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
0490 
0491         if (++ring->start >= BGMAC_RX_RING_SLOTS)
0492             ring->start = 0;
0493 
0494         if (handled >= weight) /* Should never be greater */
0495             break;
0496     }
0497 
0498     bgmac_dma_rx_update_index(bgmac, ring);
0499 
0500     return handled;
0501 }
0502 
0503 /* Does ring support unaligned addressing? */
0504 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
0505                 struct bgmac_dma_ring *ring,
0506                 enum bgmac_dma_ring_type ring_type)
0507 {
0508     switch (ring_type) {
0509     case BGMAC_DMA_RING_TX:
0510         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
0511                 0xff0);
0512         if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
0513             return true;
0514         break;
0515     case BGMAC_DMA_RING_RX:
0516         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
0517                 0xff0);
0518         if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
0519             return true;
0520         break;
0521     }
0522     return false;
0523 }
0524 
0525 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
0526                    struct bgmac_dma_ring *ring)
0527 {
0528     struct device *dma_dev = bgmac->dma_dev;
0529     struct bgmac_dma_desc *dma_desc = ring->cpu_base;
0530     struct bgmac_slot_info *slot;
0531     int i;
0532 
0533     for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
0534         u32 ctl1 = le32_to_cpu(dma_desc[i].ctl1);
0535         unsigned int len = ctl1 & BGMAC_DESC_CTL1_LEN;
0536 
0537         slot = &ring->slots[i];
0538         dev_kfree_skb(slot->skb);
0539 
0540         if (!slot->dma_addr)
0541             continue;
0542 
0543         if (slot->skb)
0544             dma_unmap_single(dma_dev, slot->dma_addr,
0545                      len, DMA_TO_DEVICE);
0546         else
0547             dma_unmap_page(dma_dev, slot->dma_addr,
0548                        len, DMA_TO_DEVICE);
0549     }
0550 }
0551 
0552 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
0553                    struct bgmac_dma_ring *ring)
0554 {
0555     struct device *dma_dev = bgmac->dma_dev;
0556     struct bgmac_slot_info *slot;
0557     int i;
0558 
0559     for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
0560         slot = &ring->slots[i];
0561         if (!slot->dma_addr)
0562             continue;
0563 
0564         dma_unmap_single(dma_dev, slot->dma_addr,
0565                  BGMAC_RX_BUF_SIZE,
0566                  DMA_FROM_DEVICE);
0567         put_page(virt_to_head_page(slot->buf));
0568         slot->dma_addr = 0;
0569     }
0570 }
0571 
0572 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
0573                      struct bgmac_dma_ring *ring,
0574                      int num_slots)
0575 {
0576     struct device *dma_dev = bgmac->dma_dev;
0577     int size;
0578 
0579     if (!ring->cpu_base)
0580         return;
0581 
0582     /* Free ring of descriptors */
0583     size = num_slots * sizeof(struct bgmac_dma_desc);
0584     dma_free_coherent(dma_dev, size, ring->cpu_base,
0585               ring->dma_base);
0586 }
0587 
0588 static void bgmac_dma_cleanup(struct bgmac *bgmac)
0589 {
0590     int i;
0591 
0592     for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
0593         bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
0594 
0595     for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
0596         bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
0597 }
0598 
0599 static void bgmac_dma_free(struct bgmac *bgmac)
0600 {
0601     int i;
0602 
0603     for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
0604         bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
0605                      BGMAC_TX_RING_SLOTS);
0606 
0607     for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
0608         bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
0609                      BGMAC_RX_RING_SLOTS);
0610 }
0611 
0612 static int bgmac_dma_alloc(struct bgmac *bgmac)
0613 {
0614     struct device *dma_dev = bgmac->dma_dev;
0615     struct bgmac_dma_ring *ring;
0616     static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
0617                      BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
0618     int size; /* ring size: different for Tx and Rx */
0619     int i;
0620 
0621     BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
0622     BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
0623 
0624     if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
0625         if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) {
0626             dev_err(bgmac->dev, "Core does not report 64-bit DMA\n");
0627             return -ENOTSUPP;
0628         }
0629     }
0630 
0631     for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
0632         ring = &bgmac->tx_ring[i];
0633         ring->mmio_base = ring_base[i];
0634 
0635         /* Alloc ring of descriptors */
0636         size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
0637         ring->cpu_base = dma_alloc_coherent(dma_dev, size,
0638                             &ring->dma_base,
0639                             GFP_KERNEL);
0640         if (!ring->cpu_base) {
0641             dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n",
0642                 ring->mmio_base);
0643             goto err_dma_free;
0644         }
0645 
0646         ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
0647                               BGMAC_DMA_RING_TX);
0648         if (ring->unaligned)
0649             ring->index_base = lower_32_bits(ring->dma_base);
0650         else
0651             ring->index_base = 0;
0652 
0653         /* No need to alloc TX slots yet */
0654     }
0655 
0656     for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
0657         ring = &bgmac->rx_ring[i];
0658         ring->mmio_base = ring_base[i];
0659 
0660         /* Alloc ring of descriptors */
0661         size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
0662         ring->cpu_base = dma_alloc_coherent(dma_dev, size,
0663                             &ring->dma_base,
0664                             GFP_KERNEL);
0665         if (!ring->cpu_base) {
0666             dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n",
0667                 ring->mmio_base);
0668             goto err_dma_free;
0669         }
0670 
0671         ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
0672                               BGMAC_DMA_RING_RX);
0673         if (ring->unaligned)
0674             ring->index_base = lower_32_bits(ring->dma_base);
0675         else
0676             ring->index_base = 0;
0677     }
0678 
0679     return 0;
0680 
0681 err_dma_free:
0682     bgmac_dma_free(bgmac);
0683     return -ENOMEM;
0684 }
0685 
0686 static int bgmac_dma_init(struct bgmac *bgmac)
0687 {
0688     struct bgmac_dma_ring *ring;
0689     int i, err;
0690 
0691     for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
0692         ring = &bgmac->tx_ring[i];
0693 
0694         if (!ring->unaligned)
0695             bgmac_dma_tx_enable(bgmac, ring);
0696         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
0697                 lower_32_bits(ring->dma_base));
0698         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
0699                 upper_32_bits(ring->dma_base));
0700         if (ring->unaligned)
0701             bgmac_dma_tx_enable(bgmac, ring);
0702 
0703         ring->start = 0;
0704         ring->end = 0;  /* Points the slot that should *not* be read */
0705     }
0706 
0707     for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
0708         int j;
0709 
0710         ring = &bgmac->rx_ring[i];
0711 
0712         if (!ring->unaligned)
0713             bgmac_dma_rx_enable(bgmac, ring);
0714         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
0715                 lower_32_bits(ring->dma_base));
0716         bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
0717                 upper_32_bits(ring->dma_base));
0718         if (ring->unaligned)
0719             bgmac_dma_rx_enable(bgmac, ring);
0720 
0721         ring->start = 0;
0722         ring->end = 0;
0723         for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
0724             err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
0725             if (err)
0726                 goto error;
0727 
0728             bgmac_dma_rx_setup_desc(bgmac, ring, j);
0729         }
0730 
0731         bgmac_dma_rx_update_index(bgmac, ring);
0732     }
0733 
0734     return 0;
0735 
0736 error:
0737     bgmac_dma_cleanup(bgmac);
0738     return err;
0739 }
0740 
0741 
0742 /**************************************************
0743  * Chip ops
0744  **************************************************/
0745 
0746 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
0747  * nothing to change? Try if after stabilizng driver.
0748  */
0749 static void bgmac_umac_cmd_maskset(struct bgmac *bgmac, u32 mask, u32 set,
0750                    bool force)
0751 {
0752     u32 cmdcfg = bgmac_umac_read(bgmac, UMAC_CMD);
0753     u32 new_val = (cmdcfg & mask) | set;
0754     u32 cmdcfg_sr;
0755 
0756     if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
0757         cmdcfg_sr = CMD_SW_RESET;
0758     else
0759         cmdcfg_sr = CMD_SW_RESET_OLD;
0760 
0761     bgmac_umac_maskset(bgmac, UMAC_CMD, ~0, cmdcfg_sr);
0762     udelay(2);
0763 
0764     if (new_val != cmdcfg || force)
0765         bgmac_umac_write(bgmac, UMAC_CMD, new_val);
0766 
0767     bgmac_umac_maskset(bgmac, UMAC_CMD, ~cmdcfg_sr, 0);
0768     udelay(2);
0769 }
0770 
0771 static void bgmac_write_mac_address(struct bgmac *bgmac, const u8 *addr)
0772 {
0773     u32 tmp;
0774 
0775     tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
0776     bgmac_umac_write(bgmac, UMAC_MAC0, tmp);
0777     tmp = (addr[4] << 8) | addr[5];
0778     bgmac_umac_write(bgmac, UMAC_MAC1, tmp);
0779 }
0780 
0781 static void bgmac_set_rx_mode(struct net_device *net_dev)
0782 {
0783     struct bgmac *bgmac = netdev_priv(net_dev);
0784 
0785     if (net_dev->flags & IFF_PROMISC)
0786         bgmac_umac_cmd_maskset(bgmac, ~0, CMD_PROMISC, true);
0787     else
0788         bgmac_umac_cmd_maskset(bgmac, ~CMD_PROMISC, 0, true);
0789 }
0790 
0791 #if 0 /* We don't use that regs yet */
0792 static void bgmac_chip_stats_update(struct bgmac *bgmac)
0793 {
0794     int i;
0795 
0796     if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
0797         for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
0798             bgmac->mib_tx_regs[i] =
0799                 bgmac_read(bgmac,
0800                        BGMAC_TX_GOOD_OCTETS + (i * 4));
0801         for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
0802             bgmac->mib_rx_regs[i] =
0803                 bgmac_read(bgmac,
0804                        BGMAC_RX_GOOD_OCTETS + (i * 4));
0805     }
0806 
0807     /* TODO: what else? how to handle BCM4706? Specs are needed */
0808 }
0809 #endif
0810 
0811 static void bgmac_clear_mib(struct bgmac *bgmac)
0812 {
0813     int i;
0814 
0815     if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
0816         return;
0817 
0818     bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
0819     for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
0820         bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
0821     for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
0822         bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
0823 }
0824 
0825 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
0826 static void bgmac_mac_speed(struct bgmac *bgmac)
0827 {
0828     u32 mask = ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT | CMD_HD_EN);
0829     u32 set = 0;
0830 
0831     switch (bgmac->mac_speed) {
0832     case SPEED_10:
0833         set |= CMD_SPEED_10 << CMD_SPEED_SHIFT;
0834         break;
0835     case SPEED_100:
0836         set |= CMD_SPEED_100 << CMD_SPEED_SHIFT;
0837         break;
0838     case SPEED_1000:
0839         set |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;
0840         break;
0841     case SPEED_2500:
0842         set |= CMD_SPEED_2500 << CMD_SPEED_SHIFT;
0843         break;
0844     default:
0845         dev_err(bgmac->dev, "Unsupported speed: %d\n",
0846             bgmac->mac_speed);
0847     }
0848 
0849     if (bgmac->mac_duplex == DUPLEX_HALF)
0850         set |= CMD_HD_EN;
0851 
0852     bgmac_umac_cmd_maskset(bgmac, mask, set, true);
0853 }
0854 
0855 static void bgmac_miiconfig(struct bgmac *bgmac)
0856 {
0857     if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
0858         if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
0859             bgmac_idm_write(bgmac, BCMA_IOCTL,
0860                     bgmac_idm_read(bgmac, BCMA_IOCTL) |
0861                     0x40 | BGMAC_BCMA_IOCTL_SW_CLKEN);
0862         }
0863         bgmac->mac_speed = SPEED_2500;
0864         bgmac->mac_duplex = DUPLEX_FULL;
0865         bgmac_mac_speed(bgmac);
0866     } else {
0867         u8 imode;
0868 
0869         imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
0870             BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
0871         if (imode == 0 || imode == 1) {
0872             bgmac->mac_speed = SPEED_100;
0873             bgmac->mac_duplex = DUPLEX_FULL;
0874             bgmac_mac_speed(bgmac);
0875         }
0876     }
0877 }
0878 
0879 static void bgmac_chip_reset_idm_config(struct bgmac *bgmac)
0880 {
0881     u32 iost;
0882 
0883     iost = bgmac_idm_read(bgmac, BCMA_IOST);
0884     if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
0885         iost &= ~BGMAC_BCMA_IOST_ATTACHED;
0886 
0887     /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
0888     if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
0889         u32 flags = 0;
0890 
0891         if (iost & BGMAC_BCMA_IOST_ATTACHED) {
0892             flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
0893             if (!bgmac->has_robosw)
0894                 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
0895         }
0896         bgmac_clk_enable(bgmac, flags);
0897     }
0898 
0899     if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
0900         bgmac_idm_write(bgmac, BCMA_IOCTL,
0901                 bgmac_idm_read(bgmac, BCMA_IOCTL) &
0902                 ~BGMAC_BCMA_IOCTL_SW_RESET);
0903 }
0904 
0905 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
0906 static void bgmac_chip_reset(struct bgmac *bgmac)
0907 {
0908     u32 cmdcfg_sr;
0909     int i;
0910 
0911     if (bgmac_clk_enabled(bgmac)) {
0912         if (!bgmac->stats_grabbed) {
0913             /* bgmac_chip_stats_update(bgmac); */
0914             bgmac->stats_grabbed = true;
0915         }
0916 
0917         for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
0918             bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
0919 
0920         bgmac_umac_cmd_maskset(bgmac, ~0, CMD_LCL_LOOP_EN, false);
0921         udelay(1);
0922 
0923         for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
0924             bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
0925 
0926         /* TODO: Clear software multicast filter list */
0927     }
0928 
0929     if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK))
0930         bgmac_chip_reset_idm_config(bgmac);
0931 
0932     /* Request Misc PLL for corerev > 2 */
0933     if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
0934         bgmac_set(bgmac, BCMA_CLKCTLST,
0935               BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
0936         bgmac_wait_value(bgmac, BCMA_CLKCTLST,
0937                  BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
0938                  BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
0939                  1000);
0940     }
0941 
0942     if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
0943         u8 et_swtype = 0;
0944         u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
0945                  BGMAC_CHIPCTL_1_IF_TYPE_MII;
0946         char buf[4];
0947 
0948         if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
0949             if (kstrtou8(buf, 0, &et_swtype))
0950                 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
0951                     buf);
0952             et_swtype &= 0x0f;
0953             et_swtype <<= 4;
0954             sw_type = et_swtype;
0955         } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
0956             sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII |
0957                   BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
0958         } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
0959             sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
0960                   BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
0961         }
0962         bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
0963                           BGMAC_CHIPCTL_1_SW_TYPE_MASK),
0964                       sw_type);
0965     } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) {
0966         u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII |
0967                   BGMAC_CHIPCTL_4_SW_TYPE_EPHY;
0968         u8 et_swtype = 0;
0969         char buf[4];
0970 
0971         if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
0972             if (kstrtou8(buf, 0, &et_swtype))
0973                 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
0974                     buf);
0975             sw_type = (et_swtype & 0x0f) << 12;
0976         } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) {
0977             sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII |
0978                   BGMAC_CHIPCTL_4_SW_TYPE_RGMII;
0979         }
0980         bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK |
0981                           BGMAC_CHIPCTL_4_SW_TYPE_MASK),
0982                       sw_type);
0983     } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) {
0984         bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK,
0985                       BGMAC_CHIPCTL_7_IF_TYPE_RGMII);
0986     }
0987 
0988     /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
0989      * Specs don't say about using UMAC_CMD_SR, but in this routine
0990      * UMAC_CMD is read _after_ putting chip in a reset. So it has to
0991      * be keps until taking MAC out of the reset.
0992      */
0993     if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
0994         cmdcfg_sr = CMD_SW_RESET;
0995     else
0996         cmdcfg_sr = CMD_SW_RESET_OLD;
0997 
0998     bgmac_umac_cmd_maskset(bgmac,
0999                    ~(CMD_TX_EN |
1000                  CMD_RX_EN |
1001                  CMD_RX_PAUSE_IGNORE |
1002                  CMD_TX_ADDR_INS |
1003                  CMD_HD_EN |
1004                  CMD_LCL_LOOP_EN |
1005                  CMD_CNTL_FRM_EN |
1006                  CMD_RMT_LOOP_EN |
1007                  CMD_RX_ERR_DISC |
1008                  CMD_PRBL_EN |
1009                  CMD_TX_PAUSE_IGNORE |
1010                  CMD_PAD_EN |
1011                  CMD_PAUSE_FWD),
1012                    CMD_PROMISC |
1013                    CMD_NO_LEN_CHK |
1014                    CMD_CNTL_FRM_EN |
1015                    cmdcfg_sr,
1016                    false);
1017     bgmac->mac_speed = SPEED_UNKNOWN;
1018     bgmac->mac_duplex = DUPLEX_UNKNOWN;
1019 
1020     bgmac_clear_mib(bgmac);
1021     if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
1022         bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0,
1023                     BCMA_GMAC_CMN_PC_MTE);
1024     else
1025         bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1026     bgmac_miiconfig(bgmac);
1027     if (bgmac->mii_bus)
1028         bgmac->mii_bus->reset(bgmac->mii_bus);
1029 
1030     netdev_reset_queue(bgmac->net_dev);
1031 }
1032 
1033 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1034 {
1035     bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1036 }
1037 
1038 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1039 {
1040     bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1041     bgmac_read(bgmac, BGMAC_INT_MASK);
1042 }
1043 
1044 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1045 static void bgmac_enable(struct bgmac *bgmac)
1046 {
1047     u32 cmdcfg_sr;
1048     u32 cmdcfg;
1049     u32 mode;
1050 
1051     if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
1052         cmdcfg_sr = CMD_SW_RESET;
1053     else
1054         cmdcfg_sr = CMD_SW_RESET_OLD;
1055 
1056     cmdcfg = bgmac_umac_read(bgmac, UMAC_CMD);
1057     bgmac_umac_cmd_maskset(bgmac, ~(CMD_TX_EN | CMD_RX_EN),
1058                    cmdcfg_sr, true);
1059     udelay(2);
1060     cmdcfg |= CMD_TX_EN | CMD_RX_EN;
1061     bgmac_umac_write(bgmac, UMAC_CMD, cmdcfg);
1062 
1063     mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1064         BGMAC_DS_MM_SHIFT;
1065     if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
1066         bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1067     if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2)
1068         bgmac_cco_ctl_maskset(bgmac, 1, ~0,
1069                       BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1070 
1071     if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
1072                     BGMAC_FEAT_FLW_CTRL2)) {
1073         u32 fl_ctl;
1074 
1075         if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
1076             fl_ctl = 0x2300e1;
1077         else
1078             fl_ctl = 0x03cb04cb;
1079 
1080         bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1081         bgmac_umac_write(bgmac, UMAC_PAUSE_CTRL, 0x27fff);
1082     }
1083 
1084     if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
1085         u32 rxq_ctl;
1086         u16 bp_clk;
1087         u8 mdp;
1088 
1089         rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1090         rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1091         bp_clk = bgmac_get_bus_clock(bgmac) / 1000000;
1092         mdp = (bp_clk * 128 / 1000) - 3;
1093         rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1094         bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1095     }
1096 }
1097 
1098 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1099 static void bgmac_chip_init(struct bgmac *bgmac)
1100 {
1101     /* Clear any erroneously pending interrupts */
1102     bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1103 
1104     /* 1 interrupt per received frame */
1105     bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1106 
1107     /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1108     bgmac_umac_cmd_maskset(bgmac, ~CMD_RX_PAUSE_IGNORE, 0, true);
1109 
1110     bgmac_set_rx_mode(bgmac->net_dev);
1111 
1112     bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1113 
1114     if (bgmac->loopback)
1115         bgmac_umac_cmd_maskset(bgmac, ~0, CMD_LCL_LOOP_EN, false);
1116     else
1117         bgmac_umac_cmd_maskset(bgmac, ~CMD_LCL_LOOP_EN, 0, false);
1118 
1119     bgmac_umac_write(bgmac, UMAC_MAX_FRAME_LEN, 32 + ETHER_MAX_LEN);
1120 
1121     bgmac_chip_intrs_on(bgmac);
1122 
1123     bgmac_enable(bgmac);
1124 }
1125 
1126 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1127 {
1128     struct bgmac *bgmac = netdev_priv(dev_id);
1129 
1130     u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1131     int_status &= bgmac->int_mask;
1132 
1133     if (!int_status)
1134         return IRQ_NONE;
1135 
1136     int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1137     if (int_status)
1138         dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status);
1139 
1140     /* Disable new interrupts until handling existing ones */
1141     bgmac_chip_intrs_off(bgmac);
1142 
1143     napi_schedule(&bgmac->napi);
1144 
1145     return IRQ_HANDLED;
1146 }
1147 
1148 static int bgmac_poll(struct napi_struct *napi, int weight)
1149 {
1150     struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1151     int handled = 0;
1152 
1153     /* Ack */
1154     bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1155 
1156     bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1157     handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1158 
1159     /* Poll again if more events arrived in the meantime */
1160     if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1161         return weight;
1162 
1163     if (handled < weight) {
1164         napi_complete_done(napi, handled);
1165         bgmac_chip_intrs_on(bgmac);
1166     }
1167 
1168     return handled;
1169 }
1170 
1171 /**************************************************
1172  * net_device_ops
1173  **************************************************/
1174 
1175 static int bgmac_open(struct net_device *net_dev)
1176 {
1177     struct bgmac *bgmac = netdev_priv(net_dev);
1178     int err = 0;
1179 
1180     bgmac_chip_reset(bgmac);
1181 
1182     err = bgmac_dma_init(bgmac);
1183     if (err)
1184         return err;
1185 
1186     /* Specs say about reclaiming rings here, but we do that in DMA init */
1187     bgmac_chip_init(bgmac);
1188 
1189     err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED,
1190               net_dev->name, net_dev);
1191     if (err < 0) {
1192         dev_err(bgmac->dev, "IRQ request error: %d!\n", err);
1193         bgmac_dma_cleanup(bgmac);
1194         return err;
1195     }
1196     napi_enable(&bgmac->napi);
1197 
1198     phy_start(net_dev->phydev);
1199 
1200     netif_start_queue(net_dev);
1201 
1202     return 0;
1203 }
1204 
1205 static int bgmac_stop(struct net_device *net_dev)
1206 {
1207     struct bgmac *bgmac = netdev_priv(net_dev);
1208 
1209     netif_carrier_off(net_dev);
1210 
1211     phy_stop(net_dev->phydev);
1212 
1213     napi_disable(&bgmac->napi);
1214     bgmac_chip_intrs_off(bgmac);
1215     free_irq(bgmac->irq, net_dev);
1216 
1217     bgmac_chip_reset(bgmac);
1218     bgmac_dma_cleanup(bgmac);
1219 
1220     return 0;
1221 }
1222 
1223 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1224                     struct net_device *net_dev)
1225 {
1226     struct bgmac *bgmac = netdev_priv(net_dev);
1227     struct bgmac_dma_ring *ring;
1228 
1229     /* No QOS support yet */
1230     ring = &bgmac->tx_ring[0];
1231     return bgmac_dma_tx_add(bgmac, ring, skb);
1232 }
1233 
1234 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1235 {
1236     struct bgmac *bgmac = netdev_priv(net_dev);
1237     struct sockaddr *sa = addr;
1238     int ret;
1239 
1240     ret = eth_prepare_mac_addr_change(net_dev, addr);
1241     if (ret < 0)
1242         return ret;
1243 
1244     eth_hw_addr_set(net_dev, sa->sa_data);
1245     bgmac_write_mac_address(bgmac, net_dev->dev_addr);
1246 
1247     eth_commit_mac_addr_change(net_dev, addr);
1248     return 0;
1249 }
1250 
1251 static int bgmac_change_mtu(struct net_device *net_dev, int mtu)
1252 {
1253     struct bgmac *bgmac = netdev_priv(net_dev);
1254 
1255     bgmac_umac_write(bgmac, UMAC_MAX_FRAME_LEN, 32 + mtu);
1256     return 0;
1257 }
1258 
1259 static const struct net_device_ops bgmac_netdev_ops = {
1260     .ndo_open       = bgmac_open,
1261     .ndo_stop       = bgmac_stop,
1262     .ndo_start_xmit     = bgmac_start_xmit,
1263     .ndo_set_rx_mode    = bgmac_set_rx_mode,
1264     .ndo_set_mac_address    = bgmac_set_mac_address,
1265     .ndo_validate_addr  = eth_validate_addr,
1266     .ndo_eth_ioctl           = phy_do_ioctl_running,
1267     .ndo_change_mtu     = bgmac_change_mtu,
1268 };
1269 
1270 /**************************************************
1271  * ethtool_ops
1272  **************************************************/
1273 
1274 struct bgmac_stat {
1275     u8 size;
1276     u32 offset;
1277     const char *name;
1278 };
1279 
1280 static struct bgmac_stat bgmac_get_strings_stats[] = {
1281     { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" },
1282     { 4, BGMAC_TX_GOOD_PKTS, "tx_good" },
1283     { 8, BGMAC_TX_OCTETS, "tx_octets" },
1284     { 4, BGMAC_TX_PKTS, "tx_pkts" },
1285     { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" },
1286     { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" },
1287     { 4, BGMAC_TX_LEN_64, "tx_64" },
1288     { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" },
1289     { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" },
1290     { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" },
1291     { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" },
1292     { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" },
1293     { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" },
1294     { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" },
1295     { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" },
1296     { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" },
1297     { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" },
1298     { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" },
1299     { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" },
1300     { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" },
1301     { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" },
1302     { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" },
1303     { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" },
1304     { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" },
1305     { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" },
1306     { 4, BGMAC_TX_DEFERED, "tx_defered" },
1307     { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" },
1308     { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" },
1309     { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" },
1310     { 4, BGMAC_TX_Q0_PKTS, "tx_q0" },
1311     { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" },
1312     { 4, BGMAC_TX_Q1_PKTS, "tx_q1" },
1313     { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" },
1314     { 4, BGMAC_TX_Q2_PKTS, "tx_q2" },
1315     { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" },
1316     { 4, BGMAC_TX_Q3_PKTS, "tx_q3" },
1317     { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" },
1318     { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" },
1319     { 4, BGMAC_RX_GOOD_PKTS, "rx_good" },
1320     { 8, BGMAC_RX_OCTETS, "rx_octets" },
1321     { 4, BGMAC_RX_PKTS, "rx_pkts" },
1322     { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" },
1323     { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" },
1324     { 4, BGMAC_RX_LEN_64, "rx_64" },
1325     { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" },
1326     { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" },
1327     { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" },
1328     { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" },
1329     { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" },
1330     { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" },
1331     { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" },
1332     { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" },
1333     { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" },
1334     { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" },
1335     { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" },
1336     { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" },
1337     { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" },
1338     { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" },
1339     { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" },
1340     { 4, BGMAC_RX_CRC_ERRS, "rx_crc" },
1341     { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" },
1342     { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" },
1343     { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" },
1344     { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" },
1345     { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" },
1346     { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" },
1347 };
1348 
1349 #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats)
1350 
1351 static int bgmac_get_sset_count(struct net_device *dev, int string_set)
1352 {
1353     switch (string_set) {
1354     case ETH_SS_STATS:
1355         return BGMAC_STATS_LEN;
1356     }
1357 
1358     return -EOPNOTSUPP;
1359 }
1360 
1361 static void bgmac_get_strings(struct net_device *dev, u32 stringset,
1362                   u8 *data)
1363 {
1364     int i;
1365 
1366     if (stringset != ETH_SS_STATS)
1367         return;
1368 
1369     for (i = 0; i < BGMAC_STATS_LEN; i++)
1370         strlcpy(data + i * ETH_GSTRING_LEN,
1371             bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN);
1372 }
1373 
1374 static void bgmac_get_ethtool_stats(struct net_device *dev,
1375                     struct ethtool_stats *ss, uint64_t *data)
1376 {
1377     struct bgmac *bgmac = netdev_priv(dev);
1378     const struct bgmac_stat *s;
1379     unsigned int i;
1380     u64 val;
1381 
1382     if (!netif_running(dev))
1383         return;
1384 
1385     for (i = 0; i < BGMAC_STATS_LEN; i++) {
1386         s = &bgmac_get_strings_stats[i];
1387         val = 0;
1388         if (s->size == 8)
1389             val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
1390         val |= bgmac_read(bgmac, s->offset);
1391         data[i] = val;
1392     }
1393 }
1394 
1395 static void bgmac_get_drvinfo(struct net_device *net_dev,
1396                   struct ethtool_drvinfo *info)
1397 {
1398     strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1399     strlcpy(info->bus_info, "AXI", sizeof(info->bus_info));
1400 }
1401 
1402 static const struct ethtool_ops bgmac_ethtool_ops = {
1403     .get_strings        = bgmac_get_strings,
1404     .get_sset_count     = bgmac_get_sset_count,
1405     .get_ethtool_stats  = bgmac_get_ethtool_stats,
1406     .get_drvinfo        = bgmac_get_drvinfo,
1407     .get_link_ksettings     = phy_ethtool_get_link_ksettings,
1408     .set_link_ksettings     = phy_ethtool_set_link_ksettings,
1409 };
1410 
1411 /**************************************************
1412  * MII
1413  **************************************************/
1414 
1415 void bgmac_adjust_link(struct net_device *net_dev)
1416 {
1417     struct bgmac *bgmac = netdev_priv(net_dev);
1418     struct phy_device *phy_dev = net_dev->phydev;
1419     bool update = false;
1420 
1421     if (phy_dev->link) {
1422         if (phy_dev->speed != bgmac->mac_speed) {
1423             bgmac->mac_speed = phy_dev->speed;
1424             update = true;
1425         }
1426 
1427         if (phy_dev->duplex != bgmac->mac_duplex) {
1428             bgmac->mac_duplex = phy_dev->duplex;
1429             update = true;
1430         }
1431     }
1432 
1433     if (update) {
1434         bgmac_mac_speed(bgmac);
1435         phy_print_status(phy_dev);
1436     }
1437 }
1438 EXPORT_SYMBOL_GPL(bgmac_adjust_link);
1439 
1440 int bgmac_phy_connect_direct(struct bgmac *bgmac)
1441 {
1442     struct fixed_phy_status fphy_status = {
1443         .link = 1,
1444         .speed = SPEED_1000,
1445         .duplex = DUPLEX_FULL,
1446     };
1447     struct phy_device *phy_dev;
1448     int err;
1449 
1450     phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
1451     if (!phy_dev || IS_ERR(phy_dev)) {
1452         dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
1453         return -ENODEV;
1454     }
1455 
1456     err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1457                  PHY_INTERFACE_MODE_MII);
1458     if (err) {
1459         dev_err(bgmac->dev, "Connecting PHY failed\n");
1460         return err;
1461     }
1462 
1463     return err;
1464 }
1465 EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct);
1466 
1467 struct bgmac *bgmac_alloc(struct device *dev)
1468 {
1469     struct net_device *net_dev;
1470     struct bgmac *bgmac;
1471 
1472     /* Allocation and references */
1473     net_dev = devm_alloc_etherdev(dev, sizeof(*bgmac));
1474     if (!net_dev)
1475         return NULL;
1476 
1477     net_dev->netdev_ops = &bgmac_netdev_ops;
1478     net_dev->ethtool_ops = &bgmac_ethtool_ops;
1479 
1480     bgmac = netdev_priv(net_dev);
1481     bgmac->dev = dev;
1482     bgmac->net_dev = net_dev;
1483 
1484     return bgmac;
1485 }
1486 EXPORT_SYMBOL_GPL(bgmac_alloc);
1487 
1488 int bgmac_enet_probe(struct bgmac *bgmac)
1489 {
1490     struct net_device *net_dev = bgmac->net_dev;
1491     int err;
1492 
1493     bgmac_chip_intrs_off(bgmac);
1494 
1495     net_dev->irq = bgmac->irq;
1496     SET_NETDEV_DEV(net_dev, bgmac->dev);
1497     dev_set_drvdata(bgmac->dev, bgmac);
1498 
1499     if (!is_valid_ether_addr(net_dev->dev_addr)) {
1500         dev_err(bgmac->dev, "Invalid MAC addr: %pM\n",
1501             net_dev->dev_addr);
1502         eth_hw_addr_random(net_dev);
1503         dev_warn(bgmac->dev, "Using random MAC: %pM\n",
1504              net_dev->dev_addr);
1505     }
1506 
1507     /* This (reset &) enable is not preset in specs or reference driver but
1508      * Broadcom does it in arch PCI code when enabling fake PCI device.
1509      */
1510     bgmac_clk_enable(bgmac, 0);
1511 
1512     /* This seems to be fixing IRQ by assigning OOB #6 to the core */
1513     if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
1514         if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)
1515             bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86);
1516     }
1517 
1518     bgmac_chip_reset(bgmac);
1519 
1520     err = bgmac_dma_alloc(bgmac);
1521     if (err) {
1522         dev_err(bgmac->dev, "Unable to alloc memory for DMA\n");
1523         goto err_out;
1524     }
1525 
1526     bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1527     if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1528         bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1529 
1530     netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, NAPI_POLL_WEIGHT);
1531 
1532     err = bgmac_phy_connect(bgmac);
1533     if (err) {
1534         dev_err(bgmac->dev, "Cannot connect to phy\n");
1535         goto err_dma_free;
1536     }
1537 
1538     net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1539     net_dev->hw_features = net_dev->features;
1540     net_dev->vlan_features = net_dev->features;
1541 
1542     /* Omit FCS from max MTU size */
1543     net_dev->max_mtu = BGMAC_RX_MAX_FRAME_SIZE - ETH_FCS_LEN;
1544 
1545     err = register_netdev(bgmac->net_dev);
1546     if (err) {
1547         dev_err(bgmac->dev, "Cannot register net device\n");
1548         goto err_phy_disconnect;
1549     }
1550 
1551     netif_carrier_off(net_dev);
1552 
1553     return 0;
1554 
1555 err_phy_disconnect:
1556     phy_disconnect(net_dev->phydev);
1557 err_dma_free:
1558     bgmac_dma_free(bgmac);
1559 err_out:
1560 
1561     return err;
1562 }
1563 EXPORT_SYMBOL_GPL(bgmac_enet_probe);
1564 
1565 void bgmac_enet_remove(struct bgmac *bgmac)
1566 {
1567     unregister_netdev(bgmac->net_dev);
1568     phy_disconnect(bgmac->net_dev->phydev);
1569     netif_napi_del(&bgmac->napi);
1570     bgmac_dma_free(bgmac);
1571     free_netdev(bgmac->net_dev);
1572 }
1573 EXPORT_SYMBOL_GPL(bgmac_enet_remove);
1574 
1575 int bgmac_enet_suspend(struct bgmac *bgmac)
1576 {
1577     if (!netif_running(bgmac->net_dev))
1578         return 0;
1579 
1580     phy_stop(bgmac->net_dev->phydev);
1581 
1582     netif_stop_queue(bgmac->net_dev);
1583 
1584     napi_disable(&bgmac->napi);
1585 
1586     netif_tx_lock(bgmac->net_dev);
1587     netif_device_detach(bgmac->net_dev);
1588     netif_tx_unlock(bgmac->net_dev);
1589 
1590     bgmac_chip_intrs_off(bgmac);
1591     bgmac_chip_reset(bgmac);
1592     bgmac_dma_cleanup(bgmac);
1593 
1594     return 0;
1595 }
1596 EXPORT_SYMBOL_GPL(bgmac_enet_suspend);
1597 
1598 int bgmac_enet_resume(struct bgmac *bgmac)
1599 {
1600     int rc;
1601 
1602     if (!netif_running(bgmac->net_dev))
1603         return 0;
1604 
1605     rc = bgmac_dma_init(bgmac);
1606     if (rc)
1607         return rc;
1608 
1609     bgmac_chip_init(bgmac);
1610 
1611     napi_enable(&bgmac->napi);
1612 
1613     netif_tx_lock(bgmac->net_dev);
1614     netif_device_attach(bgmac->net_dev);
1615     netif_tx_unlock(bgmac->net_dev);
1616 
1617     netif_start_queue(bgmac->net_dev);
1618 
1619     phy_start(bgmac->net_dev->phydev);
1620 
1621     return 0;
1622 }
1623 EXPORT_SYMBOL_GPL(bgmac_enet_resume);
1624 
1625 MODULE_AUTHOR("Rafał Miłecki");
1626 MODULE_LICENSE("GPL");
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