ethernet/broadcom/bcm63xx_enet.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef BCM63XX_ENET_H_
0003 #define BCM63XX_ENET_H_
0004
0005 #include <linux/types.h>
0006 #include <linux/mii.h>
0007 #include <linux/mutex.h>
0008 #include <linux/phy.h>
0009 #include <linux/platform_device.h>
0010
0011 #include <bcm63xx_regs.h>
0012 #include <bcm63xx_io.h>
0013 #include <bcm63xx_iudma.h>
0014
0015 /* default number of descriptor */
0016 #define BCMENET_DEF_RX_DESC 64
0017 #define BCMENET_DEF_TX_DESC 32
0018
0019 /* maximum burst len for dma (4 bytes unit) */
0020 #define BCMENET_DMA_MAXBURST    16
0021 #define BCMENETSW_DMA_MAXBURST  8
0022
0023 /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
0024  * must be low enough so that a DMA transfer of above burst length can
0025  * not overflow the fifo  */
0026 #define BCMENET_TX_FIFO_TRESH   32
0027
0028 /*
0029  * hardware maximum rx/tx packet size including FCS, max mtu is
0030  * actually 2047, but if we set max rx size register to 2047 we won't
0031  * get overflow information if packet size is 2048 or above
0032  */
0033 #define BCMENET_MAX_MTU     2046
0034
0035 /*
0036  * MIB Counters register definitions
0037 */
0038 #define ETH_MIB_TX_GD_OCTETS            0
0039 #define ETH_MIB_TX_GD_PKTS          1
0040 #define ETH_MIB_TX_ALL_OCTETS           2
0041 #define ETH_MIB_TX_ALL_PKTS         3
0042 #define ETH_MIB_TX_BRDCAST          4
0043 #define ETH_MIB_TX_MULT             5
0044 #define ETH_MIB_TX_64               6
0045 #define ETH_MIB_TX_65_127           7
0046 #define ETH_MIB_TX_128_255          8
0047 #define ETH_MIB_TX_256_511          9
0048 #define ETH_MIB_TX_512_1023         10
0049 #define ETH_MIB_TX_1024_MAX         11
0050 #define ETH_MIB_TX_JAB              12
0051 #define ETH_MIB_TX_OVR              13
0052 #define ETH_MIB_TX_FRAG             14
0053 #define ETH_MIB_TX_UNDERRUN         15
0054 #define ETH_MIB_TX_COL              16
0055 #define ETH_MIB_TX_1_COL            17
0056 #define ETH_MIB_TX_M_COL            18
0057 #define ETH_MIB_TX_EX_COL           19
0058 #define ETH_MIB_TX_LATE             20
0059 #define ETH_MIB_TX_DEF              21
0060 #define ETH_MIB_TX_CRS              22
0061 #define ETH_MIB_TX_PAUSE            23
0062
0063 #define ETH_MIB_RX_GD_OCTETS            32
0064 #define ETH_MIB_RX_GD_PKTS          33
0065 #define ETH_MIB_RX_ALL_OCTETS           34
0066 #define ETH_MIB_RX_ALL_PKTS         35
0067 #define ETH_MIB_RX_BRDCAST          36
0068 #define ETH_MIB_RX_MULT             37
0069 #define ETH_MIB_RX_64               38
0070 #define ETH_MIB_RX_65_127           39
0071 #define ETH_MIB_RX_128_255          40
0072 #define ETH_MIB_RX_256_511          41
0073 #define ETH_MIB_RX_512_1023         42
0074 #define ETH_MIB_RX_1024_MAX         43
0075 #define ETH_MIB_RX_JAB              44
0076 #define ETH_MIB_RX_OVR              45
0077 #define ETH_MIB_RX_FRAG             46
0078 #define ETH_MIB_RX_DROP             47
0079 #define ETH_MIB_RX_CRC_ALIGN            48
0080 #define ETH_MIB_RX_UND              49
0081 #define ETH_MIB_RX_CRC              50
0082 #define ETH_MIB_RX_ALIGN            51
0083 #define ETH_MIB_RX_SYM              52
0084 #define ETH_MIB_RX_PAUSE            53
0085 #define ETH_MIB_RX_CNTRL            54
0086
0087
0088 /*
0089  * SW MIB Counters register definitions
0090 */
0091 #define ETHSW_MIB_TX_ALL_OCT            0
0092 #define ETHSW_MIB_TX_DROP_PKTS          2
0093 #define ETHSW_MIB_TX_QOS_PKTS           3
0094 #define ETHSW_MIB_TX_BRDCAST            4
0095 #define ETHSW_MIB_TX_MULT           5
0096 #define ETHSW_MIB_TX_UNI            6
0097 #define ETHSW_MIB_TX_COL            7
0098 #define ETHSW_MIB_TX_1_COL          8
0099 #define ETHSW_MIB_TX_M_COL          9
0100 #define ETHSW_MIB_TX_DEF            10
0101 #define ETHSW_MIB_TX_LATE           11
0102 #define ETHSW_MIB_TX_EX_COL         12
0103 #define ETHSW_MIB_TX_PAUSE          14
0104 #define ETHSW_MIB_TX_QOS_OCT            15
0105
0106 #define ETHSW_MIB_RX_ALL_OCT            17
0107 #define ETHSW_MIB_RX_UND            19
0108 #define ETHSW_MIB_RX_PAUSE          20
0109 #define ETHSW_MIB_RX_64             21
0110 #define ETHSW_MIB_RX_65_127         22
0111 #define ETHSW_MIB_RX_128_255            23
0112 #define ETHSW_MIB_RX_256_511            24
0113 #define ETHSW_MIB_RX_512_1023           25
0114 #define ETHSW_MIB_RX_1024_1522          26
0115 #define ETHSW_MIB_RX_OVR            27
0116 #define ETHSW_MIB_RX_JAB            28
0117 #define ETHSW_MIB_RX_ALIGN          29
0118 #define ETHSW_MIB_RX_CRC            30
0119 #define ETHSW_MIB_RX_GD_OCT         31
0120 #define ETHSW_MIB_RX_DROP           33
0121 #define ETHSW_MIB_RX_UNI            34
0122 #define ETHSW_MIB_RX_MULT           35
0123 #define ETHSW_MIB_RX_BRDCAST            36
0124 #define ETHSW_MIB_RX_SA_CHANGE          37
0125 #define ETHSW_MIB_RX_FRAG           38
0126 #define ETHSW_MIB_RX_OVR_DISC           39
0127 #define ETHSW_MIB_RX_SYM            40
0128 #define ETHSW_MIB_RX_QOS_PKTS           41
0129 #define ETHSW_MIB_RX_QOS_OCT            42
0130 #define ETHSW_MIB_RX_1523_2047          44
0131 #define ETHSW_MIB_RX_2048_4095          45
0132 #define ETHSW_MIB_RX_4096_8191          46
0133 #define ETHSW_MIB_RX_8192_9728          47
0134
0135
0136 struct bcm_enet_mib_counters {
0137     u64 tx_gd_octets;
0138     u32 tx_gd_pkts;
0139     u32 tx_all_octets;
0140     u32 tx_all_pkts;
0141     u32 tx_unicast;
0142     u32 tx_brdcast;
0143     u32 tx_mult;
0144     u32 tx_64;
0145     u32 tx_65_127;
0146     u32 tx_128_255;
0147     u32 tx_256_511;
0148     u32 tx_512_1023;
0149     u32 tx_1024_max;
0150     u32 tx_1523_2047;
0151     u32 tx_2048_4095;
0152     u32 tx_4096_8191;
0153     u32 tx_8192_9728;
0154     u32 tx_jab;
0155     u32 tx_drop;
0156     u32 tx_ovr;
0157     u32 tx_frag;
0158     u32 tx_underrun;
0159     u32 tx_col;
0160     u32 tx_1_col;
0161     u32 tx_m_col;
0162     u32 tx_ex_col;
0163     u32 tx_late;
0164     u32 tx_def;
0165     u32 tx_crs;
0166     u32 tx_pause;
0167     u64 rx_gd_octets;
0168     u32 rx_gd_pkts;
0169     u32 rx_all_octets;
0170     u32 rx_all_pkts;
0171     u32 rx_brdcast;
0172     u32 rx_unicast;
0173     u32 rx_mult;
0174     u32 rx_64;
0175     u32 rx_65_127;
0176     u32 rx_128_255;
0177     u32 rx_256_511;
0178     u32 rx_512_1023;
0179     u32 rx_1024_max;
0180     u32 rx_jab;
0181     u32 rx_ovr;
0182     u32 rx_frag;
0183     u32 rx_drop;
0184     u32 rx_crc_align;
0185     u32 rx_und;
0186     u32 rx_crc;
0187     u32 rx_align;
0188     u32 rx_sym;
0189     u32 rx_pause;
0190     u32 rx_cntrl;
0191 };
0192
0193
0194 struct bcm_enet_priv {
0195
0196     /* base remapped address of device */
0197     void __iomem *base;
0198
0199     /* mac irq, rx_dma irq, tx_dma irq */
0200     int irq;
0201     int irq_rx;
0202     int irq_tx;
0203
0204     /* hw view of rx & tx dma ring */
0205     dma_addr_t rx_desc_dma;
0206     dma_addr_t tx_desc_dma;
0207
0208     /* allocated size (in bytes) for rx & tx dma ring */
0209     unsigned int rx_desc_alloc_size;
0210     unsigned int tx_desc_alloc_size;
0211
0212
0213     struct napi_struct napi;
0214
0215     /* dma channel id for rx */
0216     int rx_chan;
0217
0218     /* number of dma desc in rx ring */
0219     int rx_ring_size;
0220
0221     /* cpu view of rx dma ring */
0222     struct bcm_enet_desc *rx_desc_cpu;
0223
0224     /* current number of armed descriptor given to hardware for rx */
0225     int rx_desc_count;
0226
0227     /* next rx descriptor to fetch from hardware */
0228     int rx_curr_desc;
0229
0230     /* next dirty rx descriptor to refill */
0231     int rx_dirty_desc;
0232
0233     /* size of allocated rx buffers */
0234     unsigned int rx_buf_size;
0235
0236     /* allocated rx buffer offset */
0237     unsigned int rx_buf_offset;
0238
0239     /* size of allocated rx frag */
0240     unsigned int rx_frag_size;
0241
0242     /* list of buffer given to hw for rx */
0243     void **rx_buf;
0244
0245     /* used when rx skb allocation failed, so we defer rx queue
0246      * refill */
0247     struct timer_list rx_timeout;
0248
0249     /* lock rx_timeout against rx normal operation */
0250     spinlock_t rx_lock;
0251
0252
0253     /* dma channel id for tx */
0254     int tx_chan;
0255
0256     /* number of dma desc in tx ring */
0257     int tx_ring_size;
0258
0259     /* maximum dma burst size */
0260     int dma_maxburst;
0261
0262     /* cpu view of rx dma ring */
0263     struct bcm_enet_desc *tx_desc_cpu;
0264
0265     /* number of available descriptor for tx */
0266     int tx_desc_count;
0267
0268     /* next tx descriptor avaiable */
0269     int tx_curr_desc;
0270
0271     /* next dirty tx descriptor to reclaim */
0272     int tx_dirty_desc;
0273
0274     /* list of skb given to hw for tx */
0275     struct sk_buff **tx_skb;
0276
0277     /* lock used by tx reclaim and xmit */
0278     spinlock_t tx_lock;
0279
0280
0281     /* set if internal phy is ignored and external mii interface
0282      * is selected */
0283     int use_external_mii;
0284
0285     /* set if a phy is connected, phy address must be known,
0286      * probing is not possible */
0287     int has_phy;
0288     int phy_id;
0289
0290     /* set if connected phy has an associated irq */
0291     int has_phy_interrupt;
0292     int phy_interrupt;
0293
0294     /* used when a phy is connected (phylib used) */
0295     struct mii_bus *mii_bus;
0296     int old_link;
0297     int old_duplex;
0298     int old_pause;
0299
0300     /* used when no phy is connected */
0301     int force_speed_100;
0302     int force_duplex_full;
0303
0304     /* pause parameters */
0305     int pause_auto;
0306     int pause_rx;
0307     int pause_tx;
0308
0309     /* stats */
0310     struct bcm_enet_mib_counters mib;
0311
0312     /* after mib interrupt, mib registers update is done in this
0313      * work queue */
0314     struct work_struct mib_update_task;
0315
0316     /* lock mib update between userspace request and workqueue */
0317     struct mutex mib_update_lock;
0318
0319     /* mac clock */
0320     struct clk *mac_clk;
0321
0322     /* phy clock if internal phy is used */
0323     struct clk *phy_clk;
0324
0325     /* network device reference */
0326     struct net_device *net_dev;
0327
0328     /* platform device reference */
0329     struct platform_device *pdev;
0330
0331     /* maximum hardware transmit/receive size */
0332     unsigned int hw_mtu;
0333
0334     bool enet_is_sw;
0335
0336     /* port mapping for switch devices */
0337     int num_ports;
0338     struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
0339     int sw_port_link[ENETSW_MAX_PORT];
0340
0341     /* used to poll switch port state */
0342     struct timer_list swphy_poll;
0343     spinlock_t enetsw_mdio_lock;
0344
0345     /* dma channel enable mask */
0346     u32 dma_chan_en_mask;
0347
0348     /* dma channel interrupt mask */
0349     u32 dma_chan_int_mask;
0350
0351     /* DMA engine has internal SRAM */
0352     bool dma_has_sram;
0353
0354     /* dma channel width */
0355     unsigned int dma_chan_width;
0356
0357     /* dma descriptor shift value */
0358     unsigned int dma_desc_shift;
0359 };
0360
0361
0362 #endif /* ! BCM63XX_ENET_H_ */