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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2021 Rafał Miłecki <rafal@milecki.pl>
0004  */
0005 
0006 #include <linux/delay.h>
0007 #include <linux/etherdevice.h>
0008 #include <linux/if_vlan.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_net.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/slab.h>
0015 #include <linux/string.h>
0016 
0017 #include "bcm4908_enet.h"
0018 #include "unimac.h"
0019 
0020 #define ENET_DMA_CH_RX_CFG          ENET_DMA_CH0_CFG
0021 #define ENET_DMA_CH_TX_CFG          ENET_DMA_CH1_CFG
0022 #define ENET_DMA_CH_RX_STATE_RAM        ENET_DMA_CH0_STATE_RAM
0023 #define ENET_DMA_CH_TX_STATE_RAM        ENET_DMA_CH1_STATE_RAM
0024 
0025 #define ENET_TX_BDS_NUM             200
0026 #define ENET_RX_BDS_NUM             200
0027 #define ENET_RX_BDS_NUM_MAX         8192
0028 
0029 #define ENET_DMA_INT_DEFAULTS           (ENET_DMA_CH_CFG_INT_DONE | \
0030                          ENET_DMA_CH_CFG_INT_NO_DESC | \
0031                          ENET_DMA_CH_CFG_INT_BUFF_DONE)
0032 #define ENET_DMA_MAX_BURST_LEN          8 /* in 64 bit words */
0033 
0034 #define ENET_MTU_MAX                ETH_DATA_LEN /* Is it possible to support 2044? */
0035 #define BRCM_MAX_TAG_LEN            6
0036 #define ENET_MAX_ETH_OVERHEAD           (ETH_HLEN + BRCM_MAX_TAG_LEN + VLAN_HLEN + \
0037                          ETH_FCS_LEN + 4) /* 32 */
0038 
0039 struct bcm4908_enet_dma_ring_bd {
0040     __le32 ctl;
0041     __le32 addr;
0042 } __packed;
0043 
0044 struct bcm4908_enet_dma_ring_slot {
0045     struct sk_buff *skb;
0046     unsigned int len;
0047     dma_addr_t dma_addr;
0048 };
0049 
0050 struct bcm4908_enet_dma_ring {
0051     int is_tx;
0052     int read_idx;
0053     int write_idx;
0054     int length;
0055     u16 cfg_block;
0056     u16 st_ram_block;
0057     struct napi_struct napi;
0058 
0059     union {
0060         void *cpu_addr;
0061         struct bcm4908_enet_dma_ring_bd *buf_desc;
0062     };
0063     dma_addr_t dma_addr;
0064 
0065     struct bcm4908_enet_dma_ring_slot *slots;
0066 };
0067 
0068 struct bcm4908_enet {
0069     struct device *dev;
0070     struct net_device *netdev;
0071     void __iomem *base;
0072     int irq_tx;
0073 
0074     struct bcm4908_enet_dma_ring tx_ring;
0075     struct bcm4908_enet_dma_ring rx_ring;
0076 };
0077 
0078 /***
0079  * R/W ops
0080  */
0081 
0082 static u32 enet_read(struct bcm4908_enet *enet, u16 offset)
0083 {
0084     return readl(enet->base + offset);
0085 }
0086 
0087 static void enet_write(struct bcm4908_enet *enet, u16 offset, u32 value)
0088 {
0089     writel(value, enet->base + offset);
0090 }
0091 
0092 static void enet_maskset(struct bcm4908_enet *enet, u16 offset, u32 mask, u32 set)
0093 {
0094     u32 val;
0095 
0096     WARN_ON(set & ~mask);
0097 
0098     val = enet_read(enet, offset);
0099     val = (val & ~mask) | (set & mask);
0100     enet_write(enet, offset, val);
0101 }
0102 
0103 static void enet_set(struct bcm4908_enet *enet, u16 offset, u32 set)
0104 {
0105     enet_maskset(enet, offset, set, set);
0106 }
0107 
0108 static u32 enet_umac_read(struct bcm4908_enet *enet, u16 offset)
0109 {
0110     return enet_read(enet, ENET_UNIMAC + offset);
0111 }
0112 
0113 static void enet_umac_write(struct bcm4908_enet *enet, u16 offset, u32 value)
0114 {
0115     enet_write(enet, ENET_UNIMAC + offset, value);
0116 }
0117 
0118 static void enet_umac_set(struct bcm4908_enet *enet, u16 offset, u32 set)
0119 {
0120     enet_set(enet, ENET_UNIMAC + offset, set);
0121 }
0122 
0123 /***
0124  * Helpers
0125  */
0126 
0127 static void bcm4908_enet_set_mtu(struct bcm4908_enet *enet, int mtu)
0128 {
0129     enet_umac_write(enet, UMAC_MAX_FRAME_LEN, mtu + ENET_MAX_ETH_OVERHEAD);
0130 }
0131 
0132 /***
0133  * DMA ring ops
0134  */
0135 
0136 static void bcm4908_enet_dma_ring_intrs_on(struct bcm4908_enet *enet,
0137                        struct bcm4908_enet_dma_ring *ring)
0138 {
0139     enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, ENET_DMA_INT_DEFAULTS);
0140 }
0141 
0142 static void bcm4908_enet_dma_ring_intrs_off(struct bcm4908_enet *enet,
0143                         struct bcm4908_enet_dma_ring *ring)
0144 {
0145     enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
0146 }
0147 
0148 static void bcm4908_enet_dma_ring_intrs_ack(struct bcm4908_enet *enet,
0149                         struct bcm4908_enet_dma_ring *ring)
0150 {
0151     enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_STAT, ENET_DMA_INT_DEFAULTS);
0152 }
0153 
0154 /***
0155  * DMA
0156  */
0157 
0158 static int bcm4908_dma_alloc_buf_descs(struct bcm4908_enet *enet,
0159                        struct bcm4908_enet_dma_ring *ring)
0160 {
0161     int size = ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);
0162     struct device *dev = enet->dev;
0163 
0164     ring->cpu_addr = dma_alloc_coherent(dev, size, &ring->dma_addr, GFP_KERNEL);
0165     if (!ring->cpu_addr)
0166         return -ENOMEM;
0167 
0168     if (((uintptr_t)ring->cpu_addr) & (0x40 - 1)) {
0169         dev_err(dev, "Invalid DMA ring alignment\n");
0170         goto err_free_buf_descs;
0171     }
0172 
0173     ring->slots = kcalloc(ring->length, sizeof(*ring->slots), GFP_KERNEL);
0174     if (!ring->slots)
0175         goto err_free_buf_descs;
0176 
0177     return 0;
0178 
0179 err_free_buf_descs:
0180     dma_free_coherent(dev, size, ring->cpu_addr, ring->dma_addr);
0181     ring->cpu_addr = NULL;
0182     return -ENOMEM;
0183 }
0184 
0185 static void bcm4908_enet_dma_free(struct bcm4908_enet *enet)
0186 {
0187     struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;
0188     struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
0189     struct device *dev = enet->dev;
0190     int size;
0191 
0192     size = rx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);
0193     if (rx_ring->cpu_addr)
0194         dma_free_coherent(dev, size, rx_ring->cpu_addr, rx_ring->dma_addr);
0195     kfree(rx_ring->slots);
0196 
0197     size = tx_ring->length * sizeof(struct bcm4908_enet_dma_ring_bd);
0198     if (tx_ring->cpu_addr)
0199         dma_free_coherent(dev, size, tx_ring->cpu_addr, tx_ring->dma_addr);
0200     kfree(tx_ring->slots);
0201 }
0202 
0203 static int bcm4908_enet_dma_alloc(struct bcm4908_enet *enet)
0204 {
0205     struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;
0206     struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
0207     struct device *dev = enet->dev;
0208     int err;
0209 
0210     tx_ring->length = ENET_TX_BDS_NUM;
0211     tx_ring->is_tx = 1;
0212     tx_ring->cfg_block = ENET_DMA_CH_TX_CFG;
0213     tx_ring->st_ram_block = ENET_DMA_CH_TX_STATE_RAM;
0214     err = bcm4908_dma_alloc_buf_descs(enet, tx_ring);
0215     if (err) {
0216         dev_err(dev, "Failed to alloc TX buf descriptors: %d\n", err);
0217         return err;
0218     }
0219 
0220     rx_ring->length = ENET_RX_BDS_NUM;
0221     rx_ring->is_tx = 0;
0222     rx_ring->cfg_block = ENET_DMA_CH_RX_CFG;
0223     rx_ring->st_ram_block = ENET_DMA_CH_RX_STATE_RAM;
0224     err = bcm4908_dma_alloc_buf_descs(enet, rx_ring);
0225     if (err) {
0226         dev_err(dev, "Failed to alloc RX buf descriptors: %d\n", err);
0227         bcm4908_enet_dma_free(enet);
0228         return err;
0229     }
0230 
0231     return 0;
0232 }
0233 
0234 static void bcm4908_enet_dma_reset(struct bcm4908_enet *enet)
0235 {
0236     struct bcm4908_enet_dma_ring *rings[] = { &enet->rx_ring, &enet->tx_ring };
0237     int i;
0238 
0239     /* Disable the DMA controller and channel */
0240     for (i = 0; i < ARRAY_SIZE(rings); i++)
0241         enet_write(enet, rings[i]->cfg_block + ENET_DMA_CH_CFG, 0);
0242     enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN, 0);
0243 
0244     /* Reset channels state */
0245     for (i = 0; i < ARRAY_SIZE(rings); i++) {
0246         struct bcm4908_enet_dma_ring *ring = rings[i];
0247 
0248         enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR, 0);
0249         enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_STATE_DATA, 0);
0250         enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_LEN_STATUS, 0);
0251         enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_DESC_BASE_BUFPTR, 0);
0252     }
0253 }
0254 
0255 static int bcm4908_enet_dma_alloc_rx_buf(struct bcm4908_enet *enet, unsigned int idx)
0256 {
0257     struct bcm4908_enet_dma_ring_bd *buf_desc = &enet->rx_ring.buf_desc[idx];
0258     struct bcm4908_enet_dma_ring_slot *slot = &enet->rx_ring.slots[idx];
0259     struct device *dev = enet->dev;
0260     u32 tmp;
0261     int err;
0262 
0263     slot->len = ENET_MTU_MAX + ENET_MAX_ETH_OVERHEAD;
0264 
0265     slot->skb = netdev_alloc_skb(enet->netdev, slot->len);
0266     if (!slot->skb)
0267         return -ENOMEM;
0268 
0269     slot->dma_addr = dma_map_single(dev, slot->skb->data, slot->len, DMA_FROM_DEVICE);
0270     err = dma_mapping_error(dev, slot->dma_addr);
0271     if (err) {
0272         dev_err(dev, "Failed to map DMA buffer: %d\n", err);
0273         kfree_skb(slot->skb);
0274         slot->skb = NULL;
0275         return err;
0276     }
0277 
0278     tmp = slot->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
0279     tmp |= DMA_CTL_STATUS_OWN;
0280     if (idx == enet->rx_ring.length - 1)
0281         tmp |= DMA_CTL_STATUS_WRAP;
0282     buf_desc->ctl = cpu_to_le32(tmp);
0283     buf_desc->addr = cpu_to_le32(slot->dma_addr);
0284 
0285     return 0;
0286 }
0287 
0288 static void bcm4908_enet_dma_ring_init(struct bcm4908_enet *enet,
0289                        struct bcm4908_enet_dma_ring *ring)
0290 {
0291     int reset_channel = 0; /* We support only 1 main channel (with TX and RX) */
0292     int reset_subch = ring->is_tx ? 1 : 0;
0293 
0294     /* Reset the DMA channel */
0295     enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, BIT(reset_channel * 2 + reset_subch));
0296     enet_write(enet, ENET_DMA_CTRL_CHANNEL_RESET, 0);
0297 
0298     enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
0299     enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_MAX_BURST, ENET_DMA_MAX_BURST_LEN);
0300     enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG_INT_MASK, 0);
0301 
0302     enet_write(enet, ring->st_ram_block + ENET_DMA_CH_STATE_RAM_BASE_DESC_PTR,
0303            (uint32_t)ring->dma_addr);
0304 
0305     ring->read_idx = 0;
0306     ring->write_idx = 0;
0307 }
0308 
0309 static void bcm4908_enet_dma_uninit(struct bcm4908_enet *enet)
0310 {
0311     struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
0312     struct bcm4908_enet_dma_ring_slot *slot;
0313     struct device *dev = enet->dev;
0314     int i;
0315 
0316     for (i = rx_ring->length - 1; i >= 0; i--) {
0317         slot = &rx_ring->slots[i];
0318         if (!slot->skb)
0319             continue;
0320         dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_FROM_DEVICE);
0321         kfree_skb(slot->skb);
0322         slot->skb = NULL;
0323     }
0324 }
0325 
0326 static int bcm4908_enet_dma_init(struct bcm4908_enet *enet)
0327 {
0328     struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
0329     struct device *dev = enet->dev;
0330     int err;
0331     int i;
0332 
0333     for (i = 0; i < rx_ring->length; i++) {
0334         err = bcm4908_enet_dma_alloc_rx_buf(enet, i);
0335         if (err) {
0336             dev_err(dev, "Failed to alloc RX buffer: %d\n", err);
0337             bcm4908_enet_dma_uninit(enet);
0338             return err;
0339         }
0340     }
0341 
0342     bcm4908_enet_dma_ring_init(enet, &enet->tx_ring);
0343     bcm4908_enet_dma_ring_init(enet, &enet->rx_ring);
0344 
0345     return 0;
0346 }
0347 
0348 static void bcm4908_enet_dma_tx_ring_enable(struct bcm4908_enet *enet,
0349                         struct bcm4908_enet_dma_ring *ring)
0350 {
0351     enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
0352 }
0353 
0354 static void bcm4908_enet_dma_tx_ring_disable(struct bcm4908_enet *enet,
0355                          struct bcm4908_enet_dma_ring *ring)
0356 {
0357     enet_write(enet, ring->cfg_block + ENET_DMA_CH_CFG, 0);
0358 }
0359 
0360 static void bcm4908_enet_dma_rx_ring_enable(struct bcm4908_enet *enet,
0361                         struct bcm4908_enet_dma_ring *ring)
0362 {
0363     enet_set(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE);
0364 }
0365 
0366 static void bcm4908_enet_dma_rx_ring_disable(struct bcm4908_enet *enet,
0367                          struct bcm4908_enet_dma_ring *ring)
0368 {
0369     unsigned long deadline;
0370     u32 tmp;
0371 
0372     enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
0373 
0374     deadline = jiffies + usecs_to_jiffies(2000);
0375     do {
0376         tmp = enet_read(enet, ring->cfg_block + ENET_DMA_CH_CFG);
0377         if (!(tmp & ENET_DMA_CH_CFG_ENABLE))
0378             return;
0379         enet_maskset(enet, ring->cfg_block + ENET_DMA_CH_CFG, ENET_DMA_CH_CFG_ENABLE, 0);
0380         usleep_range(10, 30);
0381     } while (!time_after_eq(jiffies, deadline));
0382 
0383     dev_warn(enet->dev, "Timeout waiting for DMA TX stop\n");
0384 }
0385 
0386 /***
0387  * Ethernet driver
0388  */
0389 
0390 static void bcm4908_enet_gmac_init(struct bcm4908_enet *enet)
0391 {
0392     u32 cmd;
0393 
0394     bcm4908_enet_set_mtu(enet, enet->netdev->mtu);
0395 
0396     cmd = enet_umac_read(enet, UMAC_CMD);
0397     enet_umac_write(enet, UMAC_CMD, cmd | CMD_SW_RESET);
0398     enet_umac_write(enet, UMAC_CMD, cmd & ~CMD_SW_RESET);
0399 
0400     enet_set(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH);
0401     enet_maskset(enet, ENET_FLUSH, ENET_FLUSH_RXFIFO_FLUSH | ENET_FLUSH_TXFIFO_FLUSH, 0);
0402 
0403     enet_set(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB);
0404     enet_maskset(enet, ENET_MIB_CTRL, ENET_MIB_CTRL_CLR_MIB, 0);
0405 
0406     cmd = enet_umac_read(enet, UMAC_CMD);
0407     cmd &= ~(CMD_SPEED_MASK << CMD_SPEED_SHIFT);
0408     cmd &= ~CMD_TX_EN;
0409     cmd &= ~CMD_RX_EN;
0410     cmd |= CMD_SPEED_1000 << CMD_SPEED_SHIFT;
0411     enet_umac_write(enet, UMAC_CMD, cmd);
0412 
0413     enet_maskset(enet, ENET_GMAC_STATUS,
0414              ENET_GMAC_STATUS_ETH_SPEED_MASK |
0415              ENET_GMAC_STATUS_HD |
0416              ENET_GMAC_STATUS_AUTO_CFG_EN |
0417              ENET_GMAC_STATUS_LINK_UP,
0418              ENET_GMAC_STATUS_ETH_SPEED_1000 |
0419              ENET_GMAC_STATUS_AUTO_CFG_EN |
0420              ENET_GMAC_STATUS_LINK_UP);
0421 }
0422 
0423 static irqreturn_t bcm4908_enet_irq_handler(int irq, void *dev_id)
0424 {
0425     struct bcm4908_enet *enet = dev_id;
0426     struct bcm4908_enet_dma_ring *ring;
0427 
0428     ring = (irq == enet->irq_tx) ? &enet->tx_ring : &enet->rx_ring;
0429 
0430     bcm4908_enet_dma_ring_intrs_off(enet, ring);
0431     bcm4908_enet_dma_ring_intrs_ack(enet, ring);
0432 
0433     napi_schedule(&ring->napi);
0434 
0435     return IRQ_HANDLED;
0436 }
0437 
0438 static int bcm4908_enet_open(struct net_device *netdev)
0439 {
0440     struct bcm4908_enet *enet = netdev_priv(netdev);
0441     struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;
0442     struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
0443     struct device *dev = enet->dev;
0444     int err;
0445 
0446     err = request_irq(netdev->irq, bcm4908_enet_irq_handler, 0, "enet", enet);
0447     if (err) {
0448         dev_err(dev, "Failed to request IRQ %d: %d\n", netdev->irq, err);
0449         return err;
0450     }
0451 
0452     if (enet->irq_tx > 0) {
0453         err = request_irq(enet->irq_tx, bcm4908_enet_irq_handler, 0,
0454                   "tx", enet);
0455         if (err) {
0456             dev_err(dev, "Failed to request IRQ %d: %d\n",
0457                 enet->irq_tx, err);
0458             free_irq(netdev->irq, enet);
0459             return err;
0460         }
0461     }
0462 
0463     bcm4908_enet_gmac_init(enet);
0464     bcm4908_enet_dma_reset(enet);
0465     bcm4908_enet_dma_init(enet);
0466 
0467     enet_umac_set(enet, UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
0468 
0469     enet_set(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_MASTER_EN);
0470     enet_maskset(enet, ENET_DMA_CONTROLLER_CFG, ENET_DMA_CTRL_CFG_FLOWC_CH1_EN, 0);
0471 
0472     if (enet->irq_tx > 0) {
0473         napi_enable(&tx_ring->napi);
0474         bcm4908_enet_dma_ring_intrs_ack(enet, tx_ring);
0475         bcm4908_enet_dma_ring_intrs_on(enet, tx_ring);
0476     }
0477 
0478     bcm4908_enet_dma_rx_ring_enable(enet, rx_ring);
0479     napi_enable(&rx_ring->napi);
0480     netif_carrier_on(netdev);
0481     netif_start_queue(netdev);
0482     bcm4908_enet_dma_ring_intrs_ack(enet, rx_ring);
0483     bcm4908_enet_dma_ring_intrs_on(enet, rx_ring);
0484 
0485     return 0;
0486 }
0487 
0488 static int bcm4908_enet_stop(struct net_device *netdev)
0489 {
0490     struct bcm4908_enet *enet = netdev_priv(netdev);
0491     struct bcm4908_enet_dma_ring *tx_ring = &enet->tx_ring;
0492     struct bcm4908_enet_dma_ring *rx_ring = &enet->rx_ring;
0493 
0494     netif_stop_queue(netdev);
0495     netif_carrier_off(netdev);
0496     napi_disable(&rx_ring->napi);
0497     napi_disable(&tx_ring->napi);
0498 
0499     bcm4908_enet_dma_rx_ring_disable(enet, &enet->rx_ring);
0500     bcm4908_enet_dma_tx_ring_disable(enet, &enet->tx_ring);
0501 
0502     bcm4908_enet_dma_uninit(enet);
0503 
0504     free_irq(enet->irq_tx, enet);
0505     free_irq(enet->netdev->irq, enet);
0506 
0507     return 0;
0508 }
0509 
0510 static int bcm4908_enet_start_xmit(struct sk_buff *skb, struct net_device *netdev)
0511 {
0512     struct bcm4908_enet *enet = netdev_priv(netdev);
0513     struct bcm4908_enet_dma_ring *ring = &enet->tx_ring;
0514     struct bcm4908_enet_dma_ring_slot *slot;
0515     struct device *dev = enet->dev;
0516     struct bcm4908_enet_dma_ring_bd *buf_desc;
0517     int free_buf_descs;
0518     u32 tmp;
0519 
0520     /* Free transmitted skbs */
0521     if (enet->irq_tx < 0 &&
0522         !(le32_to_cpu(ring->buf_desc[ring->read_idx].ctl) & DMA_CTL_STATUS_OWN))
0523         napi_schedule(&enet->tx_ring.napi);
0524 
0525     /* Don't use the last empty buf descriptor */
0526     if (ring->read_idx <= ring->write_idx)
0527         free_buf_descs = ring->read_idx - ring->write_idx + ring->length;
0528     else
0529         free_buf_descs = ring->read_idx - ring->write_idx;
0530     if (free_buf_descs < 2) {
0531         netif_stop_queue(netdev);
0532         return NETDEV_TX_BUSY;
0533     }
0534 
0535     /* Hardware removes OWN bit after sending data */
0536     buf_desc = &ring->buf_desc[ring->write_idx];
0537     if (unlikely(le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)) {
0538         netif_stop_queue(netdev);
0539         return NETDEV_TX_BUSY;
0540     }
0541 
0542     slot = &ring->slots[ring->write_idx];
0543     slot->skb = skb;
0544     slot->len = skb->len;
0545     slot->dma_addr = dma_map_single(dev, skb->data, skb->len, DMA_TO_DEVICE);
0546     if (unlikely(dma_mapping_error(dev, slot->dma_addr)))
0547         return NETDEV_TX_BUSY;
0548 
0549     tmp = skb->len << DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
0550     tmp |= DMA_CTL_STATUS_OWN;
0551     tmp |= DMA_CTL_STATUS_SOP;
0552     tmp |= DMA_CTL_STATUS_EOP;
0553     tmp |= DMA_CTL_STATUS_APPEND_CRC;
0554     if (ring->write_idx + 1 == ring->length - 1)
0555         tmp |= DMA_CTL_STATUS_WRAP;
0556 
0557     buf_desc->addr = cpu_to_le32((uint32_t)slot->dma_addr);
0558     buf_desc->ctl = cpu_to_le32(tmp);
0559 
0560     bcm4908_enet_dma_tx_ring_enable(enet, &enet->tx_ring);
0561 
0562     if (++ring->write_idx == ring->length - 1)
0563         ring->write_idx = 0;
0564     enet->netdev->stats.tx_bytes += skb->len;
0565     enet->netdev->stats.tx_packets++;
0566 
0567     return NETDEV_TX_OK;
0568 }
0569 
0570 static int bcm4908_enet_poll_rx(struct napi_struct *napi, int weight)
0571 {
0572     struct bcm4908_enet_dma_ring *rx_ring = container_of(napi, struct bcm4908_enet_dma_ring, napi);
0573     struct bcm4908_enet *enet = container_of(rx_ring, struct bcm4908_enet, rx_ring);
0574     struct device *dev = enet->dev;
0575     int handled = 0;
0576 
0577     while (handled < weight) {
0578         struct bcm4908_enet_dma_ring_bd *buf_desc;
0579         struct bcm4908_enet_dma_ring_slot slot;
0580         u32 ctl;
0581         int len;
0582         int err;
0583 
0584         buf_desc = &enet->rx_ring.buf_desc[enet->rx_ring.read_idx];
0585         ctl = le32_to_cpu(buf_desc->ctl);
0586         if (ctl & DMA_CTL_STATUS_OWN)
0587             break;
0588 
0589         slot = enet->rx_ring.slots[enet->rx_ring.read_idx];
0590 
0591         /* Provide new buffer before unpinning the old one */
0592         err = bcm4908_enet_dma_alloc_rx_buf(enet, enet->rx_ring.read_idx);
0593         if (err)
0594             break;
0595 
0596         if (++enet->rx_ring.read_idx == enet->rx_ring.length)
0597             enet->rx_ring.read_idx = 0;
0598 
0599         len = (ctl & DMA_CTL_LEN_DESC_BUFLENGTH) >> DMA_CTL_LEN_DESC_BUFLENGTH_SHIFT;
0600 
0601         if (len < ETH_ZLEN ||
0602             (ctl & (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) != (DMA_CTL_STATUS_SOP | DMA_CTL_STATUS_EOP)) {
0603             kfree_skb(slot.skb);
0604             enet->netdev->stats.rx_dropped++;
0605             break;
0606         }
0607 
0608         dma_unmap_single(dev, slot.dma_addr, slot.len, DMA_FROM_DEVICE);
0609 
0610         skb_put(slot.skb, len - ETH_FCS_LEN);
0611         slot.skb->protocol = eth_type_trans(slot.skb, enet->netdev);
0612         netif_receive_skb(slot.skb);
0613 
0614         enet->netdev->stats.rx_packets++;
0615         enet->netdev->stats.rx_bytes += len;
0616 
0617         handled++;
0618     }
0619 
0620     if (handled < weight) {
0621         napi_complete_done(napi, handled);
0622         bcm4908_enet_dma_ring_intrs_on(enet, rx_ring);
0623     }
0624 
0625     /* Hardware could disable ring if it run out of descriptors */
0626     bcm4908_enet_dma_rx_ring_enable(enet, &enet->rx_ring);
0627 
0628     return handled;
0629 }
0630 
0631 static int bcm4908_enet_poll_tx(struct napi_struct *napi, int weight)
0632 {
0633     struct bcm4908_enet_dma_ring *tx_ring = container_of(napi, struct bcm4908_enet_dma_ring, napi);
0634     struct bcm4908_enet *enet = container_of(tx_ring, struct bcm4908_enet, tx_ring);
0635     struct bcm4908_enet_dma_ring_bd *buf_desc;
0636     struct bcm4908_enet_dma_ring_slot *slot;
0637     struct device *dev = enet->dev;
0638     int handled = 0;
0639 
0640     while (handled < weight && tx_ring->read_idx != tx_ring->write_idx) {
0641         buf_desc = &tx_ring->buf_desc[tx_ring->read_idx];
0642         if (le32_to_cpu(buf_desc->ctl) & DMA_CTL_STATUS_OWN)
0643             break;
0644         slot = &tx_ring->slots[tx_ring->read_idx];
0645 
0646         dma_unmap_single(dev, slot->dma_addr, slot->len, DMA_TO_DEVICE);
0647         dev_kfree_skb(slot->skb);
0648         if (++tx_ring->read_idx == tx_ring->length)
0649             tx_ring->read_idx = 0;
0650 
0651         handled++;
0652     }
0653 
0654     if (handled < weight) {
0655         napi_complete_done(napi, handled);
0656         bcm4908_enet_dma_ring_intrs_on(enet, tx_ring);
0657     }
0658 
0659     if (netif_queue_stopped(enet->netdev))
0660         netif_wake_queue(enet->netdev);
0661 
0662     return handled;
0663 }
0664 
0665 static int bcm4908_enet_change_mtu(struct net_device *netdev, int new_mtu)
0666 {
0667     struct bcm4908_enet *enet = netdev_priv(netdev);
0668 
0669     bcm4908_enet_set_mtu(enet, new_mtu);
0670 
0671     return 0;
0672 }
0673 
0674 static const struct net_device_ops bcm4908_enet_netdev_ops = {
0675     .ndo_open = bcm4908_enet_open,
0676     .ndo_stop = bcm4908_enet_stop,
0677     .ndo_start_xmit = bcm4908_enet_start_xmit,
0678     .ndo_set_mac_address = eth_mac_addr,
0679     .ndo_change_mtu = bcm4908_enet_change_mtu,
0680 };
0681 
0682 static int bcm4908_enet_probe(struct platform_device *pdev)
0683 {
0684     struct device *dev = &pdev->dev;
0685     struct net_device *netdev;
0686     struct bcm4908_enet *enet;
0687     int err;
0688 
0689     netdev = devm_alloc_etherdev(dev, sizeof(*enet));
0690     if (!netdev)
0691         return -ENOMEM;
0692 
0693     enet = netdev_priv(netdev);
0694     enet->dev = dev;
0695     enet->netdev = netdev;
0696 
0697     enet->base = devm_platform_ioremap_resource(pdev, 0);
0698     if (IS_ERR(enet->base)) {
0699         dev_err(dev, "Failed to map registers: %ld\n", PTR_ERR(enet->base));
0700         return PTR_ERR(enet->base);
0701     }
0702 
0703     netdev->irq = platform_get_irq_byname(pdev, "rx");
0704     if (netdev->irq < 0)
0705         return netdev->irq;
0706 
0707     enet->irq_tx = platform_get_irq_byname(pdev, "tx");
0708 
0709     err = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
0710     if (err)
0711         return err;
0712 
0713     err = bcm4908_enet_dma_alloc(enet);
0714     if (err)
0715         return err;
0716 
0717     SET_NETDEV_DEV(netdev, &pdev->dev);
0718     err = of_get_ethdev_address(dev->of_node, netdev);
0719     if (err)
0720         eth_hw_addr_random(netdev);
0721     netdev->netdev_ops = &bcm4908_enet_netdev_ops;
0722     netdev->min_mtu = ETH_ZLEN;
0723     netdev->mtu = ETH_DATA_LEN;
0724     netdev->max_mtu = ENET_MTU_MAX;
0725     netif_napi_add_tx(netdev, &enet->tx_ring.napi, bcm4908_enet_poll_tx);
0726     netif_napi_add(netdev, &enet->rx_ring.napi, bcm4908_enet_poll_rx, NAPI_POLL_WEIGHT);
0727 
0728     err = register_netdev(netdev);
0729     if (err) {
0730         bcm4908_enet_dma_free(enet);
0731         return err;
0732     }
0733 
0734     platform_set_drvdata(pdev, enet);
0735 
0736     return 0;
0737 }
0738 
0739 static int bcm4908_enet_remove(struct platform_device *pdev)
0740 {
0741     struct bcm4908_enet *enet = platform_get_drvdata(pdev);
0742 
0743     unregister_netdev(enet->netdev);
0744     netif_napi_del(&enet->rx_ring.napi);
0745     netif_napi_del(&enet->tx_ring.napi);
0746     bcm4908_enet_dma_free(enet);
0747 
0748     return 0;
0749 }
0750 
0751 static const struct of_device_id bcm4908_enet_of_match[] = {
0752     { .compatible = "brcm,bcm4908-enet"},
0753     {},
0754 };
0755 
0756 static struct platform_driver bcm4908_enet_driver = {
0757     .driver = {
0758         .name = "bcm4908_enet",
0759         .of_match_table = bcm4908_enet_of_match,
0760     },
0761     .probe  = bcm4908_enet_probe,
0762     .remove = bcm4908_enet_remove,
0763 };
0764 module_platform_driver(bcm4908_enet_driver);
0765 
0766 MODULE_LICENSE("GPL v2");
0767 MODULE_DEVICE_TABLE(of, bcm4908_enet_of_match);
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