ethernet/arc/emac.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
0004  *
0005  * Registers and bits definitions of ARC EMAC
0006  */
0007
0008 #ifndef ARC_EMAC_H
0009 #define ARC_EMAC_H
0010
0011 #include <linux/device.h>
0012 #include <linux/dma-mapping.h>
0013 #include <linux/netdevice.h>
0014 #include <linux/phy.h>
0015 #include <linux/clk.h>
0016
0017 /* STATUS and ENABLE Register bit masks */
0018 #define TXINT_MASK  (1 << 0)    /* Transmit interrupt */
0019 #define RXINT_MASK  (1 << 1)    /* Receive interrupt */
0020 #define ERR_MASK    (1 << 2)    /* Error interrupt */
0021 #define TXCH_MASK   (1 << 3)    /* Transmit chaining error interrupt */
0022 #define MSER_MASK   (1 << 4)    /* Missed packet counter error */
0023 #define RXCR_MASK   (1 << 8)    /* RXCRCERR counter rolled over  */
0024 #define RXFR_MASK   (1 << 9)    /* RXFRAMEERR counter rolled over */
0025 #define RXFL_MASK   (1 << 10)   /* RXOFLOWERR counter rolled over */
0026 #define MDIO_MASK   (1 << 12)   /* MDIO complete interrupt */
0027 #define TXPL_MASK   (1 << 31)   /* Force polling of BD by EMAC */
0028
0029 /* CONTROL Register bit masks */
0030 #define EN_MASK     (1 << 0)    /* VMAC enable */
0031 #define TXRN_MASK   (1 << 3)    /* TX enable */
0032 #define RXRN_MASK   (1 << 4)    /* RX enable */
0033 #define DSBC_MASK   (1 << 8)    /* Disable receive broadcast */
0034 #define ENFL_MASK   (1 << 10)   /* Enable Full-duplex */
0035 #define PROM_MASK   (1 << 11)   /* Promiscuous mode */
0036
0037 /* Buffer descriptor INFO bit masks */
0038 #define OWN_MASK    (1 << 31)   /* 0-CPU or 1-EMAC owns buffer */
0039 #define FIRST_MASK  (1 << 16)   /* First buffer in chain */
0040 #define LAST_MASK   (1 << 17)   /* Last buffer in chain */
0041 #define LEN_MASK    0x000007FF  /* last 11 bits */
0042 #define CRLS        (1 << 21)
0043 #define DEFR        (1 << 22)
0044 #define DROP        (1 << 23)
0045 #define RTRY        (1 << 24)
0046 #define LTCL        (1 << 28)
0047 #define UFLO        (1 << 29)
0048
0049 #define FOR_EMAC    OWN_MASK
0050 #define FOR_CPU     0
0051
0052 /* ARC EMAC register set combines entries for MAC and MDIO */
0053 enum {
0054     R_ID = 0,
0055     R_STATUS,
0056     R_ENABLE,
0057     R_CTRL,
0058     R_POLLRATE,
0059     R_RXERR,
0060     R_MISS,
0061     R_TX_RING,
0062     R_RX_RING,
0063     R_ADDRL,
0064     R_ADDRH,
0065     R_LAFL,
0066     R_LAFH,
0067     R_MDIO,
0068 };
0069
0070 #define TX_TIMEOUT      (400 * HZ / 1000) /* Transmission timeout */
0071
0072 #define ARC_EMAC_NAPI_WEIGHT    40      /* Workload for NAPI */
0073
0074 #define EMAC_BUFFER_SIZE    1536        /* EMAC buffer size */
0075
0076 /**
0077  * struct arc_emac_bd - EMAC buffer descriptor (BD).
0078  *
0079  * @info:   Contains status information on the buffer itself.
0080  * @data:   32-bit byte addressable pointer to the packet data.
0081  */
0082 struct arc_emac_bd {
0083     __le32 info;
0084     dma_addr_t data;
0085 };
0086
0087 /* Number of Rx/Tx BD's */
0088 #define RX_BD_NUM   128
0089 #define TX_BD_NUM   128
0090
0091 #define RX_RING_SZ  (RX_BD_NUM * sizeof(struct arc_emac_bd))
0092 #define TX_RING_SZ  (TX_BD_NUM * sizeof(struct arc_emac_bd))
0093
0094 /**
0095  * struct buffer_state - Stores Rx/Tx buffer state.
0096  * @sk_buff:    Pointer to socket buffer.
0097  * @addr:   Start address of DMA-mapped memory region.
0098  * @len:    Length of DMA-mapped memory region.
0099  */
0100 struct buffer_state {
0101     struct sk_buff *skb;
0102     DEFINE_DMA_UNMAP_ADDR(addr);
0103     DEFINE_DMA_UNMAP_LEN(len);
0104 };
0105
0106 struct arc_emac_mdio_bus_data {
0107     struct gpio_desc *reset_gpio;
0108     int msec;
0109 };
0110
0111 /**
0112  * struct arc_emac_priv - Storage of EMAC's private information.
0113  * @dev:    Pointer to the current device.
0114  * @phy_dev:    Pointer to attached PHY device.
0115  * @bus:    Pointer to the current MII bus.
0116  * @regs:   Base address of EMAC memory-mapped control registers.
0117  * @napi:   Structure for NAPI.
0118  * @rxbd:   Pointer to Rx BD ring.
0119  * @txbd:   Pointer to Tx BD ring.
0120  * @rxbd_dma:   DMA handle for Rx BD ring.
0121  * @txbd_dma:   DMA handle for Tx BD ring.
0122  * @rx_buff:    Storage for Rx buffers states.
0123  * @tx_buff:    Storage for Tx buffers states.
0124  * @txbd_curr:  Index of Tx BD to use on the next "ndo_start_xmit".
0125  * @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
0126  * @last_rx_bd: Index of the last Rx BD we've got from EMAC.
0127  * @link:   PHY's last seen link state.
0128  * @duplex: PHY's last set duplex mode.
0129  * @speed:  PHY's last set speed.
0130  */
0131 struct arc_emac_priv {
0132     const char *drv_name;
0133     void (*set_mac_speed)(void *priv, unsigned int speed);
0134
0135     /* Devices */
0136     struct device *dev;
0137     struct mii_bus *bus;
0138     struct arc_emac_mdio_bus_data bus_data;
0139
0140     void __iomem *regs;
0141     struct clk *clk;
0142
0143     struct napi_struct napi;
0144
0145     struct arc_emac_bd *rxbd;
0146     struct arc_emac_bd *txbd;
0147
0148     dma_addr_t rxbd_dma;
0149     dma_addr_t txbd_dma;
0150
0151     struct buffer_state rx_buff[RX_BD_NUM];
0152     struct buffer_state tx_buff[TX_BD_NUM];
0153     unsigned int txbd_curr;
0154     unsigned int txbd_dirty;
0155
0156     unsigned int last_rx_bd;
0157
0158     unsigned int link;
0159     unsigned int duplex;
0160     unsigned int speed;
0161
0162     unsigned int rx_missed_errors;
0163 };
0164
0165 /**
0166  * arc_reg_set - Sets EMAC register with provided value.
0167  * @priv:   Pointer to ARC EMAC private data structure.
0168  * @reg:    Register offset from base address.
0169  * @value:  Value to set in register.
0170  */
0171 static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
0172 {
0173     iowrite32(value, priv->regs + reg * sizeof(int));
0174 }
0175
0176 /**
0177  * arc_reg_get - Gets value of specified EMAC register.
0178  * @priv:   Pointer to ARC EMAC private data structure.
0179  * @reg:    Register offset from base address.
0180  *
0181  * returns: Value of requested register.
0182  */
0183 static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
0184 {
0185     return ioread32(priv->regs + reg * sizeof(int));
0186 }
0187
0188 /**
0189  * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
0190  * @priv:   Pointer to ARC EMAC private data structure.
0191  * @reg:    Register offset from base address.
0192  * @mask:   Mask to apply to specified register.
0193  *
0194  * This function reads initial register value, then applies provided mask
0195  * to it and then writes register back.
0196  */
0197 static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
0198 {
0199     unsigned int value = arc_reg_get(priv, reg);
0200
0201     arc_reg_set(priv, reg, value | mask);
0202 }
0203
0204 /**
0205  * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
0206  * @priv:   Pointer to ARC EMAC private data structure.
0207  * @reg:    Register offset from base address.
0208  * @mask:   Mask to apply to specified register.
0209  *
0210  * This function reads initial register value, then applies provided mask
0211  * to it and then writes register back.
0212  */
0213 static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
0214 {
0215     unsigned int value = arc_reg_get(priv, reg);
0216
0217     arc_reg_set(priv, reg, value & ~mask);
0218 }
0219
0220 int arc_mdio_probe(struct arc_emac_priv *priv);
0221 int arc_mdio_remove(struct arc_emac_priv *priv);
0222 int arc_emac_probe(struct net_device *ndev, int interface);
0223 int arc_emac_remove(struct net_device *ndev);
0224
0225 #endif /* ARC_EMAC_H */