ethernet/apple/mace.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * mace.h - definitions for the registers in the Am79C940 MACE
0004  * (Medium Access Control for Ethernet) controller.
0005  *
0006  * Copyright (C) 1996 Paul Mackerras.
0007  */
0008
0009 #define REG(x)  volatile unsigned char x; char x ## _pad[15]
0010
0011 struct mace {
0012     REG(rcvfifo);       /* receive FIFO */
0013     REG(xmtfifo);       /* transmit FIFO */
0014     REG(xmtfc);     /* transmit frame control */
0015     REG(xmtfs);     /* transmit frame status */
0016     REG(xmtrc);     /* transmit retry count */
0017     REG(rcvfc);     /* receive frame control */
0018     REG(rcvfs);     /* receive frame status (4 bytes) */
0019     REG(fifofc);        /* FIFO frame count */
0020     REG(ir);        /* interrupt register */
0021     REG(imr);       /* interrupt mask register */
0022     REG(pr);        /* poll register */
0023     REG(biucc);     /* bus interface unit config control */
0024     REG(fifocc);        /* FIFO configuration control */
0025     REG(maccc);     /* medium access control config control */
0026     REG(plscc);     /* phys layer signalling config control */
0027     REG(phycc);     /* physical configuration control */
0028     REG(chipid_lo);     /* chip ID, lsb */
0029     REG(chipid_hi);     /* chip ID, msb */
0030     REG(iac);       /* internal address config */
0031     REG(reg19);
0032     REG(ladrf);     /* logical address filter (8 bytes) */
0033     REG(padr);      /* physical address (6 bytes) */
0034     REG(reg22);
0035     REG(reg23);
0036     REG(mpc);       /* missed packet count (clears when read) */
0037     REG(reg25);
0038     REG(rntpc);     /* runt packet count (clears when read) */
0039     REG(rcvcc);     /* recv collision count (clears when read) */
0040     REG(reg28);
0041     REG(utr);       /* user test reg */
0042     REG(reg30);
0043     REG(reg31);
0044 };
0045
0046 /* Bits in XMTFC */
0047 #define DRTRY       0x80    /* don't retry transmission after collision */
0048 #define DXMTFCS     0x08    /* don't append FCS to transmitted frame */
0049 #define AUTO_PAD_XMIT   0x01    /* auto-pad short packets on transmission */
0050
0051 /* Bits in XMTFS: only valid when XMTSV is set in PR and XMTFS */
0052 #define XMTSV       0x80    /* transmit status (i.e. XMTFS) valid */
0053 #define UFLO        0x40    /* underflow - xmit fifo ran dry */
0054 #define LCOL        0x20    /* late collision (transmission aborted) */
0055 #define MORE        0x10    /* 2 or more retries needed to xmit frame */
0056 #define ONE     0x08    /* 1 retry needed to xmit frame */
0057 #define DEFER       0x04    /* MACE had to defer xmission (enet busy) */
0058 #define LCAR        0x02    /* loss of carrier (transmission aborted) */
0059 #define RTRY        0x01    /* too many retries (transmission aborted) */
0060
0061 /* Bits in XMTRC: only valid when XMTSV is set in PR (and XMTFS) */
0062 #define EXDEF       0x80    /* had to defer for excessive time */
0063 #define RETRY_MASK  0x0f    /* number of retries (0 - 15) */
0064
0065 /* Bits in RCVFC */
0066 #define LLRCV       0x08    /* low latency receive: early DMA request */
0067 #define M_RBAR      0x04    /* sets function of EAM/R pin */
0068 #define AUTO_STRIP_RCV  0x01    /* auto-strip short LLC frames on recv */
0069
0070 /*
0071  * Bits in RCVFS.  After a frame is received, four bytes of status
0072  * are automatically read from this register and appended to the frame
0073  * data in memory.  These are:
0074  * Byte 0 and 1: message byte count and frame status
0075  * Byte 2: runt packet count
0076  * Byte 3: receive collision count
0077  */
0078 #define RS_OFLO     0x8000  /* receive FIFO overflowed */
0079 #define RS_CLSN     0x4000  /* received frame suffered (late) collision */
0080 #define RS_FRAMERR  0x2000  /* framing error flag */
0081 #define RS_FCSERR   0x1000  /* frame had FCS error */
0082 #define RS_COUNT    0x0fff  /* mask for byte count field */
0083
0084 /* Bits (fields) in FIFOFC */
0085 #define RCVFC_SH    4   /* receive frame count in FIFO */
0086 #define RCVFC_MASK  0x0f
0087 #define XMTFC_SH    0   /* transmit frame count in FIFO */
0088 #define XMTFC_MASK  0x0f
0089
0090 /*
0091  * Bits in IR and IMR.  The IR clears itself when read.
0092  * Setting a bit in the IMR will disable the corresponding interrupt.
0093  */
0094 #define JABBER      0x80    /* jabber error - 10baseT xmission too long */
0095 #define BABBLE      0x40    /* babble - xmitter xmitting for too long */
0096 #define CERR        0x20    /* collision err - no SQE test (heartbeat) */
0097 #define RCVCCO      0x10    /* RCVCC overflow */
0098 #define RNTPCO      0x08    /* RNTPC overflow */
0099 #define MPCO        0x04    /* MPC overflow */
0100 #define RCVINT      0x02    /* receive interrupt */
0101 #define XMTINT      0x01    /* transmitter interrupt */
0102
0103 /* Bits in PR */
0104 #define XMTSV       0x80    /* XMTFS valid (same as in XMTFS) */
0105 #define TDTREQ      0x40    /* set when xmit fifo is requesting data */
0106 #define RDTREQ      0x20    /* set when recv fifo requests data xfer */
0107
0108 /* Bits in BIUCC */
0109 #define BSWP        0x40    /* byte swap, i.e. big-endian bus */
0110 #define XMTSP_4     0x00    /* start xmitting when 4 bytes in FIFO */
0111 #define XMTSP_16    0x10    /* start xmitting when 16 bytes in FIFO */
0112 #define XMTSP_64    0x20    /* start xmitting when 64 bytes in FIFO */
0113 #define XMTSP_112   0x30    /* start xmitting when 112 bytes in FIFO */
0114 #define SWRST       0x01    /* software reset */
0115
0116 /* Bits in FIFOCC */
0117 #define XMTFW_8     0x00    /* xmit fifo watermark = 8 words free */
0118 #define XMTFW_16    0x40    /*  16 words free */
0119 #define XMTFW_32    0x80    /*  32 words free */
0120 #define RCVFW_16    0x00    /* recv fifo watermark = 16 bytes avail */
0121 #define RCVFW_32    0x10    /*  32 bytes avail */
0122 #define RCVFW_64    0x20    /*  64 bytes avail */
0123 #define XMTFWU      0x08    /* xmit fifo watermark update enable */
0124 #define RCVFWU      0x04    /* recv fifo watermark update enable */
0125 #define XMTBRST     0x02    /* enable transmit burst mode */
0126 #define RCVBRST     0x01    /* enable receive burst mode */
0127
0128 /* Bits in MACCC */
0129 #define PROM        0x80    /* promiscuous mode */
0130 #define DXMT2PD     0x40    /* disable xmit two-part deferral algorithm */
0131 #define EMBA        0x20    /* enable modified backoff algorithm */
0132 #define DRCVPA      0x08    /* disable receiving physical address */
0133 #define DRCVBC      0x04    /* disable receiving broadcasts */
0134 #define ENXMT       0x02    /* enable transmitter */
0135 #define ENRCV       0x01    /* enable receiver */
0136
0137 /* Bits in PLSCC */
0138 #define XMTSEL      0x08    /* select DO+/DO- state when idle */
0139 #define PORTSEL_AUI 0x00    /* select AUI port */
0140 #define PORTSEL_10T 0x02    /* select 10Base-T port */
0141 #define PORTSEL_DAI 0x04    /* select DAI port */
0142 #define PORTSEL_GPSI    0x06    /* select GPSI port */
0143 #define ENPLSIO     0x01    /* enable optional PLS I/O pins */
0144
0145 /* Bits in PHYCC */
0146 #define LNKFL       0x80    /* reports 10Base-T link failure */
0147 #define DLNKTST     0x40    /* disable 10Base-T link test */
0148 #define REVPOL      0x20    /* 10Base-T receiver polarity reversed */
0149 #define DAPC        0x10    /* disable auto receiver polarity correction */
0150 #define LRT     0x08    /* low receive threshold for long links */
0151 #define ASEL        0x04    /* auto-select AUI or 10Base-T port */
0152 #define RWAKE       0x02    /* remote wake function */
0153 #define AWAKE       0x01    /* auto wake function */
0154
0155 /* Bits in IAC */
0156 #define ADDRCHG     0x80    /* request address change */
0157 #define PHYADDR     0x04    /* access physical address */
0158 #define LOGADDR     0x02    /* access multicast filter */
0159
0160 /* Bits in UTR */
0161 #define RTRE        0x80    /* reserved test register enable. DON'T SET. */
0162 #define RTRD        0x40    /* reserved test register disable.  Sticky */
0163 #define RPAC        0x20    /* accept runt packets */
0164 #define FCOLL       0x10    /* force collision */
0165 #define RCVFCSE     0x08    /* receive FCS enable */
0166 #define LOOP_NONE   0x00    /* no loopback */
0167 #define LOOP_EXT    0x02    /* external loopback */
0168 #define LOOP_INT    0x04    /* internal loopback, excludes MENDEC */
0169 #define LOOP_MENDEC 0x06    /* internal loopback, includes MENDEC */